FPGA Based Multiprocessor Hardware & Software system for
Sensor network with Crypto Application
FPGA Based Multiprocessor Hardware & Software system for
Sensor network with Crypto Application
Presented By,
SUMA M R
Description
Multiprocessor
Any system that incorporates two or more microprocessors working
together to perform one or more related tasks is commonly referred
to as a multiprocessor System.
By using multi-processor systems the required performance can be
achieved at lower power consumption than in single-processor
systems.
The most power efficient solution would be to use
application-specific hardware, but it takes a lot of effort to
design them.
Multiprocessor systems provide a reusable and versatile yet
energy efficient solution with much less design effort.
Crypto Application
AES operates on a 44 column-major order matrix of bytes, termed
thestate, although some versions of Rijndael have a larger block
size and have additional columns in the state.
The key size used for an AES cipher specifies the number of
repetitions of transformation rounds that convert the input, called
the plaintext, into the final output, called the ciphertext.
Advance Encryption Standard
The number of cycles of repetition are as follows:
10 cycles of repetition for 128-bit keys.
12 cycles of repetition for 192-bit keys.
14 cycles of repetition for 256-bit keys.
The input to the AES encryption and decryption algorithms is a
single 128-bit block, depicted as a square matrix of bytes .
This block is copied into the State array, which is modified at
each stage of encryption or decryption.
All of the steps are easily reversed, and can be efficiently
implemented using XORs & table lookups.
NIOS II
The Altera Nios II processor and SOPC Builder tool can quickly
design and build multiprocessor systems that share resources.
A Nios II processor system typically refers to a system with a
processor core, a set of on-chip peripherals, on-chip memory and
interfaces to off-chip memory all implemented on a single Altera
device.
A Nios II processor system is equivalent to a microcontroller or
computer on a chip that includes a processor and a combination of
peripherals and memory on a single chip.
The Nios II architecture describes an instruction set
architecture (ISA).
The ISA in turn necessitates a set of functional units that
implement the instructions.
A Nios II processor core is a hardware design that implements
the Nios II instruction set and supports the functional units
described in this document.
The processor core does not include peripherals or the
connection logic to the outside world.
It includes only the circuits required to implement the Nios II
architecture.
FIELD PROGRAMMABLE GATE ARRAY
The field-programmable gate array (FPGA) is a semiconductor
device that can be programmed after manufacturing.
Instead of being restricted to any predetermined hardware
function, an FPGA allows you to program product features and
functions, adapt to new standards, and reconfigure hardware for
specific applications .
The product has been installed in the fieldhence the name
"field-programmable".
Cyclone II FPGA
Cyclone device family, Altera Cyclone II FPGAs extend the
low-cost FPGA density range to 68,416 logic elements (LEs) and
provide up to 622 usable I/O pins and up to 1.1 Mbits of embedded
memory.
Cyclone II FPGAs are manufactured on 300-mm wafers using TSMC's
90-nm low-k dielectric process to ensure rapid availability and low
cost.
By minimizing silicon area, Cyclone II devices can support
complex digital systems on a single chip at a cost that rivals that
of ASICs.
ALTERA DE2 BOARD
The AlteraDE2 Development and Education board was designed by
professors. It is an ideal board for learning about digital logic,
computer organization, and FPGAs.
It is suitable for a wide range of exercises in courses on
digital logic and computer organization, from simple tasks that
illustrate fundamental concepts to advanced designs.
SOPC BUILDER
SOPC Builder enables you to define and generate a complete
system-on-a-programmable-chip (SOPC) in much lesstime than using
traditional, manual integration methods.
The Nios II processor SOPC Builder automates the task of
integrating hardware components.
Using SOPC Builder, you specify the system components in a GUI
and SOPC Builder generates the interconnect logic
automatically.
You can also define and add custom components or select from a
list of provided components.
SOPC Builder modules are the building blocks for creating an
SOPC Builder system.
SOPC Builder modules use Avalon interfaces, such as
memory-mapped, streaming, and IRQ, for the physical connection of
components.
SOPC Builder modules use Avalon interfaces, such as
memory-mapped, streaming, and IRQ, for the physical connection of
components.
There are different types of Avalon interfaces, as described in
the Avalon Interface Specifications.
Quartus II
The Quartus II software provides a suite of tools similar to
those found in the Xilinx ISE software.
The Quartus II software allows you to perform design
implementation either by using command-line executables and
scripting, or by using the Quartus II GUI
The ISE software and the Quartus II software provide the tools
necessary to automate your FPGA design flow.
NIOS II IDE
The Nios II integrated development environment (IDE) is the
primary graphical software development tool for the Nios II family
of embedded processors.
To accomplish all software development tasks within the Nios II
IDE, including editing, building, debugging, and profiling
programs.
The IDE allows you to create single-threaded programs as well as
complex applications based on a real-time operating system (RTOS)
and middleware libraries available from Altera and third-party
vendors.
NIOS II IDE Design Flow
Create a project
Configure the project properties
Edit the C/C++ application code
Build the C/C++ application project
Run and debug the project
Profile execution performance
Store the project firmware on a target board
Import the software build tools projects
These projects are configured prior to import
Edit the C/C++ application code
Build the C/C++ application project
Run and debug the project
Profile execution performance
Store the project firmware on a target board
INPUT SPECIFICATIONS
RFID
