2013 2nd International Conference on Measurement, Information and Control

FPGA-Based Induction heating with Variable Modulus Control All-Digital Phase-Locked Loop

Research BaYou Jie Wang Songyang Li

Harbin University of Science and Technology

Harbin University of Science and Technology

Harbin University of Science and Technology

Harbin, Heilongjiang Province, China youbo@hrbustedu,cn

Harbin, Heilongjiang Province, China china, vikinglife@gmaiLcom

Harbin, Heilongjiang Province, China zixun _ 2009@yeah,net

Abstract-This paper presents a field-programmable gate

array (FPGA) implementation of an all-digital Phase-Locked

Loop with alterable modulus control that used for induction

heating power supply frequency tracking. The design is

developed using a hardware description language (Verilog HDL),

and by expanding PLL center frequency band and the use of

variable-mode control for fast tracking. It's very simple while

maintaining good accuracy and speed. Through the typical

frequency band computer simulation experiments confirmed that

the design has a wide range of phase-lock ability and a fast

frequency tracking performance to meet the load frequency

induction heating power tracking requirements.

Keywords-Induction heating; FPGA; PLL; variable modulus control

I. INTRODUCTION

In the induction heating power supply process, due to the load temperature and melt of burden and other factors, the load resonant frequency will change [1]. In order to make the power supply in the power factor is close to or equal to 1 of the quasi resonant or resonant condition, quickly and accurately track the change of the load frequency is important to the reliable operation of power [2]. Phase-locked loop (PLL) is an effective means to achieve the above control [3]. Induction heating frequency tracking usually adopts analog PLL and digital PLL design. However, the conventional PLL has complex circuit design, slow tracking, phase-locked frequency band is narrow, long development cycle and many other shortcomings [4].

As the SOC (System on Chip) technology has increasingly matured, digital phase-locked loop based on FPGA has the ease of integration, strong anti-jamming capability, and many other advantages to becoming a new direction of development But most of the traditional design is used for communication, is not suitable for induction heating power supply application directly [5]. Therefore, this paper proposes a novel induction heating power based on FPGA all-digital phase-locked loop, using Verilog language design, using the FPGA IP (Intellectual Property) core and a small amount of independent modules, the peripheral chips as much as possible integrated on a chip FPGA, and take automatic modular design to achieve more rapid frequency tracking.

978-1-4799-1392-3/13/$31.00 m013 IEEE 1099

II. INDUCTION HEATING POWER ALL-DIGITAL PHASE-

LOCKED Loop DESIGN

In this paper, on the basis of conventional digital phase­locked loop, using Counter32B and M _change underlying FPGA module with digital phase locked loop 74HC297 modules combine to achieve a new all-digital phase-locked loop induction heating power supply design. The 74HCT297 integrated K-counter, lID circuit, phase detector (XOR) and edge control phase detector (ECPD). As shown in figure 1 is the schematic of induction heating power all-digital phase­locked loop design in this paper.

M_change

elk elk PO

reset reset lock

fln fin A

fOllt n C 0

qo[7 .. 0]

PD c::J--======.J '10[7 .. 0] c:=1--------'

lock c:=1--------.J

PHASE_B

PHASE Al

PlIASE_A2

A n C

D IDOUT

ENCTR ECPD

IDCLK DIUPN

KCLK XORPO

Divider

elk Cout

reset

N[31..0]

Counter32R

fin reset

N[31..0] elk

/0 reset

fin reset elk

Fig I. Induction heating power supply all digital phase-locked loop diagram

K-counter is the equivalent of a Low-pass filter, TID circuit is the equivalent of a voltage-controlled oscillator , as shown in figure 2.

Set the phase-locked loop center frequency as fc, when

input the signal are fc and 1" , the output of the phase detetor

will be KdCfJe ,where the phase error is:

(1)

Harbin, CHINA

Fig 2. DPLL using EXCLUSIVE-OR phase detection.

K-counter is a subtraction reversible full up/down counter , the length of the up/down K-counter is digitally programmable according to the K-value. The phase detector output controls the up/down input to the K-counter. The counter is clocked by

input frequency Mfc, which is a multiple M of the loop centre

frequency fc .When the K-counter recycles up, it generates a carry pulse. Recycling while counting down generates a borrow pulse. If the carry and the borrow outputs are conceptually combined into one output that is positive for a carry and negative for a borrow, and if the K-counter is considered as a

frequency divider with the ratio Mfc 1 K , the output of the K­

counter will equal the input frequency multiplied by the division ratio. Thus the output of the K-counter is:

(2)

The carry and borrow pulses go to the increment/decrement (liD) circuit which, in the absence of any carry or borrow

pulses has an output that is 1/2 of the input clock (2Nfc). When there is a carry pulse, half a pulse will be inserted into the output of two divided-frequency signal; When there is a borrow pulse, the output of two divided-frequency signal will minus by half a pulse. Thus the output of the TID circuit will be:

h=Nfc+J;12 (3)

According to the requirement of the induction heating power supply, This paper uses the N value detection counter Counter32B to count the input signal and take the results as N­counter divider value to achieve PLL center frequency band expansion. The output of the N-counter (or the output of the phase-locked-loop) is thus:

J;, = (Nfc + h)1 N (4)

(5)

1100

As the (2), (5) shows that, the divider value of K-counter has a great impact on the performance of DPLL: a smaller value of K, will get a greater tracking step, a wider loop bandwidth and a faster phase locking speed; while a greater value of K will get a smaller tracking step, and a narrower loop bandwidth but the synchronization error is smaller and have the better inhibition effect of phase jitter.

Therefore, using M _change module quantized phase difference, take the whole process divided into fast capture zone, slow capture zone and synchronous capture zone, then set the K - value of the control words, as shown in Figure 3.

,--------------- ---------------------------------------------------------------------------------.. . . . . , Clk

' � � ii ���:�' Ii �

: �-------------------------------------------------------------------------------------------------;: Fig 3. M_change module

The detection circuit compares the signal phase, obtaining a phase error sequence qo, as shown in figure 4.

fin CPI Q I "H"

fo "H"

-Q2

Fig 4. Detection circuit

The output of the detect circuit and modulus control is based on qo. If qo>3, then DBCA=OOII, is the fast capture zone, else if 32'qo> I , then DBCA=OIOI, is the slow capture zone, else if qoSI is the synchronous capture zone, DBCA=IOOI. K-value is an integer power of two, when the control words DBCA belongs to 4'bOOOl�4'bl11l, the K as shown in table T .

TABLE I. K -COUNTER FUNCTION TABLE

D C B A K L L L L inhibited L L L H 2'

L L H L 24

L L H H 25

L H L L 26

L H L H 27 L H H L 2"

L H H H 29

H L L L 210

H L L H 2"

H L H L 2'2

H L H H 211

H H L L 214

H H L H 215

H H H L 216

H H H H 2'7

K is an integer power of two, when the control words DBCA belongs to 4'b0001�4'bllll, the K-value will be 4*2DCBA, as shown in table I .

Ill. PREPARE YOUR PAPER BEFORE STYLING

According to the circuit of each part of the functional requirements of the system, the paper using the Verilog HDL language and the top-down system design method to complete DPLL design. And take the Quartus IT and ModelSim for the source code's functional simulation and logic synthesis. In the simulation, the system clock is 50MHz, and dnup is fin the flag of fin and fo lead/lag. The following is the simulation results of M _change and DPLL.

The M _change simulation waveform is shown in figure 5,

the results show that when the sinnal hn, h, have different phase difference, M _change output a corresponding control word and a K-value to complete the automatic variable modulus control function.

Fig 5. M_change functional simulation waveforms

After completing the design and simulation of each part of the loop, then verity the whole system. Figure 6 is the simulation waveform of the fm change from 50KHz to 1KHz.

When the fin transition from 50KHz to 1 KHz, phase errorsequence is smaller than 3, the phase-locked loop in the sync capture zone, K-value is 2048, tracking time consuming 1500us, capture success.

Fig 6. Fin change from 50KHz to I KHz.

1101

Fig 7. Fin change from 20KHz to I KHz.

Figure 7 is the simulation waveform of the fin change from 20KHz to lKHz.Fin change at 232050us, and the output of qo is 591. DPLL change from the fast capture zone to the synchronous capture zone and the K-value is 2048. Over 1500.04us later, for tracking on the fm, qo :Sl.

Figure 8 is the simulation waveform of the fin change from 10KHz to 20KHz and 50KHz.Lock time is 74.94us and 29.97us, tracking success.

�

� •

� � tr ili Rii AA AA AA ili � = : � •

� � s � 164 1 U � H • 0 I � •

..,., •

, r= • r--IL r--- n -

== n I � C -

• J L -= •

• i147 U>18 11� IS))

Fig 8. Fin change from 10KHz to 20KHz and 50KHz.

Simulation results show that: The DPLL in the typical frequency of accurate phase lock feature to load the high­frequency and low-frequency changes that are has frequency tracking performance.

IV. CONCLUSION

This paper presents a new all-digital phase-locked loop design, in view of the traditional digital phase-locked loop based on FPGA expand the center frequency of the phase­locked loop and using alterable modulus control for the frequency tracking. The simulation results show that the proposed DPLL has a large track-in range, short pull-in time and high accuracy, and can be applied to the induction heating power supply frequency tracking perfectly. The design has the characteristic of high integration, concision and simpleness. The design is completed by the FPGA IP core and a small amount of independent module.

ACKNOWLEDGMENT

This work is partially supported by Harbin special funds for technological innovation research project (Project Number: 2011RFXXG008). The authors also gratefully acknowledge the helpful comments and suggestions of the reviewers, which have improved the presentation.

REFERENCES

[1] Yabin Li, Yonglong Peng, "FPGA-based all digital phase-locked loop controlled induction heating power supply operating at optimized ZVS mode," IEEE Region 10 Annual International Conference, 14-17 Nov. 2006, pp. 1-4.

[2] S. Dash, A.K. Sahoo, and B.C. Babu, "Design and Implementation of FPGA based Linear All Digital Phase-Locked Loop," IEEE India Conference, INDICON 2012, pp. 280-285.

[3] Xiao Shuai, Sun Jianbo, Geng Hua and Wu Jian, "FPGA Based Ratio Changeable All Digital Phase-Locked-Loop," Transactions of china electrotechnical society, vol. 27 No. 4, Apr. 2012, pp. 153-158.

[4] M. Kumm, H. Klingbeil, and P. Zipf, "An FPGA-Based Linear AII­Digital Phase-Locked Loop," IEEE Transactions on Circuits and Systems, Vo1.57, Issue:9, 2010, pp. 2487-2497.

[5] Guo Xiaoqiang, Wu Weiyang, Chen Zhe, "Multiple complex­coefficient-filter based phase-locked loop and synchronization technique for three-phase grid-interfaced converters in distributed utility networks," IEEE Transactions on Industrial Electronics, 2011, 58 (4). pp. 1194-1204.

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