Foundation Introduction Series User Guidefivedots.coe.psu.ac.th/~cj/csd/resources/manuals/Xilinx/fsuguide.pdf · Schematic Design Entry HDL Design Entry and Synthesis State ... Post-Implementation

Foundation Series User Guide Printed in U.S.A.

FoundationSeries UserGuide

Introduction

Design Methodologies

Foundation Toolset

Schematic Design Entry

HDL Design Entry andSynthesis

State Machine Designs

LogiBLOX

Functional Simulation

An Introduction to DesignImplementation

Post-ImplementationTiming Simulation

Glossary

Foundation Constraints

Foundation Series User Guide

Xilinx Development System

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R



FoundationSeries UserGuide

Instantiated Components

Foundation Series User Guide i

Preface

About the ManualThis Foundation Series User Guide provides a detailed description ofthe Foundation™ design methodologies, design entry tools, and bothfunctional and timing simulation. The manual also briefly describesthe Xilinx design implementation tools. Detailed descriptions of thedesign implementation tools can be found in the two DynaText®

online documents, Design Manager/Flow Engine Reference/User Guideand Development System Reference Guide.

Foundation Series User Guide ContentsThis guide covers the following topics:

• Chapter 1, “Introduction,” lists supported architectures,platforms, and features. The chapter also includes detaileddesign flows for FPGAs and CPLDs and describes new featuresof the online help.

• Chapter 2, “Design Methodologies,” describes various designmethodologies for top-level schematic designs, top-level VHDLdesigns, and state machine designs.

• Chapter 3, “Foundation Toolset,” explains how to access thevarious Foundation design tools from the Project Manager andbriefly describes each tool and its function.

• Chapter 4, “Schematic Design Entry,” explains how to manageyour schematic designs, create hierarchical schematic designs,manually export a netlist, and create a schematic from a netlist.


ii Xilinx Development System

• Chapter 5, “HDL Design Entry and Synthesis,” describes how tocreate top-level VHDL designs, explains how to manage largedesigns, and discusses advanced design techniques.

• Chapter 6, “State Machine Designs,” explains the basicoperations for creating state machine designs.

• Chapter 7, “LogiBLOX,” explains how to create LogiBLOX™

modules and how to use them in schematic and HDL designs.

• Chapter 8, “Functional Simulation,” describes the basicfunctional simulation process and explains when to performfunctional simulation with a top-down or bottom-upmethodology.

• Chapter 9, “An Introduction to Design Implementation,” brieflydescribes how to implement your design in the Xilinx DesignManager. The chapter also describes how to select various designoptions in the Implementation Options dialog box, and how toperform a static timing analysis.

• Chapter 10, “Post-implementation Timing Simulation,” explainshow to generate a timing-annotated netlist and describes thebasic timing simulation process.

• Appendix A, “Glossary,” defines some of the commonly usedterms in this manual.

• Appendix B, “Foundation Constraints,” discusses some of themore common constraints you can apply to your design tocontrol the timing and layout of a Xilinx FPGA or CPLD; itdescribes how to use constraints at each stage of designprocessing.

• Appendix C, “Instantiated Components,” lists the componentsmost frequently instantiated in synthesis designs.

Foundation Series User Guide iii

Conventions

TypographicalThis manual uses the following conventions. An example illustrateseach convention.

• Courier font indicates messages, prompts, and program filesthat the system displays.

speed grade: -100

• Courier bold indicates literal commands that you enter in asyntactical statement.

rpt_del_net=

Courier bold also indicates commands that you select from amenu.

File → Open

• Italic font denotes the following items.

• Variables in a syntax statement for which you must supplyvalues

edif2ngd design_name

• References to other manuals

See the Development System Reference Guide for moreinformation.

• Emphasis in text

If a wire is drawn so that it overlaps the pin of a symbol, thetwo nets are not connected.


iv Xilinx Development System

• Square brackets “[ ]” indicate an optional entry or parameter.However, in bus specifications, such as bus [7:0], they arerequired.

edif2ngd [option_name] design_name

Square brackets also enclose footnotes in tables that are printedout as hardcopy in DynaText.

• Braces “{ }” enclose a list of items from which you choose one ormore.

lowpwr ={on|off}

• A vertical bar “|” separates items in a list of choices.

symbol editor_name [bus|pins]

• A vertical ellipsis indicates repetitive material that has beenomitted.

IOB #1: Name = QOUT’IOB #2: Name = CLKIN’...

• A horizontal ellipsis “. . .” indicates that an item can be repeatedone or more times.

allow block block_name loc1 loc2 ... locn;

Online DocumentXilinx has created several conventions for use within the DynaTextonline documents.

• Red-underlined text indicates an interbook link, which is a cross-reference to another book. Click on the red-underlined text toopen the specified cross-reference.

• Blue-underlined text indicates an intrabook link, which is a cross-reference within a book. Click on the blue-underlined text toopen the specified cross-reference.

• There are several types of icons.

Iconized figures are identified by the figure icon.

Foundation Series User Guide v

Iconized tables are identified by the table icon.

The Copyright icon displays in the upper left corner on the firstpage of every Xilinx online document.

The DynaText footnote icon displays next to the footnoted text.

Double-click on these icons to display figures, tables, copyrightinformation, or footnotes in a separate window.

• Inline figures display within the text of a document. You candisplay these figures in a separate window by clicking on thefigure.


vi Xilinx Development System

Foundation Series User Guide vii

Contents

PrefaceAbout the Manual .......................................................................... iFoundation Series User Guide Contents ...................................... i

ConventionsTypographical................................................................................ iiiOnline Document .......................................................................... iv

Chapter 1 Introduction

Architecture Support ..................................................................... 1-1Platform Support ........................................................................... 1-1Design Flow .................................................................................. 1-1

FPGA Design Flow .................................................................. 1-2CPLD Design Flow................................................................... 1-5

Tutorials ........................................................................................ 1-7Online Help ................................................................................... 1-7

Chapter 2 Design Methodologies

Creating Projects........................................................................... 2-1Top-level Schematic Designs........................................................ 2-2

All Schematic Designs ............................................................. 2-2Creating the Schematic and Generating a Netlist............... 2-2Performing Functional Simulation....................................... 2-2Implementing the Design .................................................... 2-4Performing a Static Timing Analysis (Optional) .................. 2-4Performing a Timing Simulation.......................................... 2-5Downloading the Design..................................................... 2-5

Schematic Designs with Instantiated HDL-based Macros ....... 2-5Creating HDL Macros ......................................................... 2-5Creating the Schematic and Generating a Netlist............... 2-6

viii Xilinx Development System


Schematic Designs With Instantiated LogiBLOX Modules ...... 2-7Creating LogiBLOX Modules .............................................. 2-7Importing Existing LogiBLOX Modules ............................... 2-8

Schematic Designs With State Machine Macros ..................... 2-9Creating State Machine Macros ......................................... 2-9Creating the Schematic and Generating a Netlist............... 2-10

Top-level VHDL Designs............................................................... 2-11All-VHDL Designs .................................................................... 2-11VHDL Designs with Instantiated Schematic Macros................ 2-12

Creating the Schematic Module.......................................... 2-12Creating the HDL Design.................................................... 2-13

VHDL Designs with State Machine Macros ............................. 2-15Creating a State Machine Macro ........................................ 2-15Creating the HDL Design.................................................... 2-17

VHDL Designs with Instantiated Xilinx Unified Library Components.............................................................. 2-19VHDL Designs with Instantiated LogiBLOX Modules .............. 2-21VHDL Designs with Instantiated Netlist Modules..................... 2-23

State Machine Designs ................................................................. 2-24Creating the State Editor Design ............................................. 2-24Defining States......................................................................... 2-25Defining Transitions, Conditions, and Actions ......................... 2-26

Chapter 3 Foundation Toolset

Project Manager............................................................................ 3-1Project Definition...................................................................... 3-3Starting the Project Manager ................................................... 3-4Project Manager Project Contents ........................................... 3-4

Schematic Files .................................................................. 3-4HDL Text Files .................................................................... 3-4State Editor Files ................................................................ 3-4Simulation Test Vectors...................................................... 3-5

Project Manager Tabs.............................................................. 3-5Contents Tab ...................................................................... 3-5Status Tab .......................................................................... 3-5Reports Tab ........................................................................ 3-6Synthesis Tab ..................................................................... 3-6

Accessing LogiBLOX from the Project Manager...................... 3-6Documenting Your Design ....................................................... 3-6Project Archiving ...................................................................... 3-7

Foundation Series User Guide ix

Contents

Design Entry Tools........................................................................ 3-8Schematic Editor...................................................................... 3-8HDL Editor ............................................................................... 3-8State Editor .............................................................................. 3-9Logic Simulator ........................................................................ 3-9XVHDL Compiler...................................................................... 3-10Library Manager....................................................................... 3-10Symbol Editor........................................................................... 3-10

Design Implementation Tools........................................................ 3-11Design Manager....................................................................... 3-11

Managing Projects .............................................................. 3-12Managing Design Versions................................................. 3-12Managing Implementation Revisions.................................. 3-12XProject Directory............................................................... 3-13

Flow Engine ............................................................................. 3-13

Chapter 4 Schematic Design Entry

Managing Schematic Designs....................................................... 4-1Design Structure ...................................................................... 4-2Single Sheet Schematic........................................................... 4-2Multi-sheet Flat Schematic....................................................... 4-3Hierarchical Schematic ............................................................ 4-4Adding New Sheets to the Project ........................................... 4-5Adding Existing Sheets to the Project...................................... 4-6Opening Non-project Sheets.................................................... 4-6Removing Sheets from the Project .......................................... 4-6Renumbering Symbol References ........................................... 4-7Copying a Section of a Schematic to Another Sheet ............... 4-8Troubleshooting Project Contents............................................ 4-8

Hierarchical Schematic Designs ................................................... 4-9Creating a Hierarchical Schematic........................................... 4-9Recognizing Hierarchical Macros ............................................ 4-9Navigating the Project Hierarchy ............................................. 4-9Modifying Existing Macros ....................................................... 4-11Difference between a Macro and a Schematic ........................ 4-11Hierarchy Symbol Changes ..................................................... 4-12Using a Top-down Methodology .............................................. 4-12Hierarchical Design Example................................................... 4-13

Manually Exporting a Netlist.......................................................... 4-17Creating a Schematic from a Netlist.............................................. 4-17

x Xilinx Development System


Miscellaneous Tips for Using the Schematic Capture Tool........... 4-18Color-coded Symbols............................................................... 4-18Using VCC and GND ............................................................... 4-18Using the I/O Terminal Component ......................................... 4-19Using Input and Output Buffers................................................ 4-19Schematic Tabs ....................................................................... 4-19Simulate Current Macro ........................................................... 4-20

Chapter 5 HDL Design Entry and Synthesis

VHDL File Selection ...................................................................... 5-2Adding the File to the Project................................................... 5-3Getting Help with the Language............................................... 5-3

Creating a Hierarchical VHDL Design........................................... 5-4Synthesis of the HDL Modules...................................................... 5-6

Top-down Methodology ........................................................... 5-6Bottom-up Methodology........................................................... 5-6Design Flow — Top-down........................................................ 5-6Design Flow — Bottom-up ....................................................... 5-7

Managing Large Designs .............................................................. 5-8Improved Design Optimization................................................. 5-8Optimization Switch ................................................................. 5-8Optimization Tips ..................................................................... 5-9Setting the Optimization Strategy with Top-down Methodology 5-9Setting the Optimization Strategy with Bottom-up Methodology 5-10

Advanced Design Techniques ...................................................... 5-11Partitioning Guidelines ............................................................. 5-11LogiBLOX................................................................................. 5-12Tristate Buses .......................................................................... 5-13User Libraries........................................................................... 5-13

Foundation Series User Guide xi

Contents

Chapter 6 State Machine Designs

State Machine Example ................................................................ 6-2State Diagram ............................................................................... 6-2State Machine Implementation...................................................... 6-3Encoding Techniques.................................................................... 6-4

Symbolic and Encoded State Machines .................................. 6-4Compromises in State Machine Encoding ............................... 6-5Binary Encoding....................................................................... 6-5One-hot Encoding .................................................................... 6-6

One-Hot Encoding in Xilinx FPGA Architecture.................. 6-6Limitations........................................................................... 6-6

Encoding for CPLDs ................................................................ 6-7

Chapter 7 LogiBLOX

Setting Up LogiBLOX on a PC ...................................................... 7-2Starting LogiBLOX ........................................................................ 7-2Creating LogiBLOX Modules......................................................... 7-2LogiBLOX Modules ....................................................................... 7-3Using LogiBLOX for Schematic Designs....................................... 7-3Using LogiBLOX for HDL Designs ................................................ 7-4

Module-inferring Tools ............................................................. 7-4Module-instantiation Tools ....................................................... 7-4

Documentation .............................................................................. 7-4

Chapter 8 Functional Simulation

Basic Functional Simulation Process ............................................ 8-1Invoking the Simulator ............................................................. 8-1Attaching Probes (Schematic Editor Only)............................... 8-2Adding Signals ......................................................................... 8-2Creating Buses ........................................................................ 8-3Applying Stimulus .................................................................... 8-3Running Simulation.................................................................. 8-4

VHDL Top-down Methodology ...................................................... 8-5VHDL Bottom-up Methodology or Underlying Netlists .................. 8-6Simulation Macro Editor ................................................................ 8-7Waveform Editing Functions ......................................................... 8-7

xii Xilinx Development System


Chapter 9 An Introduction to Design Implementation

Starting the Xilinx Design Manager............................................... 9-1Implementing a Design ................................................................. 9-2

MAP ......................................................................................... 9-4Place and Route (PAR)............................................................ 9-5BitGen (Configure) ................................................................... 9-5CPLD Fitter .............................................................................. 9-6EPIC......................................................................................... 9-7

Selecting Options .......................................................................... 9-7Post Implementation Static Timing Analysis ................................. 9-9Summary Timing Reports ............................................................. 9-9

Chapter 10 Post-implementation Timing Simulation

Generating a Timing-annotated Netlist ......................................... 10-1Creating Timing Test Vectors........................................................ 10-1Basic Timing Simulation Process.................................................. 10-2

Appendix A Glossary

Appendix B Foundation ConstraintsConstraint Entry Mechanisms ....................................................... B-2Translating and Merging Logical Designs ..................................... B-3Constraints File Overview ............................................................. B-4

User Constraint File (UCF) ...................................................... B-4Physical Constraints File (PCF) ............................................... B-5Case Sensitivity ....................................................................... B-5

UCF Timing Constraints................................................................ B-6The “From:To” Style Timespec ................................................ B-6Using TPSYNC ........................................................................ B-7The Period Style Timespec...................................................... B-8The Offset Constraint............................................................... B-9Ignoring Paths.......................................................................... B-11Controlling Skew ...................................................................... B-11Constraint Precedence ............................................................ B-12

Layout Constraints ........................................................................ B-13Converting a Logical Design to a Physical Design .................. B-13Last One Wins Resolution ....................................................... B-14

Efficient Use of Timespecs and Layout Constraints...................... B-14Standard Block Delay Symbols..................................................... B-17Table of Supported Constraints .................................................... B-19Constraining LogiBLOX RAM/ROM with Synopsys ...................... B-22

Foundation Series User Guide xiii

Contents

Estimating the Number of Primitives Used .............................. B-22How the RAM Primitives are Named ....................................... B-22Referencing a LogiBLOX Module/Component in the Foundation Express Flow .................................................... B-23Referencing the Primitives of a LogiBLOX Module in the Foundation Express Flow .................................................... B-24Foundation Express Verilog Example...................................... B-24

test.v: .................................................................................. B-24inside.v:............................................................................... B-25test.ucf ................................................................................ B-25

Foundation Express VHDL Example ....................................... B-25test.vhd ............................................................................... B-25inside.vhd............................................................................ B-26test.ucf ................................................................................ B-27

Appendix C Instantiated ComponentsArchitecture Definitions ................................................................. C-2

XC3000 Library ........................................................................ C-2XC4000E Library...................................................................... C-2XC4000X Library...................................................................... C-3XC4000 References................................................................. C-3XC5200 Library ........................................................................ C-3XC9000 Library ........................................................................ C-3

STARTUP Component.................................................................. C-3BSCAN Component ...................................................................... C-4READBACK Component............................................................... C-5RAM and ROM.............................................................................. C-6Global Buffers ............................................................................... C-7Fast Output Primitives (XC4000X only) ........................................ C-8IOB Components........................................................................... C-10

xiv Xilinx Development System


Foundation Series User Guide 1-1

Chapter 1

Introduction

This chapter contains the following sections.

• “Architecture Support” section

• “Platform Support” section

• “Design Flow” section

• “Tutorials” section

• “Online Help” section

Architecture SupportFoundation supports the XC3000A/L, XC3100/A/L, XC4000E/L/EX/XL/XV, XCS, XC5200, and XC9500 families. For detailedinformation about architecture support, see the “Device and PackageSupport” chapter in the Foundation Series 1.4 Install and ReleaseDocument.

Platform SupportFoundation runs on the Windows NT 4.0 and Windows 95 platforms.

Design FlowThe Foundation Series Design Tools interface supports the followingdesign flows:

• top-level schematic entry with the Xilinx Unified librariescomponents, LogiBLOX symbols, or both

• schematic entry with Unified Library components with somecomponents expressed as HDL or State Machine macros


1-2 Xilinx Development System

• top-down HDL design entry and synthesis

• all-VHDL design

• mixed-VHDL designs with schematic-based, state machine, orLogiBLOX instantiated components

• finite state machine diagram entry

The figures immediately following show the FPGA and CPLD designprocess in terms of 1) high-level overview and 2) manipulation ofnetlist and constraint files. For a detailed description of designmethodologies, refer to the “Design Methodologies” chapter.

FPGA Design FlowThe following three figures illustrate FPGA design flows.

Figure 1-1 Manipulation of Netlist and Constraint Files forFPGAs (Part 1)

Symbol Descriptor

X8092

Simulation Only

See Next Page

Design Netlist and Constraints

Schematic Capture

Gate-Level Simulation Netlist Merging/Mapping

EDN

EDN

EDN

EDN UCF PCF

VHD

Viewlogic Import Utility

User-created Simulation Stimulus

LogiBLOX GUI

ABL

Finite State Machine Editor

HDL Editor

XVHDL Compiler

XABEL Compiler

Introduction



NGD

NGM

NGO NGO NGO

EDN EDN XNF

TWR

NCD/PCF

X8091

• Merges .ngo files • Expands LogiBLOX references • Expands Macro references • .ngd output is complete logical design representation (binary)

NGDBuild

• Maps logical components to physical components of target architecture • Conversts user-end design capture tool-generated constraints to physical constraints • .ncd output is a physical design netlist (binary)

Map

Knowledge-driven

Place and Route See next page.

TRCE

Static Timing Analyzer

Post-map Static Timing Analysis Report (text)

Used for generation of timing annotated post-route netlist

Block delays/estimated route delays

EDIF2NGD EDIF2NGD XNF2NGDFor backward compatibility only

binary

User Constraints

. . .

. . .

UCF

Netlist Constraints

NCF




PCF

TWR

NCD/PCF

NCD

X8093

• Places mapped physical components into specific component locations (sites) in target device • Creates connections (routes) between sites to provide design's interconnectivity • Iterate placement and routing phases to meet timing/physical constraints if necessary.

PAR

TRCEStatic Timing

Analyzer

NGDAnno

NGD2EDIF

Gate-level Simulators

NGD2VHD

NGD2VER

NGD2XNF

PROM File Formatter

Third-party Simulators

BitGen

Post-map Static Timing Analysis Report (text)

Block and Routing Delays

User-created Stimulus

From MAP

From MAP

NGA

VHD

VER

XNF

BIT

Hardware Debugger

NGM

Introduction


CPLD Design FlowThe Following three figures illustrate CPLD design flow.

Figure 1-4 Manipulation of Netlist and Constraint Files forCPLDs (Part 1)

See Next Page

Design Netlist and Constraints

Schematic Capture

Gate-level Simulation Netlist Merging/Mapping

X8225

EDN

EDN

EDN UCF PCF

VHD

Viewlogic Import Utility

User-created Simulation Stimulus

ABL

Finite State Machine Editor

HDL Editor

XVHDL Compiler

XABEL Compiler




X8226

NGDBuild

• Merges NGD files • Expands LogiBLOX references • Expands Macro references • NGO output is a complete logical design representation (binary)

Design LoaderDRC1

XNF2NGD

NGO

NGD

Auto Device/Speed Selector

Logic Synthesis Technology Mapping

Global Reset Optimization

Logic OptimizationPartitioning

Exporting Assignments

Export Level Generator

PTerm Mapping

Power/Slew Optimization

Post-Mapping Enhancements

Routing

EDN

UCF

User Constraints

Netlist Constraints

CPLD Fitter

NCF

XNF2NGD XNF2NGD

Guide file

CTL Control

<design>.VM6<design>.RPT

Pin Feedback Generation

DRC2

DRC3

Introduction



TutorialsXilinx recommends that you perform the basic FPGA tutorialprovided in the online help to become familiar with the concepts ofdesign entry, design implementation, and design verification. TheFoundation Series Quick Start Guide 1.4 contains an in-depth tutorialthat describes design entry and design implementation in detail.

Online HelpThe Xilinx Foundation Series online help system accesses help topicscovering all design entry and implementation tools provided in theproduct. The online help system also contains in-depth informationessential for designing with XC9500 CPLDs, including:

• CPLD design techniques

• CPLD timing specifications

• FPGA design information

• application notes

X8227

Timing Analyzer Engine

Timing Analyzer GUI

TIM

JED VHD

NGA

HPLUSAS6 (9500 Flow)

HPREP6

Timing Simulator

Simulator Interface

OTHEREDF

VM6

TEMP.VM6



• several tutorials

• reference information on the schematic library, attributes, andimplementation options

You can invoke the online help system from the Project Manager’sHelp pull-down menu or from the Xilinx Foundation Series programgroup.

To access the “umbrella” help system, select Help → FoundationHelp Contents from the Project Manager menu bar.

Figure 1-7 The Online Help System


Chapter 2


This chapter describes various design methodologies that you canuse with the Foundation tools.


• “Creating Projects” section

• “Top-level Schematic Designs” section

• “Top-level VHDL Designs” section

• “State Machine Designs” section

For a description of design flows with Foundation Express, refer tothe Foundation Express Application Note Supplement. With FoundationExpress, you may create both Verilog and VHDL designs.

Creating ProjectsSchematic, VHDL, and State Machine designs must be defined aselements in a project. To create a project, perform the following steps.

1. Select File → New Project from the Project manager.

2. Enter the project name in the Name box.

3. Select a location for the project in the Directory box.

4. Select the project type in the Type box.

5. Enter family, part, and speed.

6. Click OK.

The following sections assume that you have already created aproject for your designs.



Top-level Schematic DesignsThis section describes various methodologies using top-levelschematic designs.

All Schematic DesignsThis general procedure describes the schematic entry flow for designsthat are schematic only, that is, there are no instantiated HDL or StateMachine macros.

Creating the Schematic and Generating a Netlist

Following are the basic steps:

1. Open the Schematic Editor by selecting the Schematic Editor iconfrom the Project Manager.

2. Select Mode → Symbols to add components to your newschematic. Select specific components from the SC Symbolswindow.

3. Complete your schematic by placing additional componentsfrom the Symbol toolbox including I/O ports, nets, buses, labels,and attributes.

4. Save your schematic by selecting File → Save .

For more information about schematic designs, see the following:

• “Schematic Design Entry” chapter

• In the Schematic Capture window, select Help → SchematicEditor Help Contents , or alternatively press Shift F1. ClickSchematic Editor.

Performing Functional Simulation

1. Open the Functional Simulator by clicking the SIM Funct buttonin the Project Manager. The design will automatically be loadedinto the simulator.

The Waveform Viewer window displays on top of the LogicSimulator window.

2. Add signals by selecting Signal → Add Signals .



3. From the Signals Selection portion of Components Selection inthe Waveform Viewer window, select the signals that you want tosee in the simulator.

4. Use CTRL-click to select multiple signals. Make sure you addoutput signals as well as input signals.

5. Click Add and then Close. The signals are added to theWaveform Viewer in the Logic Simulator screen.

6. Select Signal → Add Stimulators from the Logic Simulatormenu. The Stimulator Selection window displays.

7. In the Stimulator Selection window, create the waveformstimulus by attaching stimulus waveforms to the inputs. Formore details on how to use the Stimulus Selection window, clickthe Help button.

8. After the stimulus has been applied to all inputs, select either theshort or long Step icon from the Logic Simulator toolbar. (If theSimulator window is not open, select View → Main Toolbar .)

Figure 2-1 Short Step Toolbar Button

Figure 2-2 Long Step Toolbar Button

9. Verify that the output waveform is correct. Select a step buttonrepeatedly to continue simulating.

10. To save the stimulus for future viewing or reuse, select File →Save Waveform . Enter a file name with a .tve extension in theFile name box of the Save Waveform window. Click OK.

For more information about saving and loading test vectors, fromthe Logic Simulator window, select Help → Logic SimulatorHelp Contents . Select Simulator Reference → WorkingWith Waveforms → Saving and Loading Waveforms .



Implementing the Design

1. Click the Implement M1 icon.

2. Select Design → Implement from the menu bar.

By default, the Design Manager targets the device that waspreviously selected in the Foundation Project Manager. If youwish to retarget the design to a different device, use theImplement dialog box. If you want to retarget to a new devicefamily, you must first do so in the Foundation Project Manager byselecting File → Project Type .

3. In the Implement dialog box, select Options. The Options dialogbox displays.

4. Choose any desired implementation option. If you are planningon conducting a timing simulation, select the Produce TimingSimulation Data option.

5. Click OK to return to the Implement dialog box.

6. Click Run. The Design Manager implements your design. TheFlow Engine displays the progress of the implementation.

When Implementation is complete, the Implement Statuswindow displays.

7. Select Reports to review your design reports.

For more information on how to use the Design Manager, refer tothe online DynaText manual, Design Manager/Flow EngineReference/User Guide.

Performing a Static Timing Analysis (Optional)

Perform a static timing analysis on mapped or place and routeddesigns for FPGAs.

For FPGAs, you can perform a post-MAP or post-place timinganalysis to obtain rough timing information before routing delays areadded. You can also perform a post-implementation timing analysison CPLDs after a design has been implemented using the CPLD fitter.

For details on how to use the Timing Analyzer, refer to the onlineDynaText manual Timing Analyzer Reference/User Guide.



Performing a Timing Simulation

1. Open the Timing Simulator by clicking the SIM Timing buttonfrom the Foundation Project Manager. The implementationtiming netlist will be loaded into the simulator.


2. Refer to the “Performing Functional Simulation” section forinstructions on simulating the design. (The operation of thesimulator is the same for functional and timing simulation.)

3. If you have already saved test vectors (for instance, in thefunctional simulation), you may load these vectors into thetiming simulator by selecting File → Load Waveform .

Downloading the Design

For CPLD designs, use the JTAG Programmer. Refer to the onlineDynaText manual, JTAG Programmer Guide. For FPGA designs, usethe Hardware Debugger. Refer to the online DynaText manual,Hardware Debugger Reference/User Guide.

Schematic Designs with Instantiated HDL-basedMacros

This section explains how to create HDL macros and then add themto your schematic design.

Creating HDL Macros

After you create an HDL macro, the macro will be available from theSC Symbols window in the Schematic Editor. These are the steps youfollow to create HDL macros.

1. Open the HDL Editor.

2. In the HDL Editor dialog box, select Use the HDL Design Wizard.Click OK.

3. From the Design Wizard window, select Next and then chooseVHDL or ABEL.

4. Enter a name for your macro in the Design Wizard - Namewindow. Select Next.



5. Define your ports in the Design Wizard-Ports window.

6. Click Finish. The Wizard creates the ports and gives you atemplate in which you can enter your macro design.

7. Complete the design for your macro in the HDL Editor.

8. Create a macro symbol by selecting Project → Create Macro .

The synthesizer will not insert top level input and output padsfor this macro. Instead the top level schematic, which containsthe macro, includes all top level input and output pads requiredfor implementation.

For more information about creating HDL macros, from theProject Manager window, select Help → Foundation HelpContents . Click HDL Editor.


1. Open the Schematic Editor.

2. Select Mode → Symbols to add components to your newschematic.

Any macros that you have created display in the SC Symbolstoolbox with the other standard symbols.

3. Select the HDL macro that you created by clicking its name.

4. Move your cursor to the schematic sheet and place the macrosymbol by clicking.

5. Complete your schematic by placing additional componentsfrom the Symbol toolbox including I/O ports, nets, buses, labels,and attributes.




• In the Schematic Capture window, select Help → FoundationHelp Contents . Click Schematic Editor.



To complete the design, read the following sections in the orderlisted:

• “Performing Functional Simulation” section

• “Implementing the Design” section

• “Performing a Static Timing Analysis (Optional)” section

• “Performing a Timing Simulation” section

• “Downloading the Design” section

Schematic Designs With Instantiated LogiBLOXModules

LogiBLOX modules can be created for use in schematic designs. First,the module must be created. The module can then be added to theschematic like any other library component.

Creating LogiBLOX Modules

To use the program in a schematic-based environment, follow thesesteps:

1. With a project open, invoke the LogiBLOX Module Selector fromwithin the Schematic Editor (Options → LogiBLOX ).

2. Select a base module type (for example, counter, memory, orshift-register).

3. Customize the module by selecting pins and specifyingattributes.

4. After completely specifying a module, click on the OK button.Selecting OK initiates the generation of a schematic symbol and asimulation model for the selected module. The schematic symbolfor the LogiBLOX component is incorporated into the projectlibrary and may be selected from the SC Symbols window in theSchematic Editor.

5. Place the module on your schematic by selecting Mode →Symbols from the Schematic Capture window.

6. Select the symbol for your LogiBLOX module from the SCSymbols window.



7. Connect the LogiBLOX module to the other components on yourschematic using ordinary nets, buses, or both.

8. Complete your schematic by placing additional componentsfrom the symbol toolbox including I/O ports, nets, buses, labels,and attributes.


Importing Existing LogiBLOX Modules

You can also import LogiBLOX modules that already exist (forexample, from another project).

To convert an existing EDN netlist of an existing LogiBLOX moduleto a binary netlist and save the component to the project workinglibrary, perform the following steps.

1. In the Schematic Editor, select Options → Import LogiBLOX .

2. From the Import LogiBLOX from MOD File dialog box, select theMOD file you want to convert. Click OK.

The schematic symbol for the LogiBLOX component isincorporated into the SC Symbols window in the SchematicEditor.

3. Follow Steps 5 through 8 in the previous section, “CreatingLogiBLOX Modules” section to instantiate your module.









Schematic Designs With State Machine MacrosThis section explains how to create state machine macros andinstantiate them in schematic designs.

Creating State Machine Macros

After a macro is created, it will then be available from the SC Symbolswindow in the Schematic Editor. These are the steps you follow tocreate State Machine macros.

1. Open the State Editor by clicking on the State Editor icon fromthe Project Manager.

2. Select Use the HDL Design Wizard. Click OK.

3. From the Design Wizard window, select Next.

4. From the Design Wizard - Language window, choose VHDL orABEL. Click Next.

5. Enter a name for your macro in the Design Wizard - Namewindow. Select Next.

6. Define your ports in the Design Wizard-Ports window. SelectNext.

7. In the Design Wizards - Machines window, select the number ofstate machines that you want. Click Finish. The Wizard createsthe ports and gives you a template in which you can enter yourstate machine design.

8. Create the design for your state machine in the State Editor.

9. When you are finished creating your state machine, create amacro symbol by selecting Project → Create Macro .

The synthesizer will not insert top level input and output padsfor this macro. Instead the top level schematic, which containsthe macro, includes all top level input and output pads requiredfor implementation.

For more information about state machines, select Help →Foundation Help Contents from the Project Manager. ClickState Editor.





2. Select Mode → Symbols to add components to your newschematic.

Any macros that you have created display in the SC Symbolstoolbox with the other standard symbols.

3. Select the state machine macro from the toolbox by clicking itsname.

4. Move your cursor to the schematic sheet and place the macrosymbol by clicking.

5. Complete your schematic by placing additional componentsfrom the SC Symbols toolbox including I/O ports, nets, buses,labels, and attributes.




• In the Schematic Capture window, select Help → FoundationHelp Contents . Click Schematic Editor.









Top-level VHDL DesignsThis section describes various methodologies using top-level VHDLdesigns.

All-VHDL DesignsThis general procedure describes the HDL entry flow for designs thatare non-hierarchical HDL only, that is, there are no instantiatedschematic, LogiBLOX, netlist, or state machine macros. For a detaileddescription of how to compile all-VHDL hierarchical designs, see the“Creating a Hierarchical VHDL Design” section of the “HDL DesignEntry and Synthesis” chapter.

Following are the basic steps to create the HDL design and generate anetlist:

1. Open the HDL Editor by clicking the HDL Editor icon from theProject Manager.

2. When the HDL Editor dialog box displays, select Use HDLDesign Wizard. Click OK. Click Next in the Design Wizardwindow.

3. From the Design Wizard - Language window, select VHDL. ClickNext.

4. In the Design Wizard - Name window, enter the name of yourdesign file. Click Next.

5. Define your ports in the Design Wizard-Ports window. ClickFinish. The Wizard creates the ports and gives you a template inwhich you can enter your design.

6. Create the design in the HDL Editor.

7. Add this design to the project by selecting Project → Add toProject .

8. Synthesize the design by selecting Synthesis → Synthesize .

The synthesizer automatically includes top-level input andoutput pads required for implementation.



For more information about HDL designs, see the following:

• “HDL Design Entry and Synthesis” chapter

• In the Project Manager window, select Help → FoundationHelp Contents . Click HDL Editor.







VHDL Designs with Instantiated Schematic MacrosThis section explains how to instantiate schematic macros into VHDLdesigns.

Creating the Schematic Module

You can create schematics in Foundation which can then beinstantiated into a VHDL file. The schematic must have I/Oterminals at each of the ports in order for the connection between theVHDL top-level design and the lower-level schematic module to berealized. Follow these steps to generate a schematic module forinstantiation.


2. Create the schematic.

Be sure that all the I/O ports of the design have I/O terminalsattached to them. Do not use I/OPADs and I/OBUFs. The namesof these I/O terminals will be the names of the ports of theinstantiated module in the VHDL code. Use the I/O terminalicon in the Schematic Editor, shown below, to add I/O terminals.



3. Save the schematic by selecting File → Save As and choose aname for the module.

4. Select Options → Create Netlist from Current Sheet .

5. Select Options → Export Netlist . Select the newly creatednetlist and make sure that the file is exported to the .edn format.

Creating the HDL Design



2. When the HDL Editor dialog box displays, select Use HDLDesign Wizard. Click OK. Click Next in the Design Wizardwindow.

3. From the Design Wizard - Language window, select VHDL. ClickNext.




7. Instantiate the schematic module into the HDL file. When youinstantiate your design, you must make a component declarationand a port map declaration. The part names for the module maybe found in the netlist or on the schematic. In the followingsample, the italicized code indicates the component declarationand instantiation for the schematic module, sch_module.

The following example shows an excerpt from a top-level VHDLfile, with the lower-level schematic module instantiated within it.



library IEEE;use IEEE.std_logic_1164.all;

entity top_vhd isport (

a1_top, d_in1_top, clk1_top, rst1_top: in STD_LOGIC;not_a1_top, q_out1_top: out STD_LOGIC

);end top_vhd;

architecture top_vhd_arch of top_vhd iscomponent sch_module

port (a1, d_in1, clk1, rst1: in std_logic;not_a1, q_out1: out std_logic

);end component;beginU1: sch_module port map (a1=>a1_top, d_in1=>d_in1_top, clk1=>clk1_top,

rst1=>rst1_top, not_a1=>not_a1_top, q_out1=>q_out1_top);end top_vhd_arch;

8. Create the design in the HDL Editor.

9. Add this design to the project by selecting Project → Add toProject .

Note: If you cannot add the file to the project, make sure that the .schfile is not added to the project in the Project Manager. (You should notsee a .sch file listed in the left-hand side of the Project Manager). If the.sch file is listed, select the file and select Document → Remove. Nowyou can add the .vhd file as the top-level file.


The synthesizer will automatically include top level input andoutput pads for this design.




11. Run the Translate phase of the implementation in the XilinxDesign Manager prior to functional simulation. For details, referto the “VHDL Bottom-up Methodology or Underlying Netlists”section of the “Functional Simulation” chapter.




• “Performing Functional Simulation” section (Steps 2 through 10)





VHDL Designs with State Machine MacrosThis section explains how to create a state machine macro andinstantiate it into a VHDL design.

Creating a State Machine Macro

1. From the Project Manager, open the State Editor.

2. Select Use the HDL Design Wizard. Click OK.


4. From the Design Wizard - Language window, choose VHDL andselect Next.

5. In the Design Wizard - Name window, enter a name for yourmacro. Select Next.


7. In the Design Wizards - Machines window, select the number ofstate machines that you want. Click Finish. The Wizard createsthe ports and gives you a template in which you can enter yourmacro design.

8. Complete the design for your macro in the State Editor.

9. Create a macro symbol by selecting Project → Create Macro .

The synthesizer will not insert top level input and output padsfor this macro. Instead the top level VHDL file, which containsthe macro, includes all top level input and output pads requiredfor implementation.



Following is an example of VHDL code (my_fsm.vhd) generatedfrom the State Editor for a state machine macro.


-- SYNOPSYS library declarationlibrary SYNOPSYS;use SYNOPSYS.std_logic_arith.all;use SYNOPSYS.std_logic_unsigned.all;

library METAMOR;use METAMOR.ATTRIBUTES.all;

entity my_fsm isport (clk: in STD_LOGIC;

in_a: in STD_LOGIC;in_b: in STD_LOGIC;in_c: in STD_LOGIC;reset: in STD_LOGIC;out_a: out STD_LOGIC;out_b: out STD_LOGIC;out_c: out STD_LOGIC);

end;

architecture my_fsm_arch of my_fsm is

-- SYMBOLIC ENCODED state machine: Sreg0type Sreg0_type is (S1, S2, S3);signal Sreg0: Sreg0_type;

begin--concurrent signal assignments--diagram ACTIONS

process (clk)

begin

if clk'event and clk = '1' thenif reset='1' then

Sreg0 <= S1;elsecase Sreg0 is

when S1 =>if in_a = '1' then

Sreg0 <= S2;end if;

when S2 =>if in_b = '1' then



Sreg0 <= S3;end if;

when S3 =>if in_c = '1' then

Sreg0 <= S1;end if;

when others =>null;

end case;end if;

end if;end process;

-- signal assignment statements for combinatorial-- outputsout_c <= '0' when (Sreg0 = S2) else

'0' when (Sreg0 = S3) else'1';

out_a <= '1' when (Sreg0 = S2) else'0' when (Sreg0 = S3) else'0';

out_b <= '0' when (Sreg0 = S2) else'1' when (Sreg0 = S3) else'0';

end my_fsm_arch;

For more information about creating state machine macros, selectHelp → Foundation Help Contents . Click State Editor.

Creating the HDL Design



2. When the HDL Editor dialog box displays, select Use HDLDesign Wizard. Click OK.

3. In the Design Wizard window, click Next.

4. From the Design Wizard - Language window, select VHDL.






8. Complete your top-level VHDL design in the HDL Editor.

9. Instantiate the macro into the top-level design. The file beinginstantiated must be located in the VHDL project directory (thatis, the directory where the top-level VHDL file resides). Whenyou instantiate your design, you must make a componentdeclaration and a port map declaration. The part names for themodule may be found in the netlist.

The following example shows an excerpt from a top-level VHDLfile (vhd_top.vhd), with the lower-level state machine module(my_fsm) instantiated within it.


entity vhd_top isport (

top_clk: in STD_LOGIC;top_ina: in STD_LOGIC;top_inb: in STD_LOGIC;top_inc: in STD_LOGIC;top_reset: in STD_LOGIC;top_outa: out STD_LOGIC;top_outb: out STD_LOGIC;top_outc: out STD_LOGIC

);

end vhd_top;

architecture vhd_top_arch of vhd_top is

--declare State Machine componentcomponent my_fsm

port (clk, in_a, in_b, in_c, reset: in std_logic;out_a, out_b, out_c: out std_logic);

end component;

begin--instantiate State Machine componentU1: my_fsm port map (top_clk, top_ina, top_inb,

top_inc, top_reset, top_outa, top_outb, top_outc);end vhd_top_arch;



10. Add the top-level design to the project by selecting Project →Add to Project .






12. Run the Translate phase of the implementation in the XilinxDesign Manager prior to Functional Simulation. For details, referto the “VHDL Bottom-up Methodology or Underlying Netlists”section of the “Functional Simulation” chapter.







VHDL Designs with Instantiated Xilinx UnifiedLibrary Components

It is possible to instantiate certain Xilinx Unified Library componentsdirectly into your VHDL code. In general, you will find this mostuseful for components that the VHDL compiler is unable to infer,such as BSCAN, RAM, and certain types of global buffers. The“Instantiated Components” appendix lists the most commonlyinstantiated components, including descriptions of their function andpins.

When instantiating Unified Library components, the componentmust first be declared before the begin keyword in VHDL in thearchitecture and then may be instantiated multiple times in the bodyof the architecture.



The following example shows how to instantiate the STARTUPcomponent in a VHDL file, which in turn allows use of the dedicatedGSR (global set/reset) net.

The following sample written in VHDL shows an example of aninstantiated Xilinx Unified Library component, STARTUP.


entity gsr_test isport (

CLK: in STD_LOGIC;D_IN: in STD_LOGIC;RESET: in STD_LOGIC;Q_OUT: out STD_LOGIC

);end gsr_test;

architecture gsr_test_arch of gsr_test iscomponent STARTUP

port (GSR: in std_logic);end component;

begin

U1: STARTUP port map (GSR=>RESET);

process (CLK)begin

if (CLK event and CLK='1') thenQ_OUT <= D_IN;

end if;end process;

end gsr_test_arch;

1. Since the VHDL file is a top-level file of the design, selectProject → Add to Project .














VHDL Designs with Instantiated LogiBLOX ModulesLogiBLOX modules may be generated in Foundation and theninstantiated in the VHDL code. This flow may be used for anyLogiBLOX component, but it is especially useful for memorycomponents such as RAM. Never describe RAM behaviorally in theVHDL code, because combinatorial feedback paths will be inferred.

The module being instantiated must be located in the VHDL projectdirectory (that is, the directory where the top-level VHDL fileresides).

LogiBLOX provides a template tool for generating the VHDLcomponent declaration statement:

1. From the HDL Editor, select Synthesis → LogiBLOX . SelectSetup.

2. Select the Options tab in the Setup window.

3. Select the VHDL template in the Component Declaration field.

4. Make the necessary selections to create the desired LogiBLOXcomponent.

5. Click OK.

A .vhi file is created that contains the VHDL code for yourLogiBLOX module. Use this file as a template when instantiatingthe module.

my_sram is the name of the LogiBLOX component being instantiatedin the following examples.

The following example shows how to instantiate a LogiBLOX 16x4synchronous RAM module into VHDL.




library METAMOR;use METAMOR.attributes.all;

entity RAM_TOP isport (

a_top, di_top: in STD_LOGIC_VECTOR (3 downto 0);wr_en_top, wr_clk_top: in STD_LOGIC;do_top: out STD_LOGIC_VECTOR (3 downto 0)

);end RAM_TOP;

architecture ram_top_arch of ram_top iscomponent my_sram

PORT(A: IN std_logic_vector(3 DOWNTO 0);DI: IN std_logic_vector(3 DOWNTO 0);WR_EN: IN std_logic;WR_CLK: IN std_logic;DO: OUT std_logic_vector(3 DOWNTO 0)

);end component;

begin

U1 : my_sram port map(A=>A_TOP, DI=>DI_TOP, WR_EN=>WR_EN_TOP,WR_CLK=>WR_CLK_TOP, DO=>DO_TOP);

end ram_top_arch;

Synthesize the design by selecting Synthesis → Synthesize . Thesynthesizer will automatically include top level input and outputpads for this design.












VHDL Designs with Instantiated Netlist ModulesYou can instantiate .EDIF, .XNF, or .NGO files into a VHDL design.The netlist should reside in the VHDL project directory, that is, thedirectory where the top-level VHDL file resides.

The following examples show an excerpt from a top-level VHDL file,with a lower-level netlist instantiated within it.

sch_module is the name of the netlist being instantiated in thefollowing examples.

If the instantiated netlist is a top-level netlist (in other words, if it hasI/O pads and buffers), then the ports of the instantiated componentmust be port mapped to I/O ports of the top-level VHDL file.



a1_top, d_in1_top, clk1_top, rst1_top: in STD_LOGIC;not_a1_top, q_out1_top: out STD_LOGIC

);end top_vhd;

architecture top_vhd_arch of top_vhd iscomponent sch_module

port (a1, d_in1, clk1, rst1: in std_logic;not_a1, q_out1: out std_logic

);end component;

begin

U1: sch_module port map (a1=>a1_top, d_in1=>d_in1_top, clk1=>clk1_top,rst1=>rst1_top, not_a1=>not_a1_top, q_out1=>q_out1_top);

end top_vhd_arch;

1. Synthesize the design by selecting Synthesis → Synthesize .The synthesizer will automatically include top level input andoutput pads for this design.






2. Run the Translate phase of the implementation in the XilinxDesign Manager prior to Functional Simulation. For details, referto the “VHDL Bottom-up Methodology or Underlying Netlists”section of the “Functional Simulation” chapter.







State Machine DesignsThe State Editor allows you to specify functionality using the "bubblestate diagram" concept. Once you have described the state machine(or machines) using the State Editor's available graphics objects, theState Editor generates behavioral VHDL or XABEL code (dependingon which language type was selected when the state diagram wasbegun). This code can then synthesized to a gate-level netlist.

Creating the State Editor Design1. Click the State Editor button in the Project Manager window.


3. From the Design Wizard - Language window, choose VHDL orABEL and select Next.

4. In the Design Wizard - Name window, enter a name for yourdesign. Select Next.




6. In the Design Wizards - Machines window, select the number ofState Machines that you want. Click Finish. The Wizard createsthe ports and gives you a template in which you can enter yourmacro design.

7. Create the design in the State Editor.

Defining States1. Select FSM→ State or click on the State button in the vertical

toolbar.

2. Place the state bubble. The default state name is S1.

3. Click on the state name to select it, then click again to edit thetext.

4. Type the desired state name.

5. Click on the state bubble to select it. Click and drag the smallsquares to change the size and shape of the bubble. When thestate bubble is large enough to hold the name, click and drag thestate name to center it in the bubble.

6. Repeat steps 1-4 to create new states.

To ensure that the state machine powers up in the correct state,you must define an asynchronous reset condition. This reset willnot be connected in the schematic, but its presence directs theVHDL compiler to define the state encoding so that the machinewill power up in the correct state.

7. Select FSM→ Reset or click on the Reset button in the verticaltoolbar.

8. Place the reset symbol in the state diagram. Click inside a statebubble to define this as the reset state.

9. To define the reset as asynchronous, right-click on the resetsymbol and select Asynchronous .



Defining Transitions, Conditions, and ActionsTransitions define the changes from one state to another. They aredrawn as arrows between state bubbles.

If there is more than one transition leaving a state, you must associatea condition with each transition. A condition is a Boolean expression.When the condition is true, the machine moves along the transitionarrow.

Actions are HDL statements that are used to make assignments tooutput ports or internal signals. Actions can be executed at severalpoints in the state diagram. The most commonly used actions arestate actions and transition actions. State actions are executed whenthe machine is in the associated state. Transition actions are executedwhen the machine goes through the associated transition.

1. Select File → Save to save the state diagram.

2. Select Project → Add to project .

3. Select Synthesis → Synthesize .








Chapter 3

Foundation Toolset

This chapter explains how to access the various Foundation designtools from the Project Manager and briefly describes each tool and itsfunction. This chapter contains the following sections.

• “Project Manager” section

• “Design Entry Tools” section

• “Design Implementation Tools” section

Project ManagerThe Project Manager, the overall project management tool, containsthe Foundation Series tools used in the design process. It is throughthe Project Manager that you access the design entry tools (SchematicEditor, HDL Editor, State Diagram Editor, and Logic Simulator) andthe design implementation tools, which are then accessed from theXilinx Design Manager.

Note: The Foundation Express tools are not incorporated into theProject Manager. For information about how to use FoundationExpress, see the Foundation Express Application Note Supplement.



Figure 3-1 The Project Manager

The Project Manager performs the following functions:

• automatically loads all design resources when opening a project

• checks that all project resources are available and up-to-date

• illustrates the design process flow

• initiates applications used in the design process

• displays error and status messages in the message window

• provides automated data transfer between various Foundationdesign tools

• displays design status information

Foundation Toolset


Project DefinitionFoundation organizes related files into a distinct logical unit called aproject. Related files include the following:

• project documents (schematics, HDL source files, and statediagram files)

• output and intermediate files (netlists, bitstreams, report and logfiles)

• configuration files

Each project is stored in a separate subdirectory, named the projectworking directory. The name of the project directory is the same as thename of the project. The project displays in the Hierarchy Browserportion of the Project Manager.

Figure 3-2 Hierarchy Browser

For each project, the Project Manager creates a configuration filecalled the Project Description File (PDF). The PDF file has the samename as the project plus the .pdf extension. The PDF file is stored atthe top-level of the associated project directory.

For more information about the PDF file and other projectinformation, refer to the online help by selecting Help →Foundation Help Contents . Click Project Manager.



Starting the Project ManagerTo start the Project Manager, click the Project Manager icon on thedesktop or select Start → Programs → Foundation Series →Foundation Series Project Manager . The Project Managermain window displays as shown in the “The Project Manager”figure.

Project Manager Project ContentsThe Project Manager may display the following file types.

Schematic Files

You create schematic files when you design your schematic withinthe Schematic Editor. The schematic files have the .sch extension. Formore information about the Schematic Editor, refer to the “SchematicDesign Entry” chapter or select Help → Foundation HelpContents . Click Schematic Editor.

HDL Text Files

The HDL Editor creates HDL source files for the XABEL (.abv, .abl)and VHDL (.vhd) hardware description languages. For moreinformation about the HDL Editor, refer to the “HDL Design Entryand Synthesis” chapter or select Help → Foundation HelpContents . Click HDL Editor.

State Editor Files

State diagrams created with the State Editor have the default fileextension .asf. For more information about the State Editor, refer tothe “State Machine Designs” chapter or select Help → FoundationHelp Contents . Click State Editor under Tools or The State Editorunder Tutorials.

Foundation Toolset


Simulation Test Vectors

Test vectors are used as input signals that stimulate a design togenerate simulation results. Test vector files (.tve) can be created inthe Logic Simulator. For more information about creating test vectors,select Help → Foundation Help Contents . Click Logic Simulatorand read the Getting Started Tutorial. Also, refer to the “AllSchematic Designs” section of the “Design Methodologies” chapter.

Project Manager TabsThe Foundation 1.4 Project Manager project flowchart windowcontains 5 new tabs that allow you to obtain current informationabout your displayed project and facilitate the design process.

Contents Tab

The Contents tab displays the full pathname of the project displayedin the hierarchy tree. This tab also displays the date that the projectwas last modified.

Status Tab

The Status tab displays the current status of the project schematicnetlist (for schematic designs only), the EDIF netlist, and the designimplementation. Following is a sample display for the calc_4keproject.

Figure 3-3 Sample Status Tab Display



The example indicates that the schematic netlist for the design iscurrent. However, the EDIF netlist and the design implementationare not current. To update the netlist, click the EDIF netlist box. Thenew netlist displays a check mark instead of an “X”. To update thedesign implementation, click the XACTstep M1 box.

You can also display the EDIF netlist by clicking the cylinder locatedto the right of the EDIF netlist. Click on the cylinder located to theright of the XACTstep M1 box to display the EDO file.

Reports Tab

Select this tab to display reports that have been generated in thedesign entry design process. The Reports tab does not display anyreports created by the Design Manager.

Synthesis Tab

Using the Synthesis tab, you can update or synthesize VHDL, ABEL,and State Machine macros.

Accessing LogiBLOX from the Project ManagerLogiBLOX is a graphical interactive tool for creating high-levelmodules, such as counters, shift registers, and multiplexers.LogiBLOX includes both a library of generic modules and a set oftools for customizing them. You can access LogiBLOX from theProject Manager by selecting Tools → LogiBLOX , from theSchematic Editor by selecting Options → LogiBLOX or from theHDL Editor by selecting Synthesis → LogiBLOX . The lbguiprogram is invoked which opens the LogiBLOX Module Selectordialog box. For details about creating LogiBLOX modules, refer to the “Creating LogiBLOX Modules” section of the “LogiBLOX” chapter.

Documenting Your DesignTo attach text files or other files to the Project, perform the followingsteps.

1. Select Document → Add.

2. In the Add Document dialog box, select the documents from theFiles list box.

3. Click OK.

Foundation Toolset


The files will then be displayed in the Project Contents browser area.This is a convenient way to provide documentation for your design.Note that you can add almost any kind of file to the project.

By double clicking on the file name in the Hierarchy Browser area,the application that is associated with the file type is invoked. Forexample, if you double click on a schematic file, the Schematic Editordisplays the schematic file. To learn more about how to use thehierarchy browser, perform the following steps:

1. Select Help → Foundation Help Contents .

2. Click Project Manager.

3. Select the Index tab.

4. Type “hierarchy browser” in the search box.

5. Double click “hierarchy browser” in the list box.

Project ArchivingFoundation 1.4 supports automatic project file zipping whenarchiving. Previously, third-party software, such as PKZIP, wasrequired. Likewise, the Foundation Project Manager contains aRestore Project option to automatically unzip archived projects.(File → Restore Project ).

Foundation 1.4 also supports archiving of symbol libraries as well asentire projects. To archive symbol libraries, perform the followingsteps:

1. Select File → Archive Project .

2. Select Next from the Archive Project Wizard - Setup window.

3. Select Add Libraries and then select the libraries from the list boxthat you want to archive.

4. Select Next to begin library archiving.



Design Entry ToolsFoundation provides a suite of tools for creating digital circuitdesigns. This section describes these design entry tools.

Schematic EditorWith the Schematic Editor, a primary Foundation design entry tool,you can create multi-sheet hierarchical schematics. The editorfeatures include the following.

• multiple sheet, flat, and hierarchical schematic support

• Viewlogic schematic import

• board-level and FPGA schematic support

• export of schematic netlists to XNF, EDIF, and VHDL formats

• integration with synthesis design tools (HDL Editor and StateDiagram editor)

• integration with Logic Simulator for non-schematic simulation

For detailed information about the Schematic Editor, select Help →Foundation Help Contents from the Project Manager mainwindow. Click Schematic Editor. Also, see the “Schematic DesignEntry” chapter.

Foundation 1.4 also supports many new features. See the “SchematicEditor” section in the Foundation Series Quick Start Guide 1.4 for acomplete list.

HDL EditorThe HDL Editor, a text editor, is designed to edit HDL source filescreated in either the VHDL or ABEL languages. The HDL Editor alsoprovides commands for hierarchy operations and utilizes syntaxcoloring for both the VHDL and ABEL languages. The Editoroperates in both hierarchical and non-hierarchical mode.

The Language Assistant tool furnishes templates with source code forboth VHDL and ABEL. There are two types of templates:

• language templates with basic language constructs

• synthesis templates of functional blocks, such as counters, flip-flops and multiplexers

Foundation Toolset


For detailed information about the HDL Editor, select Help →Foundation Help Contents from the Project Manager mainwindow. Click HDL Editor. Also, refer to the “HDL Design Entryand Synthesis” chapter.

State EditorState machine designs typically start with the translation of a conceptinto a “paper design,” usually in the form of a state diagram or abubble diagram. The paper design is converted to a state table andfinally into the source code itself. The State Editor, which allows youto create state machine designs, also supports the following:

• generates behavioral VHDL code from the state diagram.

• invokes the VHDL compiler to convert the behavioral descriptioninto a gate-level EDIF netlist.

• simulates a state diagram macro graphically.

For more information about how to use the State Editor, select Help→ Foundation Help Contents from the Project Manager mainwindow. Click “The State Editor” under Tutorials. Also refer to the“Using the State Editor (Optional)” section of the Foundation SeriesQuick Start Guide 1.4.

Logic SimulatorThe Logic Simulator, a real-time interactive design tool, can be usedfor both functional and timing simulation of designs. The LogicSimulator creates an electronic breadboard of your design directlyfrom your design’s netlist. The breadboard is tested with signalscalled test vectors. Each test vector lists logical states of all stimulussignals at a selected time interval. For more details on how to use theLogic Simulator, select Help → Foundation Help Contents fromthe Project Manager main window. Click Logic Simulator. Also seethe “Functional Simulation” chapter and the “Post-implementationTiming Simulation” chapter.



XVHDL CompilerThe compiler synthesizes and generates EDIF 2. 0.0 from Metamor™VHDL code or state machine designs. The synthesized netlist is thenoptimized by the M1 implementation tools. Optimization control isalso supplied in the Synthesis Options dialog box in the HDL Editorand the State Editor.

Library ManagerThe Library Manager allows you to perform a variety of operationson the design entry tools libraries and their contents. These librariescontain the primitives and macros that you use to build your design.

The Foundation design entry tools contain two types of libraries:system libraries and user libraries.

• System libraries, which are supplied with the Foundation designentry tools, contain sets of components for specific design types.System library contents cannot be modified. The Foundationsystem libraries include SIMPRIMS, XABELSIM, XC3000,XC4000E, XC4000EX, XC5200, XCS, and XC9500.

• User libraries contain user-defined components. Each project hasat least one user library, which is named the same as the projectand is located in the LIB subdirectory of the project directory.These libraries can only be modified within the Library Manager.

You can access the Library Manager by selecting Tools → LibraryManager from the Project Manager.

For more details on how to use the Library Manager, select Help →Foundation Help Contents from the Project Manager mainwindow. Click Library Manager.

Symbol EditorWith the Symbol Editor, you can edit features of component symbolssuch as pin locations, pin names, pin numbers, pin shape, and pindescriptions for component symbols.

You can access the Symbol Editor by selecting Tools → SymbolEditor from the Project Manager.

Foundation Toolset


For more details on how to use the Symbol Editor, select Help →Foundation Help Contents from the Project Manager mainwindow. Click Symbol Editor.

Design Implementation ToolsOnce you have completed design entry, you can implement yourdesign using the Xilinx design implementation tools, which youaccess from the Xilinx Design Manager.

Design ManagerTo access the Design Manager, click the Implement M1 icon located inthe Project Flowchart of the Project Manager.

You can use the Design Manager to implement a design in FPGAs orCPLDs. The Design Manager provides access to all the tools you needto read a design file created with the design entry tools andimplement it in a Xilinx device.

The Design Manager performs the following functions:

• creates multiple design versions for management of designchanges

• creates multiple implementation revisions which helps youmanage one or more implementation strategies

• accesses analysis reports

• accesses all design implementation tools, such as the FlowEngine, Timing Analyzer, PROM File Formatter, HardwareDebugger, EPIC Design Editor, and JTAG Programmer

• exports timing data to simulation tools

• exports configuration data



Managing Projects

The Design Manager window displays all Xilinx data related to asingle project. A project includes all design versions andimplementation revisions that are created as you implement yourdesign. You can work with multiple projects, but only one is active ata time. The hierarchical structure shows you the relationships of thedata elements to each other.

Managing Design Versions

You create your design using third party front-end tools such asschematic editors and HDL. The Design Manager reads in the designand creates a design version in the Design Manager project view. TheDesign Manager manages the design versions that it creates.

Each time you change the logic of your design, you must create a newdesign version. The Design Manager reads in the modified design tocreate the new design version. If old design versions are specified,they are automatically overwritten.

You can try modified versions of your design and easily keep track ofthem. Each new file that you create becomes a new design versionand is assigned a version name by the Design Manager. You canchoose any one of the available versions for processing. For eachversion, you can create multiple implementation revisions. For eachrevision, you can target a different device family and choose differentprocessing strategies, such as optimizing for area or speed.

Managing Implementation Revisions

After you create a design version, you can try differentimplementation strategies on that design. This method allows you tovary how your design is implemented in order to achieve yourdesign objectives. For example, you can maximize speed and densityin your design by controlling the implementation settings.

Foundation Toolset


The data associated with each of these implementation strategies iscalled an implementation revision. Each revision contains the datafiles and reports that are created based on a specific set ofimplementation strategies. You can delete revisions that are no longeruseful.

For more information about the Design Manager, see the DynaTextonline document, Design Manager/Flow Engine Reference/User Guide.

XProject Directory

In design implementation, the Design Manager automatically createsa directory named xproject and appends it to the work directory. TheDesign Manager uses the xproject directory to store all the data filesfor the project such as the files created by the Xilinx Design Managerwhen design versions and revisions are compiled.

Flow EngineThe Design Manager manages your Xilinx designs. The Flow Engineimplements your designs. The Flow Engine is tightly coupled withthe Design Manager, sharing many of the same menus and dialogboxes.

The Flow Engine allows you to easily process your design, control theimplementation of your design, and guide your implementationrevisions. For more information, see the “Implementing a Design”section of the “An Introduction to Design Implementation” chapter.




Chapter 4


This chapter contains the following sections:

• “Managing Schematic Designs” section

• “Hierarchical Schematic Designs” section

• “Manually Exporting a Netlist” section

• “Creating a Schematic from a Netlist” section

• “Miscellaneous Tips for Using the Schematic Capture Tool”section

Refer to the “Top-level Schematic Designs” section of the “DesignMethodologies” chapter for several examples of top-level schematicdesigns.

Refer to the “VHDL Designs with Instantiated Schematic Macros”section of the “Design Methodologies” chapter for an example ofinstantiating a schematic macro into a VHDL design.

Managing Schematic DesignsThe following subsections describe various features of the schematicdesign tool. To access the Schematic Editor from the ProgramManager, click the Schematic Editor icon.

The Schematic Capture window displays.



Figure 4-1 Schematic Capture Window

Design StructureYou can create Foundation schematic editor designs that have thefollowing structures:

• single sheet designs

• multi-sheet designs

• hierarchical designs

Selecting a structure depends on the design size (number of symbolsand connections), purpose (board or chip design), and companystandards. The following sections describe each of these design types.

Single Sheet SchematicSingle sheet designs are typically used for small designs. The largestpage size is 44” x 34” (size E). The major advantage of a single sheetschematic is that you can use physical connections for an entiredesign, which makes tracking of the connections easier.

The disadvantages of using large pages are:



• Schematics redraw slowly. A schematic with many symbols maytake a long time to scroll.

• Large schematics must be printed on plotters instead of laserprinters.

Multi-sheet Flat SchematicIf a design is too large to print on a single sheet, you can use a multi-sheet design structure. When you create a new sheet, it isautomatically added to the current project. To make connectionsbetween schematic sheets, you must make logical connections byusing the same net names, I/O terminals or bus taps on all schematicsheets. For example, if you use the I/O terminal CLOCK on sheet 1and net name CLOCK on sheet 2, then both names becomeconnected.

These connections can be confirmed by using the Query option. Toactivate the Query option select Mode → Query from the SchematicCapture main window and then select items on the schematic. To findout more about Query options, select Help → Schematic EditorHelp Contents from the Schematic Capture main window. Selectthe Index tab. Type Query in the search list box. Double click“querying connections.”

Following are the advantages of using the multi-sheet designstructure.

• small sheet sizes that print on laser printers

• unlimited design sizes without condensing the schematics

The disadvantage of using multi-sheet schematics is that connectivityerrors between sheets are detected only when the netlist is created.The Query window can help trace these connections.

Note: All reference designators for symbols in the multi-sheetschematics must be unique. The Foundation design entry toolsautomatically assign these unique numbers. If you manually assignthe same reference numbers to two different devices, an error isreported when you create a netlist.



Hierarchical SchematicSince large number of symbols are used in FPGA and CPLD designs,handling large designs using the multi-sheet design structure canbecome very difficult and complex. Large designs typically requirethousands of simple primitives like gates and flip-flops. To simplifyschematics, designers prefer to use high-level components that haveclear functionality. These high-level components are implementedusing hierarchical macros. A hierarchical macro, a device in thelibrary that looks like a standard component, is implemented as anetlist or schematic. For example, you can create an equivalent of acounter by drawing a macro schematic with only gates and flip-flops.This macro can then be saved and reused in your designs. SeveralFPGA libraries already contain a number of hierarchical macros.

Hierarchical designs are very effective with IC designs. Inhierarchical macro schematics, all net names and reference names arelocal, which means that you can use the same signal names indifferent macros.

The connections between hierarchical macros and the rest of thedesign is made via I/O terminals. These terminals are converted intohierarchical symbol pins. See the following figure.

Figure 4-2 Hierarchical Design Structure

X8191

I/O terminal becomes a macro pin



After the macro symbol is placed on the schematic sheet, you canconnect wires to these pins on the macro. Only the signals shown assymbol pins can be connected.

Some advantages of hierarchical designs follow:

• The symbols in a hierarchical schematic library can representlarge functional blocks implemented in detail on a lower level. Byviewing the high level schematic, you can see the general designstructure without being overwhelmed by the lower level details.

• Top-down or bottom-up methodology assists in teamdevelopment by defining design sections for each designer. Allconflicts between design sections are eliminated by allowinginterfaces only to explicitly defined pins and bus pins.

• You can use multiple instances of the same macro. If you use aschematic sheet in a flat design, you must duplicate the macro foreach instance. If you then make a correction to the macro, youmust edit all instances. The hierarchical macro is modified onceand all instances are then updated.

• Macros can be used in multiple projects. You can develop a set ofreusable modules that are stored as hierarchical macros and usedin several designs.

Following are some of the disadvantages of hierarchical designs:

• Netlist names can become very long. The method used to createunique reference identifiers adds the hierarchy reference name toeach symbol reference. For example, a symbol U58 in a macrocalled H8 will be called H8/U58. In multilevel hierarchicaldesigns, these names can become very long depending on thenumber of hierarchy levels.

• Updating macros often requires changing their symbols, whichthen means that you must correct all schematics that use thatmacro.

Adding New Sheets to the ProjectTo create a new empty sheet, select File → New Sheet . The newsheet receives the name of the project with the sequential sheetnumber assigned to it automatically. You can save the sheet with adifferent name by selecting File → Save As . Each new sheet isautomatically added to the project contents in the Hierarchy Browser.



To open a sheet that does not belong to the project, select File →Scratchpad . To add a scratchpad sheet to the project, use the File→ Save As option to define the schematic name. Then selectHierarchy → Add Current Sheet to Project .

Adding Existing Sheets to the ProjectTo add an existing schematic sheet to your project, selectHierarchy → Add Sheets to Project . In the Add to Projectwindow, select the schematic file(s) you want to add and click theAdd button. The schematic editor loads each added sheet and verifiesthat the symbols used in these schematics are available and that thereare no duplicate reference numbers. The list of project sheets is thenupdated.

Note: The schematic editor automatically adds libraries used by itsschematic sheets to the current project even if they are not listed inthe project libraries. The libraries are added when you open aschematic file and symbols are not found in the current projectlibraries.

Opening Non-project SheetsWhen you select File → Open, only the sheets that belong to thecurrent project are shown. If you want to open a sheet that does notbelong to the current project, use the Browse button to select aschematic file from any disk. The schematics opened with the Browseoption display the Cannot Edit message in their title bar. These sheetscan only be viewed, but they cannot be edited.

To edit such schematics, select Hierarchy → Add Current Sheetto Project . The currently selected sheet, which is then added to thecurrent project, can then be edited. The schematic is copied to thecurrent project directory, so the changes do not affect other projects.

Removing Sheets from the ProjectTo remove a sheet from the project, in the Project Manager, select theschematic sheet that you want to remove and select Document →Remove. Click Yes.



Note: Deleting the sheet from the project does not delete theschematic file from the disk. If you want to delete unwanted files, youcan use the Windows Explorer and delete *.SCH files from the projectdirectory.

Renumbering Symbol ReferencesThe reference numbers are assigned sequentially in the order inwhich you place symbols on different sheets. As a result, the symbolreference numbers in the multi-sheet schematics can be random. Toorder the symbol numbers, you may want the symbol referencenumbers to correspond to different sheets. For example, symbols onthe first sheet may start with U100, and symbols on the second sheetmay start with U200.

To renumber project sheets and the associated symbol referencenumbers, proceed as follows:

1. Select Options → Annotate .

2. From the Annotation window, select the Whole Project option. Inthe Sheets section, enter 100 in the Increment field.

3. Press the Annotate button.

4. Press the Close button.

Figure 4-3 Annotation Dialog Box



Copying a Section of a Schematic to Another SheetIf you want to move or duplicate a section of a schematic to anothersheet, perform the following steps:

1. Place the cursor at the corner of the area to be copied, depress themouse button and drag the cursor to outline a rectangular areafor selection. All items within the selected area are selected whenyou release the mouse button.

2. To select additional objects on the schematic sheet withoutdeselecting the currently selected object, use the Shift key.

3. Use the Copy or Cut options in the Edit menu. The Copy optioncopies the selected objects to the clipboard. The Cut option copiesthe selected block to the clipboard and deletes it from theschematic. The clipboard is a temporary sheet that stores thecopied objects.

4. Go to the sheet where you want to paste the schematic objectsand select the Paste option from the Edit menu. A rectangle isdisplayed at the cursor position. You can move it around theschematic to position the copied block to the desired location.

5. Press the mouse button to confirm the location of the pastedblock.

Note: The selected schematic block contains all wires internal to theblock, that is, between symbols or labels within the selected area. Allwires connected to symbols outside the area are not copied to theclipboard.

Troubleshooting Project ContentsThe project contents is stored in the binary file *.PDF. The file name isthe same as the current project name, and it is located in the projectdirectory. If the project contents file is corrupted, you can delete it andrecreate it by adding all sheets to the project again.

If a netlist creation error is reported, try removing one sheet at a timefrom the project until the netlist can be successfully created. Thenanalyze the last-removed sheet for any possible errors.



Hierarchical Schematic DesignsA design has a hierarchical structure if any of the symbols on theschematic sheet contain a netlist or schematic. The hierarchicalmacros may be user-created or may already exist in a library. If youuse one of these symbols, your design becomes hierarchical.

Creating a Hierarchical SchematicBefore you start drawing a schematic, make sure that you haveassigned the necessary libraries to the project. First select File →Project Libraries . When the Project Libraries window displays,select the appropriate libraries and then press the Add button. Thisoperation transfers the selected libraries from the Attached librarieswindow to the Project Libraries window, which makes these librariesavailable to the Schematic Editor.

Next, enter your schematic design, just like any other flat design,with the following constraints:

• Each macro is a self-enclosed entity; any connection to othersheets can only be performed through I/O pins.

• The schematic I/O pins must be specified explicitly as eitherInput, Output or Bidirectional. This specification is importantbecause the design entry tools automatically generate arectangular DIP symbol; the location of the pins on the symboldepends upon their schematic I/O definition (only inputs are onthe left-side of the symbol outline). If needed, edit this symbol inthe Symbol Editor.

Recognizing Hierarchical MacrosHierarchical macro symbols can be recognized by their color. Bydefault, the schematic-based macros are dark blue. The netlist-basedmacros are purple. You can change these default colors by selectingView → Preferences → Colors .

Navigating the Project HierarchyYou can view the schematic of a hierarchical symbol by selectingHierarchy → Push . When the H cursor is active, double click on asymbol to display its schematic. If you double click on a symbol thatdoes not have a schematic, the following message displays:



Symbol is a primitive cell.

To exit the H cursor mode, select Hierarchy → Pop.

You can also navigate the hierarchical structure of the design from theHierarchical Browser window shown in the next figure.

Figure 4-4 Hierarchical Browser

Hierarchy sublevels can be expanded or collapsed by double-clickingon the + or - icons.

The Hierarchical Browser window shows the hierarchical design tree.A plus (+) designates a hierarchy with additional (not shown)hierarchical sublevels. You can open them by double clicking on theseicons.

A minus (-) denotes a hierarchy that already shows lower hierarchylevels. Double clicking on the - symbols inside the icons, reduces thehierarchy to the higher levels, which simplifies the viewing of verycomplex designs.

An icon with no symbol indicates that the given hierarchical level hasno additional hierarchical sheets.

Note: Double clicking on the schematic name loads that schematic tothe screen for viewing and editing.



Modifying Existing MacrosIf you want to make some changes to an existing macro schematic,perform the following steps:

1. Bring up the schematic of the macro by invoking the H cursorand double clicking on the macro symbol.

2. Select the Select and Drag toolbar button to enter edit mode.

3. Make changes to the schematic.

4. Select File → Save .

When you change and save a hierarchical macro, you change allinstances of this macro in the entire design. If the modified macroschematic has different I/O pins, its symbol changes and the pinsmay not match their previous locations on the schematics. If thishappens, the wrong wires are automatically disconnected and will bemarked with crossed circles. These wires must be manuallyreconnected by dragging the crossed circles over the target pins andthen releasing the mouse button.

If you edit a macro from the system library that comes with theproduct, you cannot save it in the system library. You can only save itas a project library. For clarity, use a different name for the modifiedmacro so that you can always be sure which symbols are currentlyused on the schematics.

Difference between a Macro and a SchematicThe following example explains what happens with the hierarchicalschematic when you create a macro. Assume that the project TESTcontains the schematic sheets TEST1 and TEST2. Create a macro forthe schematic sheet TEST2 as follows:



1. Using the Hierarchy → Create Macro Symbol FromCurrent Sheet option, convert the TEST2 schematic into amacro called MACRO1 in the TEST project library.

The old schematic sheet TEST2 still resides in the projectdirectory. You can open this schematic file, but there is no longerany relationship between the TEST2.SCH schematic file and theTEST project or MACRO1.

2. Use the Windows Explorer to delete the file TEST2.SCH from theproject directory.

Hierarchy Symbol ChangesIf you update a hierarchical macro, its symbol is not modified unlessthere is a different number of I/O pins. When the number of pinchanges, a new symbol is generated based on the new I/O pins,which may result in incorrect connections on the schematics that havepreviously used the symbol. The schematics that are currently openare automatically updated with the new symbol when you make thechange. Other schematics are updated when you open them in theSchematic Editor.

When the symbols do not match the previous connections, the wiresare automatically disconnected from that symbol, and a crossed circleis displayed at the end of these wires. To correct these connections,you can drag the circles and drop them at the appropriate pins.

You can edit the newly created symbol in the Symbol Editor programso that it matches the old pin locations.

Using a Top-down MethodologyTo implement a top-down design, you must first create emptysymbols for hierarchical macros. These empty symbols will then beimplemented as schematic macros.

1. To create an empty symbol, select the Hierarchy → NewSymbol Wizard . Click Next. Choose Empty in the Contentssection.

2. Enter the Symbol Name and select Next.

3. In the Design Wizard - Ports dialog box, select New.



4. Enter all ports including bus pins and power supply pins, if any.Select Next.

5. In the Design Wizard - Attributes, enter a reference for the newsymbol. Select Next.

6. Click Finish in the Design Wizard - Contents window.

7. Place the empty symbols on a schematic sheet and make therequired connections. Note that the empty symbols are red.

8. Invoke the H cursor and double click on the selected emptysymbol.

9. When the message displays, “Do you want to create ahierarchical macro?”, respond Yes.

An empty schematic sheet appears with the selected symbols’input pins located to the left and the output pins located to theright.

10. Enter the design and select File → Save .

Instead of drawing a schematic inside an empty symbol, you canassign a ready-made design netlist to an empty symbol by selectingHierarchy → Assign Netlist and then clicking on the symbol.The Netlist Conversion window lets you select the desired netlist.The imported netlist can be automatically converted into a schematicif you select the Schematic import option in the Netlist Conversionwindow.

Hierarchical Design ExampleThis example explains how to create and use a hierarchical design.

1. Create a new project called MACROS.

a) From the Project Manager, select File → New Project .

b) In the Name field of the New Project window, enterMACROS and click OK.

2. Create the MACROS1 schematic shown in the “MACROS1Schematic” figure.

a) Click the Schematic Editor button.



b) Select the Symbol mode in the schematic toolbar and in theSC Symbols toolbox, select the NAND2 symbol.

c) Draw the schematic shown in the “MACROS1 Schematic”figure including the input terminals, (INA, INB, INC) andoutput terminal (OUT). Use the I/O Terminal icon to drawthe input and output terminals. Make sure you add the inputand output buffers.

F

d) Connect the symbols (Mode → Draw Wires ).

Symbol dimensions and pins may be edited using theSymbol Editor. To open the Symbol Editor, select Options →Symbol Editor from the Schematic Editor, or double clickon the placed symbol, and click the Symbol Editor button onthe Symbol Properties dialog box. For more information onusing the Symbol Editor, refer to the Symbol Editor’s onlinehelp (Help → Contents ).

e) Save the schematic using File → Save . The schematic isautomatically named as MACROS1.

Figure 4-5 MACROS1 Schematic

3. Create the MACROS1 symbol.

a) Select Hierarchy → Create Macro Symbol FromCurrent Sheet . The Create Symbol window should displaythe symbol name MACROS1. Click on that name and changeit to ONE, which will be the name of the hierarchical macrosymbol. In the Input pins section, make sure that thefollowing list of pins is entered: INA, INB, INC. Ensure thatOUT is entered in the Output field.



b) Click on the OK button. The netlist and the MACROS1schematic are saved in the project library and a graphicalsymbol is automatically created.

4. Create the second schematic (MACROS2).

a) Select File → New Sheet . A new schematic MACROS2 isautomatically opened.

b) Select the Symbol mode in the schematic toolbar and in theSC Symbols toolbox, select the FD symbol.

c) Draw the schematic shown in the “MACROS2 Schematic”figure including the input terminals (D, CLK) and outputterminal (OUT). Use the I/O Terminal icon to draw the termi-nals. Make sure you add the input and output buffers.

d) Connect the symbols (Mode → Draw Wires ).

Symbol dimensions and pins may be edited using theSymbol Editor. To open the Symbol Editor, select Options →Symbol Editor from the Schematic Editor, or double clickon the placed symbol, and click the Symbol Editor button onthe Symbol Properties dialog box. For more information onusing the Symbol Editor, refer to the Symbol Editor’s onlinehelp (Help → Contents ).

Figure 4-6 MACROS2 Schematic

e) Save the schematic using File → Save . The schematic isautomatically named as MACROS2.



5. Create the MACROS2 symbol.

a) Select Hierarchy → Create Macro Symbol FromCurrent Sheet . The Create Symbol window should displaythe symbol name MACROS2. Click on that name and changeit to TWO, which will be the name of the hierarchical macrosymbol. In the Input pins section, enter pins: CLK, D. EnterOUT in the Output field. Note that only I/O terminals arerecognized as pins for the symbol.

b) Click on the OK button. The netlist and the MACROS2schematic are saved in the project library and a graphicalsymbol is automatically created.

c) Save the schematic using the Save option.

6. Create a new sheet for the top level.

a) Select File → New Sheet . The empty sheet calledMACROS3 opens.

b) Select Mode → Symbols and find symbol ONE in the SCSymbols toolbox. Place two copies of that symbol, which areautomatically called H1 and H2, on the schematic. Similarly,place two copies of the TWO symbol on the schematic. Thesesymbols are automatically named H3 and H4. Refer to thefollowing figure for placement details.

Figure 4-7 Top Level Schematic



7. Use the Push/Pop option to view schematics.

Select Hierarchy → Hierarchy Push . A cursor with the letterH displays. Point the cursor at the Symbol H1 and double clickthe mouse button. The schematic ONE opens showing you theschematic of the symbol H1.

8. View the project contents in the Hierarchy Browser of the ProjectManager.

Manually Exporting a NetlistExternal programs used in the Foundation Series software requirenetlist in proprietary text formats such as XNF, EDIF, and structuralVHDL.

To export the project netlist, perform the following steps:

1. Select Options → Export Netlist . The Export Netlist dialogbox displays.

2. From the Netlist Format list box, select the desired format.

3. If you want to use a specific extension for the exported netlist file,use the Options button.

4. Choose the source netlist ALB file. By default, the project netlist isautomatically selected.

5. Click OK to start exporting.

Note: The XNF netlist format is not recommended for use with theM1 Design Implementation Tools.

Creating a Schematic from a NetlistYou can generate a schematic from an existing netlist. The SchematicEditor generates a schematic file and inserts it into the projectdirectory as a non-project document. You can then use File → Openor add it to the project with Hierarchy → Add Sheets toProject . The names of automatically generated schematic filesbegin with the underline character (_). The underline character isfollowed by four initial letters of the project name and a three-digitsuffix: 001 for the first file, 002 for the second, and so forth.

To generate a schematic from a netlist, perform the following steps:



1. Select File → Generate Schematic from Netlist . TheGenerating Schematic dialog box displays.

2. Select the desired netlist type from the List Files of Type list box.Then select the desired netlist file.

3. Click the Options button to display the Page Setup dialog boxwhich allows you to select the desired page size and orientation.

4. Select the page size to be used for the generated schematics. Thesmaller the page size you select, the more numerous are the sche-matic files that are generated.

5. Select Landscape or Portrait.

6. Select Wireless to implement all connections using the connect-by-name method.

7. Click OK.

Miscellaneous Tips for Using the SchematicCapture Tool

This section describes various tips for creating schematic designs.

Color-coded SymbolsSymbols are color-coded to represent their type.

• schematic user macros — blue

• primitives and empty symbols — red

• HDL, State Editor, and netlist macros — purple

• State Editor macros — purple

• library macros — black

These color codes are the default values. If you wish to change thedefaults, select View → Preferences → Colors .

Using VCC and GNDUse the toolbar button to create VCC and Ground.



Using the I/O Terminal ComponentOnly use the I/O terminal component when specifying pins for aschematic macro that you want to create from a schematic.

Using Input and Output BuffersXilinx schematics require that you use input and output buffersbetween input and output ports. The following figures illustrateincorrect and correct input and output port design.

Figure 4-8 Incorrect Port Design (Without Buffers)

Figure 4-9 Correct Port Design (With Buffers)

Schematic TabsFoundation 1.4 supports new schematic tabs on a schematic sheetwhich facilitates navigation between schematic sheets. Following isan example of the tabs that display after opening the schematics forthe sample “lock” project.



Figure 4-10 Schematic Tabs Example

Note the LOCK1 and LOCK2 tabs in the lower left corner of thefigure. Click LOCK2 to navigate to the LOCK2 schematic sheet. Forevery new schematic sheet added to the design, a new tab displays.

In addition, if you use Hierarchy → Push to display the schematicfor a component or macro, a new tab also displays in the lower leftcorner.

Simulate Current MacroIn Foundation 1.4, you can simulate a macro in a schematic design:

1. Select the macro in your design.

2. Click Hierarchy → Push and then double click the design.

3. After the design displays, select Options → SimulateCurrent Macro . When the Logic Simulator window displays,you can perform a functional simulation of the macro. Refer tothe “Functional Simulation” chapter for details.


Chapter 5

HDL Design Entry and Synthesis

This chapter describes how to create hierarchical VHDL designs,explains how to manage large designs, and discusses advanceddesign techniques.

For information about CPLD VHDL designs, select Help →Foundation Help Contents from the Project Manager. UnderTutorials, click CPLD design flows. Click either the hypertext link,VHDL- Stand Alone Design or Creating a New VHDL or ABELDesign.

Refer to the “Top-level VHDL Designs” section of the “DesignMethodologies” chapter for several examples of top-level VHDLdesigns.

If you purchased the Foundation Express package, refer to theFoundation Express Application Note Supplement for instructions onhow to create VHDL or Verilog designs with the Foundation Expresssoftware and implement these designs in the Foundationenvironment.


• “VHDL File Selection” section

• “Creating a Hierarchical VHDL Design” section

• “Synthesis of the HDL Modules” section

• “Managing Large Designs” section

• “Advanced Design Techniques” section



VHDL File SelectionTo begin entering or editing a design in VHDL, click the HDL Editoricon, which is part of the flow diagram on the right side of theFoundation Project Manager. A dialog box displays which presentsoptions for a design file, as shown in the following figure.

Figure 5-1 HDL Editor

• Use HDL Design Wizard

Use this option for new designs. The Wizard will ask youquestions about the design name, language to be used, and portnames. When finished, “skeleton” code pops up, complete withthe library, entity, ports, and architecture already declared.

• Create Empty

Use this option for new designs. This option starts the HDLEditor and displays a blank page.

• Existing Document

Use this option to select an already existing HDL file.

• Active document



The current document in the hierarchy project view, located onthe left side of the Project Manager.

Adding the File to the ProjectA Foundation project always has one or more “top-level” designfile(s). These top-level files may be HDL file(s) (VHDL or XABEL) orschematic file(s). You can see what the top-level of the project is bylooking at the hierarchical project view, located on the left side of theProject Manager.

Underneath the project’s .PDF file, you will see either .SCH file(s),.VHD file(s), or .ABL file(s) listed. You can have multiple files of thesame type at the top-level, but you cannot mix file types. For instance,you can have three .SCH files as top-level files, or you can have three.VHD files listed as top-level files, but you cannot have both a .VHDand a .SCH listed as top-level files.

When doing a top-level VHDL design, it is necessary to “add” theVHDL file to the project, so that Foundation understands that it is atop-level VHDL design. This can be done from within the HDLEditor by choosing Project → Add to Project . Alternatively, youcan both add files to and remove files from the project by selectingDocument → Add or Document → Remove from the ProjectManager.

Getting Help with the LanguageThe Foundation HDL Editor provides HDL language assistancethrough both the Language Assistant and the Online SynthesisDocumentation. The Language Assistant, shown in the followingfigure, provides templates to aid you in common VHDL constructs,common logic functions, and architecture-specific features. To accessthe Language Assistant, open the HDL Editor, and select Tools →Language Assistant .



Figure 5-2 VHDL Language Assistant

Additional documentation related to the synthesis tools can be foundin the Help menu.

Creating a Hierarchical VHDL DesignXilinx recommends limiting individual VHDL files to 4000 gates orless. This limitation helps to reduce runtime of both the synthesizerand also of the MAP program in the implementation flow.

Consequently, when you have a VHDL design that targets a Xilinxdevice larger than 4000 gates, you should create a hierarchical design,where no one module in the design describes more than 4000 gates.For this type of design, there will be one top-level VHDL file, whichhas various other lower-level VHDL modules instantiated in it. Thistop-level file should not include much logic at all, but rather providethe connections linking the other lower-level modules together. Thefollowing example shows a top-level VHDL file with a lower-levelVHDL module instantiated in it.





a_top, d_in_top, clk_top, rst_top: in STD_LOGIC;not_a_top, q_out_top: out STD_LOGIC

);end top_vhd;

architecture top_vhd_arch of top_vhd iscomponent my_module

port (a, d_in, clk, rst: in STD_LOGIC;not_a, q_out: out STD_LOGIC

);end component;

beginU1: my_module port map (a=>a_top, d_in=>d_in_top, clk=>clk_top,

rst=>rst_top, not_a=>not_a_top, q_out=>q_out_top);end top_vhd_arch;

my_module is the name of the entity in the module to be instantiated.The following is the lower-level VHDL module being instantiated:


entity my_module isport (

a, d_in, clk, rst: in STD_LOGIC;not_a, q_out: out STD_LOGIC

);end my_module;

architecture my_module_arch of my_module isbegin

not_a <= not a;process (clk, rst)begin

if rst=’1’ thenq_out <= ‘0’;

elsif (clk’event and clk=’1’) thenq_out <= d_in;

end if;end process;

end my_module_arch;



Synthesis of the HDL ModulesThere are two different design flow methodologies that you can usewhen compiling a hierarchical VHDL design. These two methods are:

• top-down

• bottom-up

In the top-down methodology, all VHDL files are added to theproject, and then all synthesized at once. In the bottom-upmethodology, only the top-level VHDL file is added to the project,and each file is synthesized separately.

Top-down MethodologyUsually, the top-down approach provides an easier method ofcompilation. It requires only a single synthesis action for the wholedesign, and allows you to go directly into functional simulation aftersynthesis. The top-down approach is used for any single-file VHDLdesign.

Bottom-up MethodologyBottom-up can be beneficial if you have a very large design, and youdo not want to have to recompile the entire design when just a singlemodule has changed. In this case, you only have to recompile themodified module, provided that the changes do not affect the ports.

Design Flow — Top-down1. Be sure that all VHDL files are added to the project. See the

“Adding the File to the Project” section for instructions onadding files to a project.

2. Open up the top-level VHDL file in the HDL Editor. This can bedone by the methods listed in the “VHDL File Selection” sectionor by double clicking on the .VHD file in the Project Manager.

3. Select Synthesis → Options . Be sure that the Compile switchis set to Chip. Click on the Advanced tab.

4. Select the top-level entity and architecture, and click OK.



5. To synthesize the design, choose Synthesis → Synthesize .This synthesizes the complete design and produces one .EDN filefor the project.

For details on conducting a functional simulation, refer to the“VHDL Top-down Methodology” section of the “FunctionalSimulation” chapter.

Design Flow — Bottom-upNote: For the bottom-up flow, each lower-level VHDL file must havethe same name as its entity within that file.

1. Add just the top-level VHDL file to the project. See the “Addingthe File to the Project” section for instructions on adding files to aproject.

2. Open up the top-level VHDL file in the HDL Editor. This can bedone by the methods listed in the “VHDL File Selection” sectionor by double clicking on the .VHD file in the Project Manager.

3. Select Synthesis → Options . Verify that the Compile switch isset to Chip. Click on the Advanced tab. Select the top-level entityand architecture, and click OK.

4. To synthesize the design, choose Synthesis → Synthesize .This synthesizes just the top-level VHDL file.

5. From within the HDL Editor, select File → Open. Open one ofthe lower-level VHDL files. Select Synthesis → Options . Besure that the Compile switch is set to Macro. Select Synthesis→ Synthesize .

6. Repeat step 5 for each lower-level VHDL module.

For details on conducting a functional simulation, refer to the“VHDL Bottom-up Methodology or Underlying Netlists” sectionof the “Functional Simulation” chapter.



Managing Large DesignsThe following subsections explain how to manage large designs.

Improved Design OptimizationFoundation allows you to control optimization of the design on amodule-by-module basis. This means that you have the ability to, forinstance, optimize certain modules of your design for speed, some forarea, some for a balance of both, and some could have nooptimization at all.

With Foundation, the optimization of the synthesized HDL designhas been improved and is now incorporated into the mappingfunction in the implementation phase of the flow. The switches forthe optimization are planted in the VHDL synthesis phase of the flow,but the actual optimization happens later in the mapping phase of theimplementation.

Note: It is highly recommended that individual VHDL module sizebe limited to 4000 gates or less. The main reason for this limitation isto reduce the runtime of both the XVHDL compiler and of the MAPprogram, later in the implementation flow, as well as to create morereadable and modular designs.

Optimization SwitchThere are two ways to “plant” the optimization switch in the HDLsynthesis phase of the flow: 1) using the HDL Editor SynthesisOptions GUI or 2) placing an attribute in the VHDL code. The choicesfor Optimization are Speed, Area, Balance, or Off.

These switches do not control the VHDL synthesizer. They are merelya way to plant the optimization switch into the netlist by the MAPprogram to use. The advantage of putting the OPTIMIZE constraint(attribute) on each module is that you can now perform module-by-module optimization in MAP. To reiterate, you will not see anydifference in runtime or quality of results from the VHDL synthesizerby changing these options. These options will only affect MAP laterin the flow.



Optimization TipsEven if you want your entire design optimized for Speed, or for Area,or for Balance, you should still set the switch on each individualmodule.

Runtimes can become quite long when MAP attempts to optimizelarge designs. By setting the Optimize switch on each module of thedesign, MAP optimizes each smaller module separately, andconsequently, runtimes decrease dramatically.

Note: After having set these optimization switches as described inthe preceding paragraph (in order to allow the MAP program to usethese settings on a module-by-module basis), you must be sure thatthe Optimization Strategy is disabled in the Design ManagerImplementation Template, which is the default. If anything otherthan OFF is selected, that value overrides all of the module-basedoptimization settings, and the design will be optimized in one largechunk rather than on a per-module basis. The result can be a lengthyruntime.

Setting the Optimization Strategy with Top-downMethodology

Optimization strategy for the top-level module can be set through theHDL Editor menus.

1. Select Synthesis → Options , and choose Balance, Area,Speed, or Off, as shown in the following figure.



Figure 5-3 XVHDL Compile and Optimization Options

2. In order to set the Optimization strategy for the lower-levelmodules in the design, the following attribute must be placed inthe entity declaration within the VHDL code:

attribute optimize: string;attribute optimize of Entity_Name : entity

is “ Opt_Strategy ”;

where entity_name is the name of the entity for the given module,and opt_strategy is one of the following:

SpeedAreaBalanceOff

Setting the Optimization Strategy with Bottom-upMethodology

Optimization strategy for both the top-level and lower-level modulescan be set using either the HDL Editor menus, or by putting theattribute in the VHDL code as described previously in the “Settingthe Optimization Strategy with Top-down Methodology” section.



The optimize attribute in the VHDL code always overrides any menuselection you make with the HDL Editor GUI. Therefore, if youintend to use the GUI option selection to choose the optimizationstrategy, be sure that the Optimize attribute is not present in theVHDL code.

Advanced Design TechniquesThe following subsections describe advanced design techniques.

Partitioning GuidelinesThe way in which a design is partitioned can affect how well theoptimizer can optimize the combinatorial logic. If a design is poorlypartitioned in the entry phase, logic optimization can suffer. Here aresome VHDL coding and partitioning guidelines that will helpimprove logic optimization.

• Avoid imposing boundaries on combinatorial paths.

If parts of a combinatorial logic path are compiled in separatemodules, no logic optimization can be performed across theblock boundaries.

Instead, partition the design so that combinatorial paths are notsplit across multiple modules. This gives the software the bestopportunity to optimize combinatorial logic on the path.

Figure 5-4 Combinatorial Logic Path Split Across Boundaries(Inefficient Use of Design Resources)

COMB.LOGIC

C

COMB.LOGIC

B

COMB.LOGIC

A REGC

REGA

A B C

X8145



Figure 5-5 Combinatorial Logic Path Grouped Into One Block(Efficient use of Design Resources)

• Register all block outputs.

Partition the design into modules in such a way that all blockoutputs are registered. This guarantees that no boundaries arebeing imposed on any combinatorial paths, as discussedpreviously.

LogiBLOXLogiBLOX are high-level customizable modules such as counters,adders, and RAM which have been pre-optimized. Because they arepre-optimized, LogiBLOX modules take advantage of the specialarchitectural features of the Xilinx device architectures, such as thefast carry logic circuitry or the on-chip RAM. When these types offunctions are behaviorally described in the VHDL code, FoundationXVHDL infers LogiBLOX components whenever possible. In theHDL Editor’s Synthesis Options Dialog Box, you can disableLogiBLOX inference if you wish by deselecting the LogiBLOX option.By default, LogiBLOX inference is enabled.

Additionally, LogiBLOX modules can be created using thecustomizable LogiBLOX GUI from the Foundation Project Manager,and then these modules may be instantiated in the VHDL code.

When attempting to use RAM or ROM, LogiBLOX instantiation isrecommended. Do not attempt to describe RAM behaviorally, ascombinatorial latches will be inferred. For more information oninstantiating LogiBLOX, refer to the “LogiBLOX” chapter.

COMB.LOGIC

A, B, & C REGC

REGA

A C

X8146



Tristate BusesWhen creating tristate buses, it is preferable to try to keep all driversof the bus within the same entity to avoid errors related to havingmultiple drivers for the given net. If you prefer to keep the drivers inseparate entities, then the design must be compiled with the bottom-up methodology, as described in the “Design Flow — Bottom-up”section.

User LibrariesIn the Foundation XVHDL environment, a user library is a VHDL filewhich is referenced by another file through a LIBRARY statement. Auser library can contain packages and/or entities.

User libraries can be located in either the current project directory orin the active\vhdl\vhdl_lib directory, where active is the directorywhere the Foundation tools have been installed (default isc:\fndtn\active).

User libraries are declared and used just like system libraries such asIEEE. For example, to access the entities defined in the librarymylib.vhd, use the following syntax:

library MYLIBuse MYLIB.all;

Normally, when a library has been included in a VHDL file, XVHDLlooks for a single file with the same name as the library.

In the example above, the compiler looks for a file called mylib.vhdcreated when the design was synthesized.

A library alias allows a library name to be mapped to one or moreVHDL files that may have different names. To create a library alias,create an empty VHDL file in the active\vhdl\vhdl_lib directory.From the HDL Editor, choose Synthesis → Options and select theLibrary Alias tab. Here you can assign various VHDL files to youruser-created alias.




Chapter 6


This chapter explains the basic operations for creating state machinedesigns.

State machine design typically starts with the translation of a conceptinto a “paper design,” usually in the form of a state diagram or abubble diagram. The paper design is converted to a state table and,finally, into the source code itself. To illustrate the process ofdeveloping state machines, this chapter discusses an example inwhich a state machine repetitively sequences through the fivenumbers 9, 5, 1, 2, and 4.


• “State Machine Example” section

• “State Diagram” section

• “State Machine Implementation” section

• “Encoding Techniques” section

Refer to the “State Machine Designs” section of the “DesignMethodologies” chapter for a detailed procedure on creating a statemachine design. For an example of how to create a state machine, seethe “Using the State Editor (Optional)” section in the FoundationSeries Quick Start Guide 1.4.

For additional information, select Help → Foundation HelpContents . Click State Editor under Tools or The State Editor underTutorials.

For information on creating state machine macros, refer to the“Schematic Designs With State Machine Macros” section of the“Design Methodologies” chapter and to the “VHDL Designs withState Machine Macros” section of the “Design Methodologies”chapter.



State Machine ExampleThe state machine in this example has four modes, which can beselected by two inputs: DIR (direction) and SEQ (sequence). DIRreverses the sequence direction; SEQ alters the sequence by swappingthe position of two of the numbers in the sequence. When themachine is turned on, it starts in the initial state and displays thenumber 9. It then sequences to the next number shown, dependingon the input. This sequence is summarized in the following table.

Conceptual descriptions show the state progression and controllingmodes, but they do not clearly show how change conditions result.

State DiagramThe state diagram is a pictorial description of state relationships. The“State Diagram” figure gives an example. Even though a statediagram provides no extra information, it is generally easier totranslate this type of diagram into a state table. Each circle containsthe name of the state, while arrows to and from the circles show thetransitions between states and the input conditions that cause statetransitions. These conditions are written next to each arrow.

Table 6-1 State Relationships

SEQ DIR Sequence of Displayed Number

1 1 9 → 5 → 1 → 2 → 4 → 9 . . .

1 0 9 → 4 → 2 → 1 → 5 → 9 . . .

0 1 9 → 5 → 2 → 1 → 4 → 9 . . .

0 0 9 → 4 → 1 → 2 → 5 → 9 . . .



Figure 6-1 State Diagram

State Machine ImplementationA state machine requires memory and the ability to make decisions.The actual hardware used to implement a state machine consists ofstate registers (flip-flops) and combinatorial logic (gates). Stateregisters store the current state until the next state is calculated, and alogic network performs functions that calculate the next state on thebasis of the present state and the state machine inputs. The followingfigure shows the logic transitioning through the state registers to theoutput decoder logic.

S9

S5

S4 S2

S4

Display = 9

Display = 4

Display = 2Display = 1

Display = 5

dir = 0

dir = 1 dir = 1

dir = 0

seq = 1 &dir = 1

seq = 1 &dir = 0

seq = 1 & dir = 0 orseq = 0 & dir = 1

seq = 1 &dir = 1

seq = 1 &dir = 0

seq = 0 & dir = 1seq = 0 & dir = 0

seq = 0 & dir =0

seq = 0 & dir =0

seq = 0 & dir = 1

orseq 1 & dir =1

X2025



Figure 6-2 Parts of a State Machine

The amount of logic used to calculate the next state varies accordingto the type of state machine you are implementing. You must choosethe most efficient design approach, depending on the hardware inwhich the design will be implemented.

Encoding TechniquesThe states in a state machine are represented by setting certain valuesin the set of state registers. This process is called state assignment orstate encoding.

There are many ways to arrange, or encode, state machines. Forexample, for a state machine of five states, you can use three flip-flopsset to values for states 000, 001, 010, 011, 100, which results in a highlyencoded state machine implementation. You can also use five flip-flops set to values 00001, 00010, 00100, 01000, 10000, that is, one flip-flop per state, which results in a one-hot-encoded state machineimplementation. State encoding has a substantial influence on thesize and performance of the final state machine implementation.

Symbolic and Encoded State MachinesA symbolic state machine makes no reference to the actual valuesstored in the state register for the different states in the state table.Therefore, the software determines what these values should be; itcan implement the most efficient scheme for the architecture beingtargeted or for the size of the machine being produced.

Feedback

Outputs

State RegistersLogic Gates

Logic Gates

Outputs

Inputs

X4635



All that is defined in a symbolic state machine is the relationshipamong the states in terms of how input signals affect transitionsbetween them, the values of the outputs during each state, and insome cases, the initial state.

An encoded state machine requires the same definition informationas a symbolic machine, but in addition, it requires you to define thevalue of the state register for each state.

Symbolic state machines are supported for CPLDs, but they are lessefficient than encoded state machines.

Compromises in State Machine EncodingA good state machine design must optimize the amount ofcombinatorial logic, the fanin to each register, the number of registers,and the propagation delay between registers. However, these factorsare interrelated, and compromises between them may be necessary.For example, to increase speed, levels of logic must be reduced.However, fewer levels of logic result in wider combinatorial logic,creating a higher fanin than can be efficiently implemented given thelimited number of fanins imposed by the FPGA architecture.

As another example, you must factor out the logic to decrease thegate count; that is, you must extract and implement shared termsusing separate logic. Factoring reduces the amount of logic butincreases the levels of logic between registers, which slows down thecircuit. In general, the performance of a highly encoded state machineimplemented in an FPGA device drops as the number of states growsbecause of the wider and deeper decoding that is required for eachadditional state. CPLDs are less sensitive to this problem becausethey allow a higher fanin.

Binary EncodingUsing the minimum number of registers to encode the machine iscalled binary, or maximal, encoding, because the registers are used totheir maximum capacity. Each register represents one bit of a binarynumber. The example discussed earlier in this chapter has five states,which can be represented by three bits in a binary-encoded statemachine.



Although binary encoding keeps the number of registers to aminimum, it generally increases the amount of combinatorial logicbecause more combinatorial logic is required to decode each state.Given this compromise, binary encoding works well whenimplemented in Xilinx CPLD devices, where gates are wide andregisters are few.

One-hot EncodingIn one-hot encoding, an individual state register is dedicated to onestate. Only one flip-flop is active, or hot, at any one time. There aretwo ways that one-hot encoding can significantly reduce the amountof combinatorial logic used to implement a state machine.As noted in the “Compromises in State Machine Encoding” section,highly encoded designs tend to require many high fanin logicfunctions to interpret the inputs. One-hot encoding simplifies thisinterpretation process because each state has its own register, or flip-flop. As a result, the state machine is already “decoded,” so the stateof the machine is determined simply by finding out which flip-flop isactive. One-hot encoding reduces the width of the combinatorial logicand, as a result, the state machine requires fewer levels of logicbetween registers, reducing its complexity and increasing its speed.

Although one-hot encoding can be used for CPLDs and FPGAs, it isbetter suited to FPGAs.

One-Hot Encoding in Xilinx FPGA Architecture

One-hot encoding is well-suited to Xilinx FPGAs because the Xilinxarchitecture is rich in registers, while each configurable logic block(CLB) has a limited number of inputs. As a result, state machinedesigns that require few registers, many combinatorial elements, andlarge fanin do not take full advantage of these resources. In general, aone-hot state machine implemented in a Xilinx FPGA minimizes boththe number of CLBs and the levels of logic used.

Limitations

In some cases, the one-hot method may not be the best encodingtechnique for a state machine implemented in a Xilinx device. Forexample, if the number of states is small, the speed advantages ofusing the minimum amount of combinatorial logic may be offset bydelays resulting from inefficient CLB use.



Encoding for CPLDsCPLD devices generally implement binary-encoded state machinesmore efficiently. Binary encoding uses the minimum number ofregisters. Each state is represented by a binary number stored in theregisters. Using as few registers as possible usually increases theamount of combinatorial logic needed to interpret each state.

CPLD devices have wide gates and a large amount of combinatoriallogic per register, so it is best to start with binary encoding. If thecomplexity of the state machine logic is such that binary encodingexhausts all product term resources of a CPLD, try a slightly less fullyencoded state machine.

The syntax used to specify one-hot encoded state machines forFPGAs is also supported for CPLD designs.




Chapter 7

LogiBLOX

LogiBLOX is an on-screen design tool for creating high-level modulessuch as counters, shift registers, and multiplexers for FPGA designs.LogiBLOX includes both a library of generic modules and a set oftools for customizing these modules.

With LogiBLOX, high-level LogiBLOX modules that will fit into yourschematic-based design or HDL synthesis-based design can becreated and processed. For information about instantiatingLogiBLOX into designs, refer to the “Schematic Designs WithInstantiated LogiBLOX Modules” section and the “VHDL Designswith Instantiated LogiBLOX Modules” section of the “DesignMethodologies” chapter.


• “Setting Up LogiBLOX on a PC” section

• “Starting LogiBLOX” section

• “Creating LogiBLOX Modules” section

• “LogiBLOX Modules” section

• “Using LogiBLOX for Schematic Designs” section

• “Using LogiBLOX for HDL Designs” section

• “Documentation” section

Note: The Xilinx products that support LogiBLOX are XC3000A/L,XC3100A/L, XC4000E/L/EX/XL/XV, XCS and XC5200.



Setting Up LogiBLOX on a PCLogiBLOX will be automatically installed with the Xilinx designimplementation tools and will be ready to use from the FoundationProject Manager interface when you start the product.

Starting LogiBLOXLogiBLOX can be started when you make the Tools → LogiBLOXmenu selection in the Project Manager. LogiBLOX can also be startedwithin the Schematic Editor by selecting Options → LogiBLOX or inthe HDL Editor by selecting Synthesis → LogiBLOX . The Logi-BLOX Module Selector dialog box then opens.

LogiBLOX components may be used in both schematics and VHDLdesigns for FPGAs. Once you are in the LogiBLOX GUI, you cancustomize standard modules and process them for insertion into yourdesign.

Note: Once a LogiBLOX module is created, do not changeparameters for the module on the schematic. Any changes to themodule parameters must be made through the LogiBLOX GUI and anew module created.

You can also import an existing LogiBLOX module from anotherdirectory or project into the current project library by selectingTools → Import LogiBLOX from the Project Manager and choosingthe .MOD file of the module to be imported. For details, see the“Importing Existing LogiBLOX Modules” section of the “DesignMethodologies” chapter.

Creating LogiBLOX ModulesOnce you have opened LogiBLOX, create a module as follows:

1. Enter the name of the module you want to create in the ModuleName field or select an existing one from the list box.

2. Select the type of module from the Module Type list box.

3. Select the bus width for the module from the Bus width list box.

4. Select or deselect optional pins of the module symbol displayedin the Details box by clicking the appropriate check boxes.

LogiBLOX


5. Click OK. LogiBLOX creates two files for each module: the MODfile, which contains symbol pins and a template for each moduleand the EDN file with the EDIF netlist.

The Project Manager automatically converts the EDIF netlist, readsthe generic module file from the\FNDTN\ACTIVE\CONFIG\LOGIBLOX directory and the MODfile to customize the module symbol. The Project Manager thengenerates the ALR and ASX files containing the module’s binarynetlist and ports description and saves the module to the projectworking library. The module is then ready to use in your project.

LogiBLOX ModulesLogiBLOX has many different modules that you can use in aschematic or HDL synthesis design. The following is a list of theLogiBLOX modules.

Using LogiBLOX for Schematic DesignsLogiBLOX modules can be created to use in schematic designs. First,the module must be created. The module can then be added to theschematic like any other library component. For details on theprocedure, refer to the “Schematic Designs With InstantiatedLogiBLOX Modules” section of the “Design Methodologies” chapter.

Accumulator Adder/Subtracter Clock Divider

Comparator Constant Counter

Data Register Decoder Input/Output(schematic only)

Memory Multiplexer Pad (schematic only)

Shift Register Simple Gates Tristate Buffers



Using LogiBLOX for HDL DesignsThe tools for synthesis-based designs are described in the followingsubsections.

Module-inferring ToolsFoundation VHDL infers LogiBLOX components where appropriate.Use the HDL Editor to create the VHDL file; the Design Wizard canhelp you with this process.

In the HDL Editor’s Synthesis Options Dialog Box, you can disableLogiBLOX inference if you wish by deselecting the LogiBLOX option.By default, LogiBLOX inference is enabled.

Module-instantiation ToolsYou can instantiate the LogiBLOX components in your HDL code totake advantage of their high-level functionality. Define eachLogiBLOX module in HDL code with a component declaration,which describes the module type, and a component instantiation,which describes how the module is connected to the other designelements. For more information, refer to the “VHDL Designs withInstantiated LogiBLOX Modules” section of the “DesignMethodologies” chapter.

DocumentationThe following documentation is available for the LogiBLOX program:

• The LogiBLOX Reference/User Guide is available on the CD-ROMsupplied with your software and viewable with a DynaTextbrowser.

• The LogiBLOX online help can be accessed from LogiBLOX orfrom the Foundation online help system.

• The Xilinx Software Conversion Guide from XACTstep v5.X.X toXACTstep vM1.X.X compares XBLOX and LogiBLOX, and how toconvert an XBLOX design to LogiBLOX. This document isavailable on the Xilinx web site at http://www.xilinx.com/techdocs/htm_index/docs_M1.htm.


Chapter 8


For schematic and HDL designs, the functional simulation netlists arecreated in the Foundation design entry tools environment. Yourdesign methodology determines when you perform functionalsimulation. Generally, you can perform functional simulation directlyafter you have completed your design within the design entry tools.However, if you have created your design using the bottom-uphierarchical HDL methodology or your design contains underlyingnetlists (XNF or EDIF), the design must first be “translated” in theXilinx Design Manager in order to merge these additional netlists.


• “Basic Functional Simulation Process” section

• “VHDL Top-down Methodology” section

• “VHDL Bottom-up Methodology or Underlying Netlists”section

• “Simulation Macro Editor” section

• “Waveform Editing Functions” section

Basic Functional Simulation ProcessThis section describes the basic process for performing simulation.

Invoking the SimulatorThe simulator may be invoked from either the Project Manager ordirectly from the Schematic Editor. To invoke the simulator (forfunctional simulation) from the Project Manager, click on the SIMFunct button.



Note: For a schematic design, you can invoke the simulator (forfunctional simulation) from the Schematic Editor by clicking on theSimulator toolbar button.

Attaching Probes (Schematic Editor Only)Prior to opening up the Simulator, probes may be attached to signalsin the Schematic Editor to allow those signals to be automaticallyloaded into the Simulator Waveform Viewer. Select Mode → TestPoints. The SC probes toolbox displays. You can select both inputand output test points.

Figure 8-1 Input Test Points

Figure 8-2 Output Test Points

A gray box appears next to the signal name, indicating the placementof the probe. Probes may be added at any point during the simulationto add signals to the Waveform Viewer.

Adding SignalsOnce in the Simulator, signals may be added by selecting the AddSignals toolbar button.



Creating BusesBuses may be created by combining any set of signals by highlightingthe desired signals and then selecting Signal → Bus → Combine .This same menu may be obtained by right-mouse-clicking in thesignal list area of the Waveform Viewer. To expand or collapse thebus, click on the Bus Expansion toolbar button.

Applying StimulusStimulus may be applied in a number of various ways.

By selecting the Stimulator Selection toolbar button, you may addstimulus using keyboard keys, formulas, or output signals of aninternal software-generated 16 bit binary counter. For moreinformation regarding how to apply stimulus using these methods,refer to the online help by clicking on the Help button in theStimulator Selection window.

Figure 8-3 Stimulator Selection Dialog Box



A second method of applying stimulus is by editing and using wave-form test vectors. Test vectors may be edited and/or created usingthe Waveform → Edit... menu selection. Additionally, test vectorsand/or simulation results may be saved by selecting File → SaveWaveform . These test vector waveforms may then be loaded into thesimulator at any time by selecting File → Load Waveform .

For more information on using and saving waveforms, refer to theonline Help at Help → Logic Simulator Help Contents →Simulator Reference → Working with Waveforms .

A third method of applying stimulus is through a script file macro.Stimulus is entered through commands in the script file (.CMD) andthe simulator displays the input and output response in theWaveform Viewer when the script is run.

Note: Foundation 1.4 contains a new Macro Editor for creating simu-lation scripts. See the “Simulation Macro Editor” section.

Proper script syntax is documented in the online Help at Help →Logic Simulator Help Contents → Simulator Reference →Simulation Scripts . To run a command script, select File →Run Script , and choose the appropriate .CMD file. Additionally,the .CMD file may be edited by selecting Tools → Script File →Edit .

Running SimulationTo step through the simulation, click on the Short step button in thetoolbar for a short step or the Long step button for a long step.

Figure 8-4 Short Step

Figure 8-5 Long Step

The length of these steps may be modified by selecting Options →Simulation Step . To start a simulation for an extended amount oftime, select Options → Start Long Simulation . In the dialogbox, input the desired length of simulation.



Figure 8-6 Start Long Simulation Window

To interrupt the simulation while it is running, click the Stop buttonin the toolbar.

Simulator results may be saved by selecting File → SaveSimulation and File → Save Waveforms . Choosing SaveSimulation saves the simulation results and current state of thesimulation only. On the other hand, Save Waveforms saves thewaveforms in test vector format, allowing you to resimulate thesaved waveforms at a later time.

For more information about simulator options and features, refer tothe online Help by selecting Help → Logic Simulator HelpContents .

VHDL Top-down MethodologyIf your design has been created and synthesized as a top-level design(see the “Design Flow — Top-down” section of the “HDL DesignEntry and Synthesis” chapter), then click on the SIM Funct button inthe Foundation Project Manager to automatically invoke thesimulator and load the netlist. The SIM Funct button is shown in thefollowing figure.

For a description of how to select signals, choose stimulators, and runthe simulation, refer to the online help tutorial by selecting Help →Foundation Help Contents . Then click on Logic Simulator.Double click on the Getting Started Tutorial.



VHDL Bottom-up Methodology or UnderlyingNetlists

If you have created a VHDL bottom-up design, synthesize the designas described in the “Bottom-up Methodology” section of the “HDLDesign Entry and Synthesis” chapter. If your design includesunderlying netlists (XNF or EDIF), the design must also first be“translated” in the Xilinx Design Manager in order to merge theseadditional netlists. Now follow the steps below to successfullycombine all of the individual modules into one netlist for simulationby “translating” the design in the Xilinx Design Manager.

1. Click on the Implement M1 button in the Foundation ProjectManager to invoke the Design Manager.

2. Select Design → New Version , and then Design → NewRevision .

3. With the new revision highlighted, go into the Flow Engine byclicking on the Flow Engine toolbar icon.

4. From within the Flow Engine, select the Step button to translatethe design.

5. After Translate is complete, go back to the Foundation ProjectManager, and select Tools → Checkpoint Simulation .

6. Choose the appropriate NGD file from the Revision which wasjust created, and click OK. This invokes the simulator and loadsthe netlist.

For a description of how to select signals, choose stimulators, andrun the simulation, refer to Steps 2 through 10 in the “PerformingFunctional Simulation” section of the “Design Methodologies”chapter.

Detailed information can also be found in the online help tutorialby selecting Help → Foundation Help Contents . Then clickon Logic Simulator. Double click on the Getting Started Tutorial.Another very detailed source can be found by selecting Help →Foundation Help Contents .



7. Click CPLD Design Flows. Scroll down and click The FunctionalSimulation Tutorial. You can also click Creating a New TestVector File to find out detailed information about creatingstimuli.

Simulation Macro EditorA new feature of Foundation 1.4, the Simulation Macro Editor,facilitates script creation. From the Logic Simulator, select Tools →Script Editor to access this editor. Some of the features of this neweditor include the following:

• Syntax highlighting of simulation commands

• Simulation scripts in Macro Assistant (Tools → MacroAssistant ). The Macro Assistant contains examples ofViewsim-compatible macros as well as Viewlogic® -compatibleand Aldec® proprietary macros.

• Script command reference (Help → SIM Macros Help )

• Debugging capabilities

• An online link to the simulator which allows single steppingthrough command sequences and support for breakpoints

For a description of the Macro Editor and commands, select Help →SIM Macros Help .

Waveform Editing FunctionsFoundation 1.4 supports dragging of signal transitions within theWaveform Editor. Following is an example.

1. Open the “lock” project in the Project Manager.

2. Click the Sim Funct button.

3. In the Logic Simulator, select File → Load Waveform .

4. Double click “function.tve” in the Load Waveform list box.

5. Right click the mouse button. Select Edit from the menu.



6. After the Test Vector State Selection box displays, press and holdthe left mouse button at the point of the signal that you want tobegin altering the signal transition. Drag the mouse to the desiredendpoint. The following figure displays an example selection forthe Start signal.

Figure 8-7 Selecting a Signal Transition

7. Select High from the Test Vector State Selection box. The lowsignal transforms to high.


Chapter 9

An Introduction to Design Implementation


• “Starting the Xilinx Design Manager” section

• “Implementing a Design” section

• “Selecting Options” section

• “Post Implementation Static Timing Analysis” section

• “Summary Timing Reports” section

The Xilinx Design Manager is the graphical interface that managesthe implementation versions and revisions created during the designprocess. Results of these implementations are made available inreports and may be accessed through the Design Manager’s ReportBrowser.

The Design Manager also provides on-screen push-button access tothe other Xilinx tools, such as the Flow Engine, Timing Analyzer,PROM File Formatter, EPIC Report Browser, and various navigationand information tools. For detailed information about designimplementation, consult the Design Manager/Flow Engine Reference/User Guide and the Development System Reference Guide.

Starting the Xilinx Design ManagerTo start the Xilinx design implementation tools, click on theImplement M1 button in the Project Flowchart area of the ProjectManager.



The Foundation Design Manager window is shown in the followingfigure.

Figure 9-1 Foundation Design Manager Window

Implementing a Design1. From the Design Manager menu (refer to the previous figure),

select Design → Implement .

Figure 9-2 Design Manager Menus and Toolbar

2. In the Implement dialog box, select Options.



3. Choose any desired implementation option. If you are planningon conducting a timing simulation, select the Produce TimingSimulation Data option.

4. Click OK.

5. In the Implement dialog box, select the part and click on Run.The Design Manager automatically creates a new version andrevision. Additional versions are created when the netlist ismodified and re-implemented. Also, additional revisions arecreated when the same netlist is re-implemented with newoptions or constraints.

The Design Manager invokes the Flow Engine to process thedesign. The Flow Engine interface prominently displays thestatus of each phase of the design.

Figure 9-3 Flow Engine Shows All Design SegmentsCompleted (FPGAs)

Figure 9-4 Flow Engine Shows All Design SegmentsCompleted (CPLDs)



When you process your design, the Flow Engine translates the designfile into the Xilinx internal database format (NGD). The Flow Enginethen implements your design and generates bitstream data.

Process indicators in the Flow Engine main window show you whichof these stages is currently processing. The arrows between each stepturn black after the previous step is completed. Underneath eachprocess indicator, a progress bar shows the status of each processingstep, whether running, completed, aborted, or failed. You can controleach step in the processing of your design by using the processcontrol buttons at the bottom of the Flow Engine main window.

For more information about the Design Manager, refer to the“Introduction” chapter of the online document Design Manager/FlowEngine Reference/User Guide.

MAPThe MAP program maps a logical design to a Xilinx FPGA. The inputto a mapping program is an NGD file, which contains a logicaldescription of the design in terms of both the hierarchicalcomponents used to develop the design and the lower level Xilinxprimitives, and any number of NMC (macro library) files, each ofwhich contains the definition of a physical macro. MAP first performsa logical DRC (Design Rule Check) on the design in the NGD file.MAP then maps the logic to the components (logic cells, I/O cells,and other components) in the target Xilinx FPGA. The output designis an NCD (Native Circuit Description) file physically representingthe design mapped to the components in the Xilinx FPGA. The NCDfile can then be placed and routed.

The Mapper can be run from a GUI or command line. For adescription of the GUI, see the DynaText online document, DesignManager/Flow Engine Reference/User Guide. For a description of theMAP command and its options, see the DynaText online document,Development System Reference Guide.



Place and Route (PAR)After an FPGA design has undergone the necessary translation tobring it into the NCD (Circuit Description) format, it is ready forplacement and routing. This phase is done by PAR (Xilinx's Place andRoute program). PAR takes an NCD file, places and routes the design,and outputs an NCD file which is used by the bitstream generator(BitGen). The output NCD file can also act as a guide file when yourepeat placement and routing for a design to which minor changeshave been made after the previous place and route.

In the Xilinx Development System, PAR places and routes a designusing a combination of two methods:

• Cost-based — This means that placement and routing areperformed using various cost tables which assign weightedvalues to relevant factors such as constraints, length ofconnection and available routing resources.

• Timing-Driven — PAR places and routes a design based uponyour timing constraints.

For a complete description of PAR, see the “PAR—Place and Route”chapter in the Development System Reference Guide.

For a discussion of PAR improvements for Foundation 1.4, refer tothe “Place and Route Improvements” section of the Foundation SeriesQuick Start Guide 1.4.

BitGen (Configure)The BitGen program produces a bitstream for Xilinx FPGA deviceconfiguration. After the design has been completely routed, it isnecessary to configure the device so that it can execute the desiredfunction. This is done with BitGen, Xilinx's bitstream generationprogram. BitGen takes a fully routed NCD (Circuit Description) fileas its input and produces a configuration bitstream—a binary filewith a .bit extension. The BIT file contains all of the configurationinformation from the NCD file defining the internal logic andinterconnections of the FPGA, plus device-specific information fromother files associated with the target device. The binary data in theBIT file can then be downloaded into the FPGA's memory cells, or itcan be used to create a PROM file.



For a complete description of BitGen, see the “BitGen” chapter in theDevelopment System Reference Guide. This chapter also explains how touse the command line to run BitGen.

Within the Flow Engine, BitGen runs as part of the Configure process.For details consult the various configuration template options in the“Implementation Options” chapter of the Design Manager/Flow EngineReference/User Guide.

CPLD FitterThe CPLD Fitter implements designs for the XC9500 devices. TheFitter outputs several files:

• The Fitting report (design_name.rpt) lists summary and detailedinformation about the logic and I/O pin resources used by thedesign, including the pinout, error and warning messages, andBoolean equations representing the implemented logic.

• The Static timing report (design_name.tim) shows a summaryreport of worst-case timing for all paths in the design; itoptionally includes a complete listing of all delays on eachindividual path in the design.

• The Guide file (design_name.gyd) contains all resulting pinoutinformation required to reproduce the current pinout if the"pinfreeze" option is specified during the next invocation of theCPLD command for the same design name. (The Guide file iswritten only upon successful completion of the fitter.)

• The Programming file (design_name.jed for XC9000) is a JEDEC-formatted (9k) programming file to be downloaded into theCPLD device.

• Timing simulation database (design_name.nga) is a binarydatabase representing the implemented logic of the design,including all delays, consisting of Xilinx simulation modelprimitives (simprims).

For detailed information about implementing CPLD designs, refer tothe DynaText online documents, CPLD Schematic Design Guide andthe CPLD Synthesis Design Guide.



EPICThe Editor for Programmable Integrated Circuits (EPIC) is agraphical application for displaying and configuring FPGAs. You canuse EPIC to place and route critical components before running theautomatic place and route tools on your designs. You can also useEPIC to manually finish placement and routing if the routingprogram does not completely route your design. In addition, EPICreads from and writes to the Physical Constraints File (PCF).

For a description of EPIC, see the DynaText online manual, EPICDesign Editor Reference/User Guide.

Selecting OptionsOptions specify how a design is optimized, mapped, placed, routed,and configured. Options are grouped into objects calledimplementation templates and configuration templates. Eachtemplate defines an implementation or configuration approach. Forexample, one implementation style could be Quick Evaluation, whileanother could be Timing Constraint Driven.



Figure 9-5 Flow Engine Options Dialog Box

You can have multiple templates in a project. By choosing a template,you are choosing an implementation or configuration style. To accessthe options and templates:

1. Select the Options button in the Implement dialog or from theFlow Engine menu select Setup → Options .

2. In the Program Option Templates portion of the Options Dialog,select the Edit Template button for Implementation orConfiguration to access the associated template.

3. From the Design Manager menu, select Utilities →Template Manager .



The default options settings are able to accommodate most imple-mentations. For information on the options, select Help →Contents from the Design Manager menu.

Post Implementation Static Timing AnalysisPost-implementation timing reports incorporate all delays to providea comprehensive timing summary. If an implemented design has metall of your timing constraints, then you can proceed by creatingconfiguration data and downloading a device. On the other hand, ifyou identify problems in the timing reports, you can try fixing theproblems by increasing the placer effort level, using re-entrantrouting, or using multi-pass place and route. You can also redesignthe logic paths to use fewer levels of logic, tag the paths forspecialized routing resources, move to a faster device, or allocatemore time for the paths.

Summary Timing ReportsSummary reports show timing constraint performance and clockperformance. Implementing a design in the Flow Engine canautomatically generate summary timing reports. To create summarytiming reports, perform the following steps.

1. Open the Options dialog. For a post-map report select theProduce Logic Level Timing Report button. For a post-PARreport, select the Produce Post Layout Timing Report button.

2. To modify the reports to highlight path delays or paths that havefailed timing constraints, perform the following:

a) Edit the template implementation.

b) Select the timing tab.

c) Select a report format.

3. Once MAP or PAR has completed, the respective timing reportsappear in the Report Browser.




Chapter 10

Post-implementation Timing Simulation

The procedures for functional and timing simulation are nearlyidentical. Like functional simulation, you must use test vectors to runthe simulation. To create test vectors, refer to the “PerformingFunctional Simulation” section of the “Design Methodologies”chapter.


• “Generating a Timing-annotated Netlist” section

• “Creating Timing Test Vectors” section

• “Basic Timing Simulation Process” section

Generating a Timing-annotated NetlistBefore performing a timing simulation on your design, you mustgenerate a timing-annotated netlist. To generate this netlist, you needto select the Produce Timing Simulation Data option from theImplementation Options dialog box.

1. Within the Design Manager, select Design → Implement .

2. From the Implement dialog box, select the Options button.

3. In the Options dialog box, select Produce Timing SimulationData.

Creating Timing Test VectorsBefore performing timing simulation, you must also create timingtest vectors. Refer to the “Performing Functional Simulation” sectionof the “Design Methodologies” chapter for details.



Basic Timing Simulation ProcessThis section describes the basic step to perform a timing simulation.

1. Open the Timing Simulator by clicking the SIM Timing button.


Figure 10-1 Logic Simulator and Waveform Viewer

2. Load the timing test vectors by selecting File → LoadWaveform .

3. Select the timing test vector file that you have created. The testvectors will display in the Waveform Viewer.

4. Use the controls from the Simulator window to verify yourdesign.

You can find timing simulation online help for CPLDs byselecting Help → Foundation Help Contents . Click CPLDDesign Flows under the Tutorial heading. Scroll down the DesignFlow Tutorial window and click The Timing Simulation Tutorial.

Foundation Series User Guide A-1

Appendix A

Glossary

This appendix contains definitions and explanations for terms usedin the Foundation Series User Guide.

actionsIn state machines, actions are HDL statements that are used to makeassignments to output ports or internal signals. Actions can beexecuted at several points in a state diagram. The most commonlyused actions are state actions and transition actions. State actions areexecuted when the machine is in the associated state. Transitionactions are executed when the machine goes through the associatedtransition.

aliasesAliases, or signal groups, are useful for probing specific groups ofnodes.

attributeAttributes are instructions placed on symbols or nets in a schematicto indicate their placement, implementation, naming, direction, orother properties.

binary encodingUsing the minimum number of registers to encode a state machine iscalled binary, or maximal, encoding, because the registers are used totheir maximum capacity. Each register represents one bit of a binarynumber.


A-2 Xilinx Development System

BitGenThe BitGen program produces a bitstream for Xilinx FPGA deviceconfiguration. The BitGen program displays as the Configure stepwithin the Design Manager Flow Engine.

blockA group consisting of one or more logic functions. Also called CLB.

componentA component is an instantiation or symbol reference from a library oflogic elements that can be placed on a schematic.

conditionIf there is more than one transition leaving a state in a state machine,you must associate a condition with each transition. A condition is aBoolean expression.

constraintConstraints are specifications for the implementation process. Thereare several categories of constraints: routing, timing, area, mapping,and placement constraints.

Using attributes, you can force the placement of logic (macros) inCLBs, the location of CLBs on the chip, and the maximum delaybetween flip-flops. CLBs are arranged in columns and rows on theFPGA device. The goal is to place logic in columns on the device toattain the best possible placement from the standpoint of bothperformance and space.

CPLDComplex Programmable Logic Device

CPLD fitterThe CPLD Fitter implements designs for the XC9500 devices.

Glossary


design entry toolsThe Foundation design entry tools consist of the Schematic Editor,HDL Editor, and State Editor. The tools can be accessed via buttons inthe Project Manager. The optional Foundation Express packagecontains VHDL and Verilog design entry tools.

design implementation toolsA set of tools that comprise the mainstream programs offered in theXilinx design implementation tools. The tools are NGDBuild, MAP,PAR, NGDAnno, TRCE, all the NGD2 translator tools, BitGen,PROMGen, and EPIC.

Design ManagerXilinx’s graphical user interface for managing and implementingdesigns. The Design Manager can be accessed by selecting theImplement M1 button from the Project Manager.

EPICThe Editor for Programmable Integrated Circuits (EPIC) is agraphical application for displaying and configuring FPGAs. You canuse EPIC to place and route critical components before running theautomatic place and route tools on your designs.

FPGAField Programmable Gate Arrays

guided mappingAn existing NCD file is used to “guide” the current MAP run. Theguide file may be used at any stage of implementation: unplaced orplaced, unrouted or routed.

HDLHDL (hardware description language)



hierarchical designsA design has a hierarchical structure if any of its components areinstantiated as HDLs, schematics, netlists, LogiBLOX modules, orstate machines.

instantiationIncorporating a macro or module into a top-level design. Theinstantiated module can be a LogiBLOX module, VHDL, schematicdesign, state machine, or netlist.

Language AssistantThe Language Assistant in the HDL Editor provides templates to aidyou in common VHDL constructs, common logic functions, andarchitecture-specific features.

lockingLock placement applies a constraint to all placed components in yourdesign. This option specifies that placed components cannot beunplaced, moved, or deleted.

LogiBLOXXilinx design tool for creating high-level modules such as counters,shift registers, and multiplexers.

logicLogic is one of the three major classes of ICs in most digital electronicsystems — microprocessors, memory, and logic. Logic is used fordata manipulation and control functions that require higher speedthan a microprocessor can provide.

Library ManagerThe Library Manager allows you to perform a variety of operationson the design entry tools libraries and their contents. These librariescontain the primitives and macros that you use to build your design.

Glossary


Logic SimulatorThe Logic Simulator, a real-time interactive design tool, can be usedfor both functional and timing simulation of designs. The LogicSimulator creates an electronic breadboard of your design directlyfrom your design’s netlist. The Logic Simulator can be accessed viathe SIM Funct and SIM Timing buttons in the Project Manager.

macroA macro is a component made of nets and primitives (flip-flops orlatches) that implements high-level functions, such as adders,subtractors, and dividers. Soft macros and RPMs are types of macros.

A macro can be unplaced, partially placed, or fully placed, and it canalso be unrouted, partially routed, or fully routed. See also “physicalmacro.”

MAPThe MAP program maps a logical design to a Xilinx FPGA. The inputto a mapping program is an NGD file. The MAP program is initiatedwithin the Flow Engine in the Design Manager.

NCD fileAn NCD (netlist circuit description) file is the output design file fromthe MAP program, LCA2NCD, PAR, or EPIC. It is a flat physicaldesign database correlated to the physical side of the NGD in order toprovide coupling back to the user’s original design. The NCD file isan input file to MAP, PAR, TRCE, BitGen, and NGDAnno.

NGDBuildThe NGDBuild program performs all the steps necessary to read anetlist file in XNF or EDIF format and create an NGD file describingthe logical design. The NGDBuild program executes as the Translatestep within the Design Manager Flow Engine.



NGD fileAn NGD (native generic database) file is an output from theNGDBuild run. An NGD file contains a logical description of thedesign expressed both in terms of the hierarchy used when the designwas first created and in terms of lower-level Xilinx primitives towhich the hierarchy resolves.

one-hot encodingFor state machines, in one-hot encoding, an individual state registeris dedicated to one state. Only one flip-flop is active, or hot, at anyone time.

optimizationFoundation allows you to control optimization of a design on amodule-by-module basis. This means that you have the ability to, forinstance, optimize certain modules of your design for speed, some forarea, and some for a balance of both.

PAR (Place and Route)PAR is a program that takes an NCD file, places and routes thedesign, and outputs an NCD file. The NCD file produced by PAR canbe used as a guide file for reiterative placement and routing. TheNCD file can also be used by the bitstream generator, BitGen.

path delayA path delay is the time it takes for a signal to propagate through apath.

PCF fileThe PCF file is an output file of the MAP program. It is an ASCII filecontaining physical constraints created by the MAP program as wellas physical constraints entered by you. You can edit the PCF file fromwithin EPIC. (FPGA only)

Glossary


physical Design Rule Check (DRC)Physical Design Rule Check (DRC) is a series of tests to discoverlogical and physical errors in the design. Physical DRC is appliedfrom EPIC, BitGen, PAR, and Hardware Debugger. By default, resultsof the DRC are written into the current working directory.

physical macroA physical macro is a logical function that has been created fromcomponents of a specific device family. Physical macros are stored infiles with the extension .nmc. A physical macro is created when EPICis in macro mode. See also “macro.”

pinA pin can be a symbol pin or a package pin. A package pin is aphysical connector on an integrated circuit package that carriessignals into and out of an integrated circuit. A symbol pin, alsoreferred to as an instance pin, is the connection point of an instance toa net.

pinwiresPinwires are wires which are directly tied to the pin of a site (i.e. CLB,IOB, etc.)

projectFoundation organizes related files into a distinct logical unit called aproject, which contains a variety of file types.

Project ManagerThe Project Manager, the overall Foundation project managementtool, contains the Foundation Series tools used in the design process.Via the Project Manager, you access both the design entry tools andthe design implementation tools.



routeThe process of assigning logical nets to physical wire segments in theFPGA that interconnect logic cells.

route-throughA route that can pass through an occupied or an unoccupied CLB siteis called a route-through. You can manually do a route-through inEPIC. Route-throughs provide you with routing resources that wouldotherwise be unavailable.

Schematic EditorThe schematic design tool accessed by selecting the Schematic Editorbutton in the Project Manager.

state diagramA state diagram is a pictorial description of state relationships.

state machine designsState machine designs typically start with the translation of a conceptinto a “paper design,” usually in the form of a state diagram or abubble diagram. The paper design is converted to a state table and,finally, into the source code itself.

statesThe values stored in the memory elements of a device (flip-flops,RAMs, CLB outputs, and IOBs) that represent the state of that devicefor a particular readback (time). To each state, there corresponds aspecific set of logical values.

Symbol EditorWith the Symbol Editor, you can edit features of component symbolssuch as pin locations, pin names, pin numbers, pin shape, and pindescriptions for component symbols.

Glossary


transitionsTransitions define the movement from one state to another in a statemachine. They are drawn as arrows between state bubbles.

UCF fileA UCF (user constraints file) contains user-specified logicalconstraints.

VHDLFoundation design entry tool accessed via the HDL Editor.

wireA wire is either a net or a signal.

XVHDL CompilerThis compiler synthesizes and generates EDIF 2 0 0 from MetamorVHDL code or state machine designs.



Foundation Series User Guide B-1

Appendix B


This appendix discusses some of the more common constraints youcan apply to your design to control the timing and layout of a XilinxFPGA or CPLD; it describes how to use constraints at each stage ofdesign processing.

This appendix contains the following sections:

• “Constraint Entry Mechanisms” section

• “Translating and Merging Logical Designs” section

• “Constraints File Overview” section

• “UCF Timing Constraints” section

• “Layout Constraints” section

• “Efficient Use of Timespecs and Layout Constraints” section

• “Standard Block Delay Symbols” section

• “Table of Supported Constraints” section

• “Constraining LogiBLOX RAM/ROM with Synopsys” section

For a complete listing of all supported constraints, please refer to theLibraries Guide (Chapter 13, “Attributes, Constraints, and CarryLogic,”). For a more complete discussion of how timing constraintswork in Foundation, refer to the Development System Reference Guide(Chapter 4, “Using Timing Constraints,”). For information on allattributes, including timing constraints, used in CPLD designs, referto the Foundation online help.


B-2 Xilinx Development System

Constraint Entry MechanismsThe Foundation version of the Xilinx design implementation toolsallows you to control the implementation of a design by definingconstraints that affect the mapping and layout of the physical circuit.Additionally, you may specify the “path” timing requirements of thecircuit to obtain the best results and allow the implementation toolsto choose the layout which best satisfies these requirements.

The various design constraints available to use within Foundationcan be entered at design creation (i.e., the logical domain) or after thedesign is mapped (i.e., the physical domain). Constraints entered inthe logical domain are either entered into the schematic or applied toa synthesis process and then forward-annotated through the netlistfile—for example, the XNF netlist file the Synopsys FoundationExpress flow generates.

Constraints entered in the physical domain are entered directly intothe Physical Constraints File (PCF). These constraints areconceptually the same as those entered during design creation,however they are directly related to objects within the physicaldesign database and are therefore applied using the PCF syntax.

The following figure illustrates the constraints entry approach for theFoundation version of the Xilinx tools.



Figure B-1 Constraint Entry Flow

Translating and Merging Logical DesignsThe process of implementing a design within the Foundation toolsstarts with a logical design file (NGD) that represents the designcreated by the NGDBuild application (as shown in the “ConstraintEntry Flow” figure).

The NGD file contains all of the design’s logic structures (gates) andconstraints. The NGD file is produced through the NGDBuild processwhich controls the translation and merging of all of the related logicdesign files.

Entry Tool

Schematic Entry or HDL Tool

X8085

NGDBuild

Netlist

NCD PCF

To Physical Implementation Tools

User Constraints File

Physical Constraints File

MAP

UCF

NGD



All design files are translated from industry standard netlists intointermediate NGO files by one of two netlist translation programsXNF2NGD or EDIF2NGD. The exception to this rule is logic, which iscreated through the use of LogiBLOX components. LogiBLOXcomponents may be compiled directly in memory, and are thereforenever written to disk as a separate intermediate NGO file.

Constraints File OverviewThe following subsections describe the User Constraint File and thePhysical Constraints File.

User Constraint File (UCF)The User Constraint File was developed to provide a convenientmechanism for constraining a logical design without returning to thedesign entry tools. UCF constraints intentionally overwriteconstraints that are present in the netlist.

UCF constraints override any constraints contained within the netlistcreated by the schematic or synthesis tools. A constraint that is beingapplied via the UCF file must specify the complete hierarchical pathname for the instance or net being constrained.

In the Foundation design flow, UCF constraints are considered moresignificant due to their later appearance and provide a mechanism forestablishing or modifying logical design constraints withoutrequiring you to re-enter a schematic or synthesis tool.

The process of building the complete logical design representation(NGD files) is the job of NGDBuild. In developing this completedesign database, NGDBuild annotates design constraints with thoseit finds in a UCF file. If a UCF file exists with the same name as thetop-level netlist then it will automatically be read. Otherwise, youmust indicate a specific file for User Constraints in the Options dialogbox. The syntax for the UCF constraints file is explained (on a per-constraint basis) in the “UCF Timing Constraints” section.

Note: Versions prior to M1.2 required the -uc switch to identify aUser Constraint File that needed to be annotated to the design.Versions M1.2 and later allow UCF file annotation to be performed bydefault—if the UCF file has the same base name as the input.



Physical Constraints File (PCF)The physical design is the “domain” of the layout tools, and as such,the PCF file is written in terms that these tools can readily interpret.Layout and timing constraints are written in terms of the physicaldesign’s components (COMPs), fractions of COMPs (BELs), andcollections of COMPs (macros).

Because of this different design viewpoint, the PCF syntax is notnecessarily the same as that used in the logical design constraint files(UCF/NCF). Furthermore, because the PCF file is written to use bythe physical design implementation tools, its syntax may not be asintuitive as the UCF file. Regardless of the syntactical challengesassociated with using a PCF file, many designers will choose to workat the physical level of design abstraction because:

• It is readily modified and immediately applicable to the task athand—implementing an FPGA (that is, there is no need to re-runNGDBuild or MAP in order to run layout or analysis tools).

• Implications of logical design structures on the physical design’simplementation only become obvious once the design isevaluated using the physical tools. Altering the PCF file for“what-if” analysis can be desirable.

• Certain constraints are only available within the PCF file.

Note: If you modify the PCF file, you should be certain that you enteryour constraints after the line “SCHEMATIC END ;”. Otherwise,your constraints will be overwritten every time MAP is re-executed.

Case SensitivityYou should be aware that since EDIF is a case-sensitive format, theFoundation constraints are case sensitive as well. Therefore, youshould always be sure that you specify the net names and instancenames exactly as they are in your schematic or code. You should alsobe consistent when using TNMs and other user-defined names inyour constraints file; always use the same case throughout. For sitenames (such as “CLB_R2C8” or “P2”), you should use only uppercase letters, since site names within Xilinx devices are all upper case.



UCF Timing ConstraintsThe following subsections discuss UCF timing constraints.

The “From:To” Style TimespecWhen using the From:To style of constraint, the path(s) that areconstrained are specified by declaring the start point and end point,which must be a pad, flip-flop, latch, or RAM. To group a set ofendpoints together, you may attach a TNM attribute to the object (orto a net that is an input to the object). A TIMEGRP is a method forcombining two or more sets of TNMs or other TIMEGRPs together, oralternatively, to create a new group by pattern matching (grouping aset of objects that all have output nets that begin with a given string).

TNMs are used to identify a group of design objects which are to bereferenced within a Timespec. If a TNM is placed on a net, theFoundation tools determine TNM membership by tracing forwardfrom the specified net to all the valid endpoints of the net. Refer to theDevelopment System Reference Guide (Chapter 4, “Using TimingConstraints,”) for more information on this subject.

# This is a comment line# UCF FROM:TO style Timespecs

NET DATA_EN TNM = PIPEA ;TIMEGRP BUSPADS = PADS(BUS*) ;TIMESPEC TS01 = FROM:BUSPADS:TO:PIPEA:20 ;

# Spaces or colons (:) may be used as field separators

TIMESPEC TS02 = FROM FFS TO RAMS 15 ;

The first line of the above example illustrates the application of theTNM (Timing Name) PIPEA to the net named DATA_EN. The secondline illustrates the TIMEGRP design object formed using a patternmatching mechanism in conjunction with the predefined TIMEGRP“PADS”. In this example, the TIMEGRP named BUSPADS willinclude only those PADs with names that start with BUS.

Each of the user-defined Timegroups is then used to define the objectspace constrained by the timing specification (Timespec) namedTS01. This timing specification states that all paths from each memberof the BUSPADS group to each member of the PIPEA group need tohave a path delay that does not exceed 20 nanoseconds (ns are thedefault units for time).



The TIMESPEC TS02 constraint illustrates a similar type of timingconstraint using the predefined groups FFS and RAMS.

It is worthwhile noting that all From:To Timespecs must be relative toa Timegroup. The above example illustrates that Timegroups may bedefined by you either explicitly (TIMEGRPs) or implicitly (TNMs), orthey may be predefined groups (PADS, LATCHES, FFS, RAMS).

There is an additional keyword that can be added to the From:Tospecification that allows the user to narrow the set of paths that arecovered—THRU. By using the From:Thru:To form of a Timespec, youare able to constrain only those paths that go through a certain set ofnets, defined by the TPTHRU keyword, as shown in the followingexample.

# UCF FROM:TO Timespec using THRU

NET $1I6/thisnet TPTHRU=these ;NET $1I6/thatnet TPTHRU=these ;

TIMEGRP sflops=FFS(DATA*) ;TIMEGRP dflops=FFS(OUTREG*) ;

TIMESPEC TS23=FROM:sflops:THRU:these:TO:dflops:20 ;

Here, only those paths that go from the Q pin of the sflops through thenets $1I6/thisnet and $1I6/thatnet and on to the D pin of dflopswill be controlled by TS23.

Using TPSYNCIn the Foundation design implementation tools, you may define anynode as a source or destination for a Timespec with the TPSYNCkeyword. The use of TPSYNC is similar to TPTHRU—it is a label thatis attached to a set of nets, pins, or instances in the design.

For example, suppose a design has a PAD ENABLE_BUS that mustarrive at the enable pin of several different 3-state buffers in less thana specified time. With the Foundation tools, you can now define that3-state buffer as an endpoint for a timing spec. For example,

# TPSYNC example; pad to a 3-state buffer enable pin# Note TPSYNC attached to 3-state buffer’s output NET

NET BUS3STATE TPSYNC=bus3;TIMESPEC TSNewSpc3=FROM:PAD(ENABLE_BUS):TO:bus3:20ns;



In the NET statement shown above, the TPSYNC is attached to theoutput net of a 3-state buffer called BUS3STATE. If a TPSYNC isattached to a net, then the source of the net is considered to be theendpoint (in this case, the 3-state buffer itself). The subsequentTIMESPEC statement can use the TPSYNC name just as it uses aTNM name.

The next TPSYNC example shows how you may use the keywordPIN instead of NET if you wish to attach an attribute to a pin:

# Note TPSYNC attached to 3-state buffer’s enable PIN

PIN $1I6/BUSMACRO1/TRIBUF34.T TPSYNC=bus1;TIMESPEC TSNewSpc1=FROM:PAD(ENABLE_BUS):TO:bus1:20ns;

In this example, the instance name of the 3-state buffer is statedfollowed by the pin name of the enable (.T). If a TPSYNC is attachedto a primitive input pin, then the primitive’s input is considered thestartpoint or endpoint for a timing specification. If it is attached to aoutput pin, then the output of the primitive is used.

The last TPSYNC example shows how you may use the keywordINST if you wish to attach an attribute to a instance:

# Note TPSYNC attached to 3-state buffer INSTANCE

INST $1I6/BUSMACRO2/BUFFER_2 TPSYNC=bus2;TIMESPEC TSNewSpc2=FROM:PAD(ENABLE_BUS):TO:bus2:20ns;

If a TPSYNC is attached to an instance, then the output of theinstance is considered the startpoint or endpoint for a timingspecification.

The Period Style TimespecThe TIMESPEC form of the PERIOD constraint allows flexibility ingroup definitions and allows you to define clock timing relative toanother TIMESPEC. The following example illustrates the use of thePERIOD Timespec referenced to timegroups CLK2_GRP and CLK3.

# UCF PERIOD style Timespecs

NET CLK2 TNM = CLK2_GRP ;NET CLK3 TNM = CLK3 ;

TIMESPEC TS03 = PERIOD CLK2_GRP 50 ;TIMESPEC TS04 = PERIOD CLK3 TS03 * 2 ;



Furthermore, the example shows how constraints and nets may begiven the same name because they occupy separate name-spaces.Also, it shows the constraint syntax whereby one Timespec is definedrelative to another (the value of TS04 is declared to be two times thatof TS03).

The PERIOD constraint covers all timing paths which start or end at aregister, latch, or synchronous RAM that is clocked by the referencednet. The only exception to this rule are paths to output pads, whichare not covered by the PERIOD constraint. (Input pads, which are thesource of a “pad-to-setup” timing path for one of the specifiedsynchronous elements, are covered by the PERIOD constraint.)

The flexibility of the TIMESPEC form of the PERIOD constraint arisesfrom being able to modify the contents of the TIMEGRP once thedesign has been mapped. By adding or removing objects from theTIMEGRP, which are listed in the PCF file, the paths that are coveredby the PERIOD constraint may be altered.

If you do not need the flexibility offered by the TIMESPEC form, theNET form of the PERIOD constraint may be used. The syntax for theNET form of the PERIOD constraint is simpler than the TIMESPECform, while continuing to provide the same path coverage. Thefollowing example illustrates the syntax of the NET form of thePERIOD constraint:

# NET form of the PERIOD timing constraint# (no TSidentifier)

NET CLK PERIOD = 40 ;

The Offset ConstraintThe OFFSET constraint is applied to a net that connects with a PAD(see the “Using OFFSET Constraints” figure). It defines the delay of asignal relative to a clock and is only valid for registered data paths.The OFFSET constraint specifies the signal delay external to the chip,allowing the implementation tools to automatically adjust relevantinternal delays (CLK buffer and distribution delays) to accommodatethe external delay specified with this constraint.

# Net form of the OFFSET timing constraint

NET ADD0_IN OFFSET = IN 14 AFTER CLK ;



In analyzing OFFSET paths, the Xilinx timing tools adjust thePERIOD associated with the constrained synchronous element basedon both the timing specified in the OFFSET constraint and the delayof the referenced clock signal. In the “Using OFFSET Constraints”figure, assume a delay of 8 ns for the signal CLK to arrive at the CLB,a 5 ns setup time for ADD0, and a 14 ns OFFSET delay for the signalADD0. Assume a period of 40 ns is specified. The Foundation toolsallocate 29 ns for the signal ADD0 to arrive at the CLB input pin(40 ns - 14 ns + 8 ns - 5 ns = 29 ns).

Figure B-2 Using OFFSET Constraints

This same timing constraint could be applied using theFROM:PADS:TO:FFS timing constraint. However, using a From:Tomethodology would require the designer to know the intrinsic CLKnet delay, and the user would have to adjust the value assigned to theFrom:To Timespec. The internal CLK net delay is implicit in theOFFSET/PERIOD constraint. Furthermore, migrating the design toanother speed grade or device would require modification of theFrom:To Timespec to accommodate the new intrinsic CLK net delay.It should be noted that an alternative solution is to use the flip-flop inthe IOB of certain FPGA architectures (XC4000E/EX, for instance), asthe clock-to-setup time is specified in the Programmable Logic DataBook.

Note: Relative Timespecs can only be applied to similar Timespecs.For example, a PERIOD Timespec may be defined in terms of anotherPERIOD Timespec, but not a From:To Timespec.

D Q

p/o CLBCLK IOB

CLK

ADD0ADD0 IN

CLK IN

IOB

OFFSET of ADD0 with respect to CLK

X8086



Ignoring PathsWhen a Timespec is declared that includes paths where the timing isnot important, the tools may create a less optimal route since there ismore competition for routing resources. This problem can bealleviated by using a TIG (timing ignore) attribute on the non-criticalnets. TIG causes all paths that fan out from the net or pin where it isapplied to be “ignored” during timing simulation.

#Timespec-specific TIG example

NET $1I456/slow_net TIG=TS01, TS04 ;

The above syntax indicates that $1I456/slow_net should not havethe Timespec TS01 or TS04 applied to it.

On the other hand, the following syntax indicates that the layouttools should ignore paths through the $1I456/slow_net net for allknown Timespecs.

#Global TIG example

NET $1I456/slow_net TIG

Controlling SkewA new feature of the Foundation timing tools gives you the ability tocontrol skew. The maximum skew (MAXSKEW) is the differencebetween the fastest fanout of a given net and the slowest fanout ofthat same net.

#MAXSKEW example

NET $1I345/net_a MAXSKEW=3 ;

The above indicates that 3 ns is the maximum skew allowed on$1I345/net_a .



Constraint PrecedenceA design may assign a precedence to Timespecs only within a certainclass of constraints. For example, you may specify a priority for aparticular From:To specification to be greater than another, but youmay not specify a From:To constraint to have priority over a TIGconstraint. The following example illustrates the explicit assignmentof priorities between two same-class timing constraints, the lowestnumber having the highest priority.

# Priority UCF example

TIMESPEC TS01 = FROM GROUPA TO GROUPB 40 PRIORITY 4 ;TIMESPEC TS02 = FROM GROUP1 TO GROUP2 35 PRIORITY 2;

The “Precedence of Constraints” table illustrates the order ofprecedence for the various types (and various sources) of timingconstraints.

Table B-1 Precedence of Constraints

Across Constraint Sources

Highest Priority Physical Constraint File (PCF)

User Constraint File (UCF)

Lowest Priority Input netlist

Within Constraint Sources

Highest Priority TIG (Timing Ignore)

FROM:FFS:THRU:TM1:TO:FFS specification

FROM:FFS:TO:FFSspecification

PERIOD specification

Lowest Priority “Allpaths” type constraints



Layout constraints also have an inherent precedence which is basedon the type of constraint and the site description provided to thetools. If two constraints are of the same priority and cover the samepath, then the last constraint in the constraint file will override anyother constraints that overlap.

Layout ConstraintsThe mapping constraints in the example below illustrate some of thecapabilities for controlling the implementation process for a design.The OPTIMIZE attribute is attached to the block of logic associatedwith the instance “GLUE”. All of the combinatorial logic within theblock GLUE will be optimized for speed (minimizing levels of logic)while other aspects of the design will be processed by the defaultmapping algorithms (assuming the design-based optimizationswitches are not issued).

# Mapping constraint

INST GLUE OPTIMIZE = SPEED ;

# Layout constraint

NET IOBLOCK/DATA0_IN LOC = P12 ;

The layout constraint in the example above illustrates the use of a fullhierarchical path name for the net named DATA0_IN in theapplication of the I/O location constraint. In this example, IOBLOCKis a hierarchical boundary that contains the net DATA0_IN. Locationconstraints applied to “pad nets” are used to constrain the location ofthe PAD itself, in this case to site P12.

Note: If the design contains a PAD, the constraint could have beenjust as easily applied to it directly (some design flows do not provideexplicit I/O pads in the design netlist).

Converting a Logical Design to a Physical DesignThe process of mapping translates a design from the logical designdomain to the physical design domain. The MAP process creates boththe physical design components (CLBs, IOBs, etc. ) and the physicaldesign constraints (layout and timing). The physical designcomponents are written into a Native Circuit Description (NCD) file.The physical design constraints are written into a PhysicalConstraints File (PCF).



As the design flow of the “Constraint Entry Flow” figure shows,MAP not only writes a PCF file, but also reads a specified pre-existingPCF file. MAP reads an existing PCF file in order to facilitate theoverriding of constraints that are contained within another logicdesign using the “last one wins” resolution mechanism provided bythe PCF file. The following subsection briefly describes this approach.

Last One Wins ResolutionMAP creates new physical design constraints each time it converts alogical design into a physical design. The constraints that are createdduring this process are written into the “Schematic” section of thePCF file. This section is recreated each time MAP is run based on theconstraints that are contained within the NGD file. The schematicsection is always written at the top of the PCF file, and constraintsthat are in the PCF file but outside of the Schematic section (after theline “SCHEMATIC END”) are considered to be in the “User” sectionof the PCF file. The user section is read, syntactically checked, andrewritten each time MAP is run. Since these constraints always followthose written into the schematic section, they will always takeprecedence (following the “last-one-wins” rule).

Efficient Use of Timespecs and Layout ConstraintsThe previous section described the mechanisms available forconstraining a design’s timing within the Foundation tools. Thesections that follow summarize each of the constraints that areavailable. The natural question that will arise is “How should I bestdescribe my requirements to the tools?”

The robust nature of the language enables you to define your designrequirements at the highest level of abstraction first, and then finetune the timing requirements using more specific Timespecs, ifneeded. This is the methodology that should be followed.

The following observations help to illustrate the reasons why thismethodology should be followed (from a tool runtime perspective).

• The use of explicit Timegroups causes slower runtimes than theuse of implicit timegroups arising from the use of constraintssuch as PERIOD.

• The processing of larger Timegroups takes longer than theprocessing of smaller Timegroups.



• The use of many specific Timespecs results in slower runtimesthan the use of a smaller set of more general Timespecs.

In conclusion, overall design runtime is improved when a “qualifiedglobal” timing methodology is employed instead of a “thorough-detailed” timing methodology.

The following examples clearly identify the “preferred” mechanismfor controlling the timing of your design. The preferred methodassumes a goal of getting the required results in the fastest run-timepossible. If the design has a single clock and required I/O timing thatequals the clock period, all that is needed are the three constraintsshown in the following example:

# Global UCF example

NET CLK1 PERIOD = 40 ;NET OUT* OFFSET = OUT 13 AFTER CLK ;

TIMESPEC TS01 = FROM PADS TO PADS 40 ;

The PERIOD constraint covers all pad-to-setup and clock-to-setuptiming paths. The OFFSET constraint covers the clock-to-pad timingfor each of the output nets beginning with OUT. Both the OFFSETand PERIOD constraints account for the delay of the Clock Buffer/Net in the I/O timing calculations.

The PCF snippet below illustrates the differences in syntax betweenthe UCF and PCF languages. In addition to the syntactical changes, itis important to note that net and instance names may change. As anexample, one of the net matches resulting from the UCF “NET OUT*”constraint is now applied to “COMP OUT1_PAD”. The nameOUT1_PAD is the name assigned to the pad instance. In addition toname changes, another difference to note is the verbosity of the PCF.In the PCF there is additional syntax for “MAXDELAY”, “TIMEGRP”and “PRIORITY”. These are all optional qualifications of theTimespec within the UCF, but written explicitly to the PCF fileillustrating the full flexibility of the language.

# Global PCF example

SCHEMATIC START;

. . .

NET PERIOD “CLK_IN” = 40 nS HIGH 50.00% ;COMP “OUT1_PAD” OFFSET = OUT 40 ns AFTER COMP “CLK”;



COMP “OUT2_PAD” OFFSET = OUT 40 ns AFTER COMP “CLK”;

TS01 = MAXDELAY FROM TIMEGRP “PADS” TO TIMEGRP “PADS”40000 pS PRIORITY 0;

SCHEMATIC END;

The next UCF example illustrates the use of both global constraints(PERIOD, OFFSET) for generally constraining the design anddetailed Timespecs (FROM:THRU:TO) for providing fast and slowexceptions to the general timing requirements. Because the amount ofconstraints placed on a design directly impact runtime, it isrecommended that users first apply global constraints, then applyindividual constraints only to those elements of the design thatrequire additional constraints (or an exception to a constraint). Themore global the constraints, the better the runtime performance of thetools.

# Sample UCF file# Specify target device and package

CONFIG PART = XC4010e-PQ208-3 ;

# Global constraints

NET CLK1 PERIOD = 40 ;NET DATA_OUT* OFFSET = OUT 15 AFTER DCLK ;TIMESPEC TS01 = FROM PADS TO PADS 40 ;

# Layout constraints

NET SCLINF LOC = P125 ;

# Detailed constraints# Exception to cover X_DAT and Y_DAT buses

NET ?_DAT* OFFSET = OUT 25 AFTER CLK_IN ;

# Ignore timing on reset net

NET RESET_N TIG ;

# Slow exception for data leaving INA FFs

TIMESPEC TS02 = FROM FFS(INA*) TO FFS 80 ;

# Faster timing required for data leaving RAM

TIMESPEC TS03 = FROM RAMS TO FFS 20 ;

# Form special timegroups related to RAMs



INST $1I64 TNM = SPDRAM ;NET RAMBUS0 TPTHRU = RAMVIA ;NET RAMBUS1 TPTHRU = RAMVIA ;

# Specify timing for this special timing path

TIMESPEC TS04 = FROM SPDRAM THRU RAMVIA TO FFS 45 ;

Standard Block Delay SymbolsThe “Timing Symbols and Their Default Values” table lists the blockdelay symbols, each with their corresponding description. There is aone-to-many correspondence between these symbol names and theProgrammable Logic Data Book symbol names. For those symbols listedas having a default value of disabled, no timing analysis is performedon paths that have a segment composed of symbol path. For example,paths which have a set/reset to output path will not be analyzed.Any of the block delays (Symbol) listed in the table may be explicitlyenabled or disabled using the PCF file.

The following example shows the PCF syntax that enables the pathtracing for all paths that contain RAM data to out paths. Note thatthis PCF directive is placed in the user section of the PCF.

SCHEMATIC END;

// This is a PCF comment line// Enable RAM data to out path tracing

ENABLE = ram_d_o;



Table B-2 Timing Symbols and Their Default Values

Symbol Default Description

reg_sr_q Disabled Set/reset to output propagation delay

lat_d_q Disabled Data to output transparent latch delay

ram_d_o Disabled RAM data to output propagation delay

ram_we_o Enabled RAM write enable to output propaga-tion delay

tbuf_t_o Enabled TBUF tristate to output propagationdelay

tbuf_i_o Enabled TBUF input to output propagationdelay

io_pad_I Enabled IO pad to input propagation delay

io_t_pad Enabled IO tristate to pad propagation delay

io_o_I Enabled IO output to input propagation delay(Disabled for tristated IOBs.)

io_o_pad Enabled IO output to pad propagation delay



Table of Supported ConstraintsThe “Constraint Applicability” table presents a summary of allFoundation-supported constraints; it also shows whether theconstraint must be entered at the schematic level or whether it can bespecified in one or more of the valid constraint file types (NCF, UCF,or PCF). For further explanation and examples of each of theconstraints, please see the Libraries Guide (Chapter 13, “Attributes,Constraints, and Carry Logic”).

Table B-3 Constraint Applicability

Origin of Constraint

Constraint Schematic UCF PCF

BASE Y N N

BLKNM Y Y N

BUFG Y Y N

COLLAPSE Y Y N

COMPGRP N N Y

CONFIG** Y N N

DECODE Y Y N

DIVIDE1_BYDIVIDE2_BY

Y Y N

DOUBLE Y N N

DRIVE Y Y N

DROP_SPEC N Y Y*

EQUATE_FEQUATE_G

Y N N

FAST Y Y N

FILE Y N N

FREQUENCY N N Y

HBLKNM Y Y N

HU_SET Y Y N

INIT Y N N

INREG Y Y Y



KEEP Y Y N

LOC Y Y Y*

LOCATE N N Y

LOCK N N Y

MAP Y Y N

MAXDELAY Y Y Y*

MAXSKEW Y Y Y*

MEDDELAY Y Y N

S(ave) Net Flag Attributes Y Y N

NODELAY Y Y N

NOREDUCE Y Y N

OFFSET N Y Y*

OPTIMIZE Y Y N

OPT_EFFORT Y Y N

OUTREG Y Y Y

PATH N N Y

PART Y Y N

PENALIZE TILDE N N Y

PERIOD Y Y Y*

PIN N N Y

PRIORITIZE N N Y

PROHIBIT Y Y Y*

PWR_MODE Y Y N

RLOC Y Y N

RLOC_ORIGIN Y Y Y*

RLOC_RANGE Y Y Y

SITEGRP N N Y

SLOW Y Y N






TIG Y Y Y*

Timegroup Attributes Y Y Y

TNM Y Y N

TPSYNC Y Y N

TPTHRU Y Y N

TSidentifier Y Y Y*

U_SET Y Y N

USE_RLOC Y Y N

WIREAND Y Y N

* Use cautiously—while constraint is available, there are differences between theUCF/NCF and PCF syntax.

** The CONFIG attribute configures internal options of an XC3000 CLB or IOB. Do notconfuse this attribute with the CONFIG primitive, which is a table containingPROHIBIT and PART attributes.






Constraining LogiBLOX RAM/ROM with SynopsysIn the M1 XSI (Xilinx Synopsys Interface) HDL methodology,whenever large blocks of RAM/ROM are needed, LogiBLOX RAM/ROM modules are instantiated in the HDL code. With LogiBLOXRAM/ROM modules instantiated in the HDL code, timing and/orplacement constraints on these RAM/ROM modules, and the RAM/ROM primitives that comprise these modules, can be specified in aUCF file. To create timing and/or placement constraints for RAM/ROM LogiBLOX modules, knowledge of how many primitives willbe used and how the primitives, and/or how the RAM/ROMLogiBLOX modules are named is needed.

Estimating the Number of Primitives UsedWhen a RAM/ROM is specified with LogiBLOX, the RAM/ROMdepth and width are specified. If the RAM/ROM depth is divisibleby 32, then 32x1 primitives are used. If the RAM/ROM depth is notdivisible by 32, then 16x1 primitives are used instead. In the case ofdual-port RAMs, 16x1 primitives are always used. Based on whether32x1 or 16x1 primitives are used, the number of RAM/ROM can becalculated.

For example, if a RAM48x4 was required for a design, RAM16x1primitives would be used. Based on the width, there would be fourbanks of RAM16x1s. Based on the depth, each bank would have threeRAM16x1s.

How the RAM Primitives are NamedUsing the example of a RAM48x4, the RAM primitives inside theLogiBLOX are named as follows:

Each primitive in a LogiBLOX RAM/ROM module has an instancename of MEMx_y, where y represents the primitive position in thebank of memory and where x represents the bit position of the RAM/ROM output.

MEM0_0 MEM1_0 MEM2_0 MEM3_0





For the next two items, refer to the Verilog/VHDL examples includedat the end of this section. The Verilog/VHDL example instantiates aRAM32x2S, which is in the bottom of the hierarchy. The RAM32x2Swas implemented with LogiBLOX. The next two items are writtenwithin the context of the Verilog examples but also apply to theVHDL examples as well.

Referencing a LogiBLOX Module/Component in theFoundation Express Flow

LogiBLOX RAM/ROM modules in the Foundation Express flow areconstrained via a UCF file. LogiBLOX RAM/ROM modulesinstantiated in the HDL code can be referenced by the full-hierarchical instance name. If a LogiBLOX RAM/ROM module is atthe top-level of the HDL code, then the instance name of theLogiBLOX RAM/ROM module is just the instantiated instance name.

In the case of a LogiBLOX RAM/ROM, which is instantiated withinthe hierarchy of the design, the instance name of the LogiBLOXRAM/ROM module is the concatenation of all instances whichcontain the LogiBLOX RAM/ROM. The concatenated instance namesare separated by a “_¨. In the example, the RAM32X1S is namedmemory. The module memory is instantiated in Verilog moduleinside with an instance name U0. The module inside is instanti-ated in the top-level module test. Therefore, the RAM32X1S can bereferenced in a .ucf file as U0/U0. For example, to attach a TNM tothis block of RAM, the following line could be used in the UCF file:

INST U0_U0 TNM=block1 ;

Since U0/U0 is composed of two primitives, a Timegroup calledblock1 would be created; block1 TNM could be used throughout the.ucf file as a Timespec end/start point, and/or U0/U0 could have aLOC area constraint applied to it. If the RAM32X1S has beeninstantiated in the top-level file, and the instance name used in theinstantiation was U0, then this block of RAM could just be referencedby U0.



Referencing the Primitives of a LogiBLOX Module inthe Foundation Express Flow

Sometimes it is necessary to apply constraints to the primitives thatcompose the LogiBLOX RAM/ROM module. For example, if youchoose a floorplanning strategy to implement your design, it may benecessary to apply LOC constraints to one or more primitives inside aLogiBLOX RAM/ROM module.

Returning to the RAM32x2S example above, suppose that the each ofthe RAM primitives had to be constrained to a particular CLBlocation. Based on the rules for determining the MEMx_y instancenames and using the example from above, each of the RAMprimitives could be referenced by concatenating the full-hierarchicalname to each of the MEMx_y names. The RAM32x2S created byLogiBLOX would have primitives named MEM0_0 and MEM1_0. So,for Foundation Express, CLB constraints in a UCF file for each of thesetwo items would be:

INST U0_U0/MEM0_0 LOC=CLB_R10C10 ;INST U0_U0/MEM0_1 LOC=CLB_R11C11 ;

Foundation Express Verilog ExampleFollowing is a Verilog example.

test.v:

module test(DATA,DATAOUT,ADDR,C,ENB);

input [1:0] DATA;output [1:0] DATAOUT;input [4:0] ADDR;input C;input ENB;wire [1:0] dataoutreg;reg [1:0] datareg;reg [1:0] DATAOUT;reg [4:0] addrreg;

inside U0 (.MDATA(datareg),.MDATAOUT(dataoutreg),.MADDR(addrreg),.C(C),.WE(ENB));

always@(posedge C) datareg = DATA;always@(posedge C) DATAOUT = dataoutreg;always@(posedge C) addrreg = ADDR; endmodule



inside.v:

module inside(MDATA,MDATAOUT,MADDR,C,WE);

input [1:0] MDATA;output [1:0] MDATAOUT;input [4:0] MADDR;input C;input WE;

memory U0 ( .A(MADDR), .DO(MDATAOUT),.DI(MDATA), .WR_EN(WE), .WR_CLK(C));

endmodule

test.ucf

INST “U0_U0” TNM = usermem;TIMESPEC TS_6= FROM : FFS :TO: usermem: 50;INST “U0_U0/mem0_0” LOC=CLB_R7C2;

Foundation Express VHDL ExampleFollowing is a VHDL example.

test.vhd

library IEEE;use IEEE.STD_LOGIC_1164.all;use IEEE.STD_LOGIC_UNSIGNED.all;

entity test isport(

DATA: in STD_LOGIC_VECTOR(1 downto 0);DATAOUT: out STD_LOGIC_VECTOR(1 downto 0);ADDR: in STD_LOGIC_VECTOR(4 downto 0);C, ENB: in STD_LOGIC);

end test;

architecture details of test issignal dataoutreg,datareg: STD_LOGIC_VECTOR(1 downto 0);signal addrreg: STD_LOGIC_VECTOR(4 downto 0);

component insideport(

MDATA: in STD_LOGIC_VECTOR(1 downto 0);MDATAOUT: out STD_LOGIC_VECTOR(1 downto 0);MADDR: in STD_LOGIC_VECTOR(4 downto 0);



C,WE: in STD_LOGIC);end component;

beginU0: inside port

map(MDATA=>datareg.,MDATAOUT=>dataoutreg.,MADDR=>addrreg,C=>C,WE=>ENB);

process( C )begin

if(Cevent and C=1) thendatareg <= DATA;

end if;end process;

process( C )begin

if(Cevent and C=1) thenDATAOUT <= dataoutreg;

end if;end process;

process( C )begin

if(Cevent and C=1) thenaddrreg <= ADDR;

end if;end process;

end details;

inside.vhd

entity inside isport(

MDATA: in STD_LOGIC_VECTOR(1 downto 0);MDATAOUT: out STD_LOGIC_VECTOR(1 downto 0);MADDR: in STD_LOGIC_VECTOR(4 downto 0);C,WE: in STD_LOGIC);

end inside;

architecture details of inside is component memoryport(

A: in STD_LOGIC_VECTOR(4 downto 0);DO: out STD_LOGIC_VECTOR(1 downto 0);DI: in STD_LOGIC_VECTOR(1 downto 0);WR_EN,WR_CLK: in STD_LOGIC);

end component;



beginU0: memory port map(A=>MADDR,DO=>MDATAOUT,

DI=>MDATA,WR_EN=>WE,WR_CLK=>C);end details;

test.ucf

INST “U0_U0” TNM = usermem;TIMESPEC TS_6= FROM : FFS :TO: usermem: 50;INST “U0_U0/mem0_0” LOC=CLB_R7C2;



Foundation Series User Guide C-1

Appendix C


This appendix lists the components most frequently instantiated insynthesis designs for FPGAs. This appendix contains the followingsections:

• “Architecture Definitions” section

• “STARTUP Component” section

• “BSCAN Component” section

• “READBACK Component” section

• “RAM and ROM” section

• “Global Buffers” section

• “Fast Output Primitives (XC4000X only)” section

• “IOB Components” section

The function of each component is briefly described and the pinnames are supplied, along with a listing of the Xilinx product familiesinvolved. Associated instantiation can be used to include thecomponent in an HDL design. For complete lists of the Xilinxcomponents, see the online Libraries Guide.


C-2 Xilinx Development System

Architecture DefinitionsThe following subsections describe the scope of each architecture.

XC3000 LibraryInformation appearing under the title of XC3000 pertains to theXC3000A and XC3100A families. This includes the XC3000L andXC3100L, which are identical in architecture and features to theXC3000A and XC3100A, respectively, but operate at a nominalsupply voltage of 3.3 V.

XC4000E LibraryWherever XC4000E is mentioned, it includes the XC4000E, XC4000L,and Spartan families. The XC4000L is identical in architecture andfeatures to the XC4000E but operates at a nominal supply voltage of3.3 V.

The Spartan architecture is based on the XC4000E with the followingdifferences:

• Only slave serial, master serial, and JTAG configuration modesare supported.

• Spartan does not support the following elements:

• Edge decoders: DECODE4, 8, 16

• MD0, MD1, MD2

• WAND1, 4, 8, 16

• WOR2AND

• Asynchronous RAMs: RAM16X1, RAM16X2, RAM16X4,RAM16X8, RAM32X1, RAM32X2, RAM32X4, RAM32X8



XC4000X LibraryInformation under the title XC4000X pertains to the XC4000EX,XC4000XL, and XC4000XV families. The XC4000XL is identical inarchitecture and features to the XC4000EX but operates at a nominalsupply voltage of 3.3 V. The XC4000XV has identical library symbolsto the XC4000EX and XC4000XL but operates at a nominal supplyvoltage of 2.5 V and includes additional features (the DRIVEattribute).

XC4000 ReferencesWherever XC4000 is mentioned, the information applies to both theXC4000E and XC4000X libraries.

XC5200 LibraryThe title XC5200 pertains to the XC5200 family.

XC9000 LibraryThe title XC9000 pertains to the XC9500 CPLD family.

STARTUP ComponentThe STARTUP component is typically used to access the global set/reset and global 3-state signals. STARTUP can also be used to accessthe startup sequence clock.

For information on the startup sequence and the associated signals,see the Programmable Logic Data Book and the online Libraries Guide.

Table C-1 Design STARTUP Components

Name Family Description Outputs Inputs

STARTUP XC4000EXC4000XXC5200*

Used to connect Global Set/Reset,global 3-state control, and userconfiguration clock.

Q2, Q3,Q1Q4,DONEIN

GSR,GTS, CLK

* For 5200, GSR pin is GR



BSCAN ComponentTo use the boundary-scan (BSCAN) circuitry in a Xilinx FPGA, theBSCAN component must be present in the input design. The TDI,TDO, TMS, and TCK components are typically used to access thereserved boundary scan device pads for use with the BSCANcomponent but can be connected to user logic as well. For moreinformation on the BSCAN component, the internal boundary scancircuitry, and the directional properties of the four reserved boundaryscan pads, refer to Programmable Logic Data Book and the onlineLibraries Guide.

Table C-2 Boundary Scan Components


BSCAN XC4000EXC4000XXC5200

Indicates that the boundary scanlogic should be enabled after theFPGA has been configured.

TDO,DRCK,IDLE,

SEL1, SEL2

TDI,TMS,TCK,

TDO1,TDO2

TDI XC4000EXC4000XXC5200

Connects to the BSCAN TDI input.Loads instructions and data oneach low-to-high TCK transition.

I —

TDO XC4000EXC4000XXC5200

Connects to the BSCAN TDOoutput. Provides the boundaryscan data on each low-to-high TCKtransition.

— O

TMS XC4000EXC4000XXC5200

Connects to the BSCAN TMSinput. It determines whichboundary scan is performed.

I —

TCK XC4000EXC4000XXC5200

Connects to the BSCAN TCKinput. Shifts the serial data andinstructions into and out of theboundary scan data registers.

I —

* The XC5200 has three additional pins: Reset, Update, Shift



READBACK ComponentTo use the dedicated readback logic in a Xilinx FPGA, theREADBACK component must be inserted in the input design. TheMD0, MD1, and MD2 components are typically used to access themode pins for use with the readback logic but can be connected touser logic as well. For more information on the READBACKcomponent, the internal readback logic, and the directionalproperties of the three reserved mode pins, see the Programmable LogicData Book and the online Libraries Guide.

Table C-3 Readback Components


READBACK XC4000EXC4000XXC5200

Accesses the bitstream readbackfunction. A low-to-high transitionon the TRIG input initiates thereadback process.

DATA, RIP CLK,TRIG

MD0 XC4000EXC4000XXC5200

Connects to the Mode 0 (M0) inputpin, which is used to determine theconfiguration mode.

I —



— O



I —



RAM and ROMSome of the most frequently instantiated library components are theRAM and ROM primitives. Because most synthesis tools are unableto infer RAM or ROM components from the source HDL, theprimitives must be used to build up more complex structures. Thefollowing list of RAM and ROM components is a complete list of theprimitives available in the Xilinx library. For more information on thecomponents, see the Programmable Logic Data Book and the onlineLibraries Guide.

Table C-4 Memory Components


RAM16X1 XC4000EXC4000X

A 16-word by 1-bit static read-writerandom-access memory compo-nent.

O D, A3,A2, A1,A0, WE

RAM16X1D XC4000EXC4000X

A 16-word by 1-bit dual portrandom access memory withsynchronous write capability andasynchronous read capability.

SPO,DPO

D, A3,A2, A1,A0,DPRA3,DPRA2,DPRA1,DPRA0,WE,WCLK

RAM16X1S XC4000EXC4000X

A 16-word by 1-bit static randomaccess memory with synchronouswrite capability and asynchronousread capability.

O D, A3,A2, A1,A0, WE,WCLK

RAM32X1 XC4000EXC4000X

A 32-word by 1-bit static read-writerandom access memory.

O D, A0,A1, A2,A3, A4,WE

RAM32X1S XC4000EXC4000X

A 32-word by 1-bit static randomaccess memory with synchronouswrite capability and asynchronousread capability.

O D, A4,A3, A2,A1, A0,WE,WCLK



Global BuffersEach Xilinx PLD device has multiple styles of global buffers; theXC4000EX devices have 20 actual global buffers—eight BUFGLSs,eight BUFEs, and four BUFFCLKs. For some designs it may benecessary to use the exact buffer desired to ensure appropriate clockdistribution delay.

For most designs, the BUFG, BUFGS, and BUFGP components can beinferred or instantiated, thus allowing the design implementationtools to make an appropriate physical buffer allocation. For moreinformation on the components, see the Programmable Logic Data Book.

ROM16X1 XC4000EXC4000X

A 16-word by 1-bit read-onlymemory component.

O A3, A2,A1, A0

ROM32X1 XC4000EXC4000X

A 32-word by 1-bit read-onlymemory component.

O A4, A3,A2, A1,A0

Table C-5 Global Buffer Components


BUFG XC3000XC4000EXC4000XXC5200XC9000

An architecture-independentglobal buffer, distributes high fan-out clock signals throughout a PLDdevice.

O I

BUFGP* XC4000EXC4000XXC5200XC9000

A primary global buffer, distrib-utes high fan-out clock or controlsignals throughout PLD devices.

O I

BUFGS** XC4000EXC4000X

A secondary global buffer, distrib-utes high fan-out clock or controlsignals throughout a PLD device.

O I

BUFGLS XC4000X Global low-skew buffer. BUFGLScomponents can drive all flip-flopclock pins.

O I

Table C-4 Memory Components




Fast Output Primitives (XC4000X only)One of the features added to the XC4000X architecture is the fastoutput MUX. There is one fast output MUX located in each IOBwhich can be used to implement any two input logic functions. Eachcomponent can have zero, one, or two inverted inputs. Because theoutput MUX is located in the IOB, it must be connected to the inputpin of either an OBUF or an OBUT. For more information on theoutput primitives, see the Programmable Logic Data Book.

Note: For information on how to instantiate output MUXs withinverted inputs, see the Synopsys (XSI) Interface/ Tutorial Guide.

BUFGE XC4000X Global early buffer. XC4000EXdevices have eight total, two ineach corner. BUFGE componentscan drive all clock pins in theircorner of the device.

O I

BUFFCLK XC4000X Fast clocks. XC4000EX deviceshave 4 total, 2 each on the left andright sides. BUFFCLK componentscan drive all IOB clock pins ontheir left or right half edge.

O I

* BUFGP_F for Synopsys

** BUFGS_F for Synopsys

Table C-5 Global Buffer Components




Table C-6 Fast Output Primitives


OAND2 XC4000X 2-input AND gate that is imple-mented in the output multiplexerof the XC4000EX IOB.

O F, I0

ONAND2 XC4000X 2-input NAND gate that is imple-mented in the output multiplexerof the XC4000EX IOB.

O F, I0

OOR2 XC4000X 2-input OR gate that is imple-mented in the output multiplexerof the XC4000EX IOB.

O F, I0

ONOR2 XC4000X 2-input NOR gate that is imple-mented in the output multiplexerof the XC4000EX IOB.

O F, I0

OXOR2 XC4000X 2-input exclusive OR gate that isimplemented in the output multi-plexer of the XC4000EX IOB.

O F, I0

OXNOR2 XC4000X 2-input exclusive NOR gate that isimplemented in the output multi-plexer of the XC4000EX IOB.

O F, I0

OMUX2 XC4000X 2-by-1 MUX implemented in theoutput multiplexer of theXC4000EX IOB.

O D0, D1,S0



IOB ComponentsDepending on the synthesis vendor being used, some IOBcomponents must be instantiated directly in the input design. Mostsynthesis tools support IOB D-type flip-flop inferences but may notyet support IOB D-type flip-flop inference with clock enables.Because there are many slew rates and delay types available, thereare many derivatives of the primitives shown. For a complete list ofthe IOB primitives, see the online Libraries Guide.

Table C-7 Input/Output Block Components


IBUF XC3000XC4000EXC4000XXC5200XC9000

Single input buffers. An IBUFisolates the internal circuit from thesignals coming into a chip.

O I

OBUF XC3000XC4000EXC4000XXC5200XC9000

Single output buffers. An OBUFisolates the internal circuit andprovides drive current for signalsleaving a chip.

O I

OBUFT XC3000XC4000EXC4000XXC5200XC9000

Single 3-state output buffer withactive-low output enable. (3-stateHigh.)

O I,T

IFD XC3000XC4000EXC4000XXC5200XC9000

Single input D flip-flop. Q D, C

OFD XC3000XC4000EXC4000XXC5200XC9000

Single output D flip-flop. Q D, C



OFDT XC3000XC4000EXC4000XXC5200XC9000

Single D flip-flop with active-high3-state active-low output enablebuffers.

O D, C,T

IFDX XC4000EXC4000X

Single input D flip-flop with clockenable.

Q D0, D1,S0

OFDX XC4000EXC4000X

Single output D flip-flop with clockenable.

Q D, C, CE

OFDTX XC4000EXC4000XXC5200

Single D flip-flop with active-hightristate and active-low outputenable buffers.

O D, C, CE,T

ILD_1 XC3000XC4000EXC4000XXC5200

Transparent input data latch withinverted gate. (Transparent High.)

Q D, G

Table C-7 Input/Output Block Components




Documents

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