Forschungszentrum Informatik, Karlsruhe Power Estimation Approach for SRAM- based FPGAs FZI Embedded System Design Group (ESDG) Karlheinz Weiss, Thorsten

Forschungszentrum Informatik, Karlsruhe

Power Estimation Approach for SRAM-based FPGAs

FZI Embedded System Design Group (ESDG)

Karlheinz Weiss, Thorsten Steckstor,

Wolfgang Rosenstiel

FZI Forschungszentrum Informatikat the University of Karlsruhe

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Overview• Introduction

– State of the art

• Estimating Power Consumption for Virtex

– technology power factor Kp(Virtex)

– benchmark test design

• SPYDER-System– SPYDER-VIRTEX-X2

– SPYDER-CORE-P2/SH3 (7709A/7729-DSP)

• Experimental Results

• Current work in progress– SPYDER-VIRTEX-X2E

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Introduction• FPGA development in the last few years

– significant increase in on-chip gate capacity

– decrease in run-times through programmable logic

• Dramatically increase of the power consumption– circuit speed (in terms of average clock frequency)

– utilized chip area (in terms of CLBs, routing length and IOs)

• Problems for embedded system design– FPGAs can consume several amperes of current

– appropriate board design for power supply is needed

– sufficient ambient conditions to carry of the heat must be provided

• Solution: – Estimation of power consumption in an early design step

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State of the Art: XC4000 architecture• PEST = PSTAT + PIO + PINT

– PSTAT : static power (few microwatts)

– PIO = PDC + PAC : IO-power

– PINT : internal power (important)

>> Kp(Virtex) ??

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Estimating Power for Virtex

PINT : measured on SPYDER-VIRTEX-X2VCore := 2.5 VfMax: constrain from the development toolNLC := 2.25 x nSlice (output development tool)TogLC : can be set to 1

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SPYDER-System

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C-API-Routines for NT 4.0

connection to CORE-tools

SPYDER-VIRTEX-X2: architecture P

CI

- S

LO

T PCI-interface

PLX-PCI9080

Xilinx-Virtex-FPGA

XCV300...XCV800

BGA 432

arbiter

CPLD

XC95144xl

Configuration-Flash

2M x 8

external FPGA configuration header(parallel port)

extension header I and II

high densitylogic analyzer connectors

86

86

32

30

I

II

configuration

power supply+ 2,5V or 1,8V / 10A

+ 3,3V / 3A

mic

roc

on

tro

lle

r

SSRAM256k x 32

or SDRAM4M x 32

SSRAM256k x 32

or SDRAM4M x 32

Memory Add-On Board

4M x 32 SDRAM or

256k x 32 SSRAM or

1M x 32 Flash

I

II

Memory Add-On Board

4M x 32 SDRAM or

256k x 32 SSRAM or

1M x 32 Flash

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Experimental Results

small middle large

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Experimental Results

Worst Case Scenarios

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86 I

86 II

86 III

86 IV Xilinx Virtex FPGA(provide up to 2 mio. gates)

XCV1000E up toXCV2000E

BGA 560

SSRAM256k x 32

or SDRAM4M x 32

SSRAM256k x 32

or SDRAM4M x 32

scaleable in size

ConfigurationSH3-7709A

core 8MB Flash

100/10BaseTethernet

LAN/WANIntra/Internet (TCP/IP)

Current work: SPYDER-VIRTEX-X3E

extension headers I to IV

high densitylogic analyzer connectors

86 I

86 II

86 III

86 IV Xilinx Virtex FPGA(provide up to 2 mio. gates)

XCV1000E up toXCV2000E

BGA 560

SSRAM256k x 32

or SDRAM4M x 32

SSRAM256k x 32

or SDRAM4M x 32

power supply+ 2,5V or 1,8V / 10A

+ 3,3V / 3A

not visible to the user back

planes

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Conclusion• Estimating power consumption in an early design step

– used the kown approach for XC4000

– extended that approach to the novel Virtex architecture

• Work was done using the SPYDER-tool set– especially SPYDER-VIRTEX-X2

– PCI-based Virtex-FPGA emulation platform

• Experimental Result

–Kp(Virtex) = 4.6 x 10-12

– about 2.5 better than XC4000XV-family• Current work: SPYDER-VIRTEX-X3E

– Intra/Internet accessible

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Picture of SPYDER-VIRTEX-X2

Further information:http://www.fzi.de/sim/spyder.html- user manual- application notes- support software download- IP-cores- all accepted papers of the ESDG

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Forschungszentrum Informatik, Karlsruhe Power Estimation Approach for SRAM- based FPGAs FZI Embedded System Design Group (ESDG) Karlheinz Weiss, Thorsten