Embed Size (px)
Citation preview
Florida State University Libraries
Electronic Theses, Treatises and Dissertations The Graduate School
2013
The Next Generation Grid-Connected PVInverters for High Penetration ApplicationsYan Zhou
Follow this and additional works at the FSU Digital Library. For more information, please contact [email protected]
THE FLORIDA STATE UNIVERSITY
COLLEGE OF ENGINEERING
THE NEXT GENERATION GRID-CONNECTED PV INVERTERS FOR HIGH
PENETRATION APPLICATIONS
By
YAN ZHOU
A Dissertation submitted to the Department of Electrical and Computer Engineering
in partial fulfillment of the requirements for the degree of
Doctor of Philosophy
Degree Awarded: Fall Semester, 2013
ii
Yan Zhou defended this dissertation on September 06, 2013.
The members of the supervisory committee were:
Hui Li
Professor Directing Dissertation
Chiang Shih
University Representative
Simon Y. Foo
Committee Member
Jim P. Zheng
Committee Member
Uwe Meyer-Baese
Committee Member
The Graduate School has verified and approved the above-named committee members, and
certifies that the dissertation has been approved in accordance with university requirements.
iii
I dedicated this to my parents Jiangao Zhou and Genmei Wu
and
my wife Hui Zhou
iv
ACKNOWLEDGMENTS
I would like to express my sincere gratitude to my advisor, Dr. Hui Li, for her support
and guidance during my Ph.D. study. She provided me an excellent research environment and
taught me how to accomplish high-quality research. The attitude toward research will benefit me
in my future career.
I would like to appreciate all my committee members, Dr. Chiang Shih, Dr. Simon Y.
Foo, Dr. Jim P. Zheng and Dr. Uwe Meyer-Baese, for their invaluable comments and advices.
I would like to thank Dr. Shanxu Duan who guided me into the field of power electronics
and helped me lay a solid foundation in this area.
I would like to thank the industry partners, Dr. Miaosen Shen from UTRC, Dr. Patrick
Chapman form SolarBridge Techniques, Mr. Bhasy Nair and Mr. Steve Colino from EPC for
their valuable discussions and help on the project.
Many thanks go to the CPAS staff and members of the research group. In particular I
would like to thank Dr. Liming Liu and Dr. Jin Shi for their guidance and friendship which have
been invaluable to my work and life.
Last but not least, I would like to thank my family and friends for their support
throughout my Ph.D. study.
v
TABLE OF CONTENTS
List of Tables ................................................................................................................................ vii List of Figures .............................................................................................................................. viii Abstract ......................................................................................................................................... xii
1. INTRODUCTION ...................................................................................................................1
1.1 Research Background ....................................................................................................1 1.1.1 Performance Improvement and Cost Reduction of Next Generation PV Inverters .........................................................................................................................1 1.1.2 Mitigation of Adverse Impacts of the Distributed PV Systems on Utility Grid .....................................................................................................................5
1.2 Research Objective and Dissertation Proposal ..............................................................8
2. PV MODULE-INTEGRATED CONVERTER BASED ON CASCADED QUASI-Z-SOURCE INVERTERS .................................................................................................................10
2.1 State-of-the-art PV Module-integrated Converter .......................................................10 2.1.1 Commercial PV MIC .......................................................................................10 2.1.2 PV MIC Based on Cascaded Multilevel Inverter ............................................12
2.2 Proposed PV MIC Based on Cascaded qZSIs .............................................................14 2.2.1 Topology Selection in Z-source Inverter Family .............................................15 2.2.2 Cascaded qZSIs with Modified Modulation Strategy ......................................17
2.3 qZSI Module Design Optimization ..............................................................................19 2.3.1 Ac Equivalent Model of the qZSI ....................................................................19 2.3.2 Power Loss Analytical Model ..........................................................................22 2.3.3 Optimal Design of the qZSI Module ...............................................................27 2.3.4 Optimal Design Example .................................................................................28
2.4 Prototype Development and Experimental Results .....................................................30 2.4.1 qZSI Prototype Development ..........................................................................30 2.4.2 Experimental Results .......................................................................................33 2.4.3 Efficiency Improvement with Synchronous Rectification ...............................36
2.5 Cost Analysis ...............................................................................................................37 2.6 Summary ......................................................................................................................40
3. ANALYSIS AND SUPPRESSION OF LEAKAGE CURRENT IN CASCADED-MULTILEVEL-INVERTER BASED PV SYSTEMS ..................................................................41
3.1 Leakage Current Analysis in CMI-based PV systems .................................................41 3.2 Proposed Leakage Current Suppression Solution 1 .....................................................45
3.2.1 Description of the Solution ..............................................................................45 3.2.2 Simplified Leakage Current Analytical Model and Filter Design Criteria ......46 3.2.3 Application Example: qZSI-based CMI with 100kHz Switching Frequency .48
3.3 Proposed Leakage Current Suppression Solution 2 .....................................................53 3.3.1 Description of the Solution ..............................................................................53 3.3.2 Simplified Leakage Current Analytical Model and Filter Design Criteria ......54
vi
3.3.3 Application Example: H-bridge-based CMI with 10kHz Switching Frequency .....................................................................................................................56
3.4 Summary ......................................................................................................................61
4. INTEGRATED AUTONOMOUS VOLTAGE REGULATION AND ISLANDING DETECTION .................................................................................................................................63
4.1 State-of-the-art Voltage Regulation and Islanding Detection Methods .......................63 4.2 Proposed PV Control System Description ...................................................................65
4.2.1 Principle of integrating VR and ID ..................................................................65 4.2.2 PV Control System with the Proposed Unified Var Controller .......................67
4.3 Voltage Controller Design Methodology.....................................................................70 4.3.1 Voltage Controller Design based on Single PV system...................................71 4.3.2 VR Interaction among Multiple Systems .........................................................74
4.4 Islanding Detection Characteristic Analysis ................................................................77 4.4.1 NDZ of the Proposed Method ..........................................................................77 4.4.2 Coordination of Multiple PV Systems in ID ...................................................79
4.5 RTDS Simulation and PHIL Experimental Verification .............................................81 4.5.1 The RTDS Simulation Platform and PHIL Testbed ........................................81 4.5.2 Overvoltage and Momentary Voltage Sag Test Cases ....................................82 4.5.3 Islanding Detection Test Case .........................................................................88
4.6 Summary ......................................................................................................................91
5. CONCLUSIONS AND FUTURE WORK ............................................................................92
5.1 Conclusions ..................................................................................................................92 5.2 Future Work .................................................................................................................93
APPENDICES ...............................................................................................................................95
A. DERIVATION OF THE RELATIONSHIP BETWEEN QPV AND VPCC ........................95
B. INFLUENCE OF THE CURRENT CONTROL LOOP ON THE VOLTAGE CONTROL LOOP .............................................................................................................................................97
REFERENCES ..............................................................................................................................99
BIOGRAPHICAL SKETCH .......................................................................................................108
vii
LIST OF TABLES
1.1 Typical module prices from 1995 to 2011. .............................................................................. 2 2.1 Specifications of the commercial MICs .................................................................................. 12 2.2 Voltage rating of the capacitors ............................................................................................. 15 2.3 Parameters and selection of the qZSI components ................................................................. 30 4.1 Parameters of a single PV system ........................................................................................... 73 4.2 The unified VAR controller parameters for the PV inverters at N844 and N890 ................... 84
viii
LIST OF FIGURES
1.1 Cumulative U.S. grid-connected PV installations from 2001 to 2010. ................................... 1
1.2 Typical structure of the cascaded multilevel inverter topology. .............................................. 2
1.3 Brief summary of the CMI in PV applications. ....................................................................... 4
1.4 Switching figure-of-merit for different power transistors ....................................................... 5
1.5 Overvoltage phenomenon under high PV penetrartion scenarios. ............................................ 6
1.6 Unintentional islanding problem............................................................................................... 8
2.1 Illustration of the PV MIC technology. .................................................................................. 11
2.2. Gird-connected PV MIC configurations based on (a) cascaded H-bridge inverters; (b) cascaded Z-source inverters. ......................................................................................................... 13
2.3. Proposed gird-connected PV MICs based on cascaded quasi-Z-source inverters. ............... 14
2.4 LC network configurations of voltage-fed Z-source inverter family (a) ZSI; (b) qZSI; and (c) qZSId............................................................................................................................................. 15
2.5 The relationship between the total required electrolytic capacitors and the PV voltage ripple for ZSI and qZSI. .......................................................................................................................... 16
2.6 Configuration of the proposed PV MICs based on cascaded qZSIs. ..................................... 17
2.7 Modulation strategies for qZSI (a) traditional method based on triangular carrier; and (b) modified method based on sawtooth carrier. ................................................................................ 18
2.8 Different operation modes of the quasi-Z-source inverter (a) active state; (b) zero state and (c) shoot-through state. ................................................................................................................. 20
2.9 The ac equivalent circuit model of the quasi-Z-source inverter. ........................................... 21
2.10 Comparison of the calculated and simulated currents through the quasi-Z-source inductors at 40V 250W input conditions. ...................................................................................................... 22
2.11 Switching sequences of the full bridge in each switching cycle for (a) buck mode and (b) boost mode. ................................................................................................................................... 24
2.12 Module efficiencies for the systems with different module numbers. ................................. 29
ix
2.13 The full bridge loss at different switching frequencies. ........................................................ 29
2.14 Picture of the qZSI module under test. ................................................................................ 31
2.15 Gate drive voltage of S2 at 45 V and 44 W input. ................................................................ 32
2.16 The high frequency power loop in the qZSI: (a) schematic and (b) PCB layout. ................ 32
2.17 The experimental waveforms of the qZSI module at 180 W under (a) 40 V input; (b) 45 V input; and (c) 50 V input. .............................................................................................................. 33
2.18 Measured qZSI module efficiency curves at 40 V, 45 V and 50 V. .................................... 34
2.19 Uncertainties of the module efficiency measurement. ......................................................... 35
2.20 Comparison of the measured and calculated efficiencies for (a) 40 V input; and (b) 45 V input. ............................................................................................................................................. 35
2.21 Comparison of the measured qZSI module efficiencies with and without synchronous rectifier at 45V input condition. .................................................................................................... 36
2.22 Comparison of the measured qZSI module efficiencies with and without synchronous rectifier at 50V input condition. .................................................................................................... 37
2.23 Widely used two-stage configuration for commercial PV MICs.......................................... 37
2.24 Topology of the MIC composed of an isolated half-bridge boost converter and a full-bridge inverter. ......................................................................................................................................... 38
2.25 Comparison of the calculated efficiencies of the qZSI modules with Si-MOSFETs and GaN devices........................................................................................................................................... 39
3.1 Basic CMI-based PV system: (a) circuit diagram and (b) equivalent circuit. ....................... 42
3.2 System equivalent circuit by replacing the phase-leg voltages with DM and CM voltage sources........................................................................................................................................... 44
3.3 The proposed leakage current suppression solution 1: (a) circuit diagram and (b) equivalent circuit. ........................................................................................................................................... 46
3.4 Simplified leakage current analytical model for the system with leakage current suppression method 1........................................................................................................................................ 48
x
3.5. System diagram of a PV system composed of four cascaded qZSIs with leakage current suppression solution 1. .................................................................................................................. 49
3.6 Design results for the PV system with leakage current suppression solution 1: (a) 1_ Hleaki
and (b) gleaki _ . ............................................................................................................................... 50
3.7 Simulation waveforms of the qZSI based PV CMI: (a) without leakage current suppression 1 and (b) with leakage current suppression solution 1. .................................................................... 51
3.8 Photograph of the two cascaded qZSI modules built in the laboratory. ................................ 52
3.9 The experimental results without leakage current suppression 1: (a) voltage across the parasitic capacitors and (b) the corresponding spectrums. ........................................................... 52
3.10 The experimental results with leakage current suppression solution 1, Cpv1=30nF and Cpv2=1nF: (a) voltage across the parasitic capacitors and (b) the corresponding spectrums. ....... 53
3.11 The proposed leakage current suppression solution 2: (a) circuit diagram and (b) equivalent circuit. ........................................................................................................................................... 54
3.12. System diagram of a PV system composed of two cascaded H-bridge inverters with leakage current suppression solution 2. ........................................................................................ 56
3.13 Design results for the PV system with leakage current suppression solution 2: (a) 1_ Hleaki
and (b) gleaki _ . ............................................................................................................................... 57
3.14 Simulation waveforms of the PV system consisted of two cascaded H-bridge inverters: (a) without leakage current suppression 2 and (b) with leakage current suppression solution 2. ...... 58
3.15 Photograph of the two cascaded H-bridge inverter modules built in the laboratory. .......... 59
3.16 The experimental results without leakage current suppression 2: (a) voltage across the parasitic capacitors and (b) the corresponding spectrums ............................................................ 60
3.17 The experimental results with leakage current suppression solution 2, Cpv1=100nF and Cpv2=10nF: (a) voltage across the parasitic capacitors and (b) the corresponding spectrums ...... 60
3.18 The measured waveform and the RMS value of 1_ dcciri . ..................................................... 61
4.1 A local PV system connected to the distribution system. ...................................................... 66
4.2 Proposed PV control system applied to multiple distributed PV systems. ............................ 68
4.3 Volts/var curve for the AVC. ................................................................................................. 69
xi
4.4 The single PV system model block diagram.......................................................................... 71
4.5 Root locus of a single PV system. ......................................................................................... 73
4.6 A distribution network with two PV systems. ....................................................................... 74
4.7 NDZ of the passive anti-islanding method and the proposed method (a) theoretical analysis according to the IEEE std. 1547 requirement; (b) simulation validation; and (c) theoretical analysis with widened protection settings and with different clearing time. ................................ 80
4.8 PHIL testbed for experimental verification under high PV penetration conditions. ............. 81
4.9 One-line diagram of the modified IEEE 34 node test feeder with high penetration PV systems. ......................................................................................................................................... 83
4.10 Overvoltage test case: RTDS simulation results of (a) node 890 PCC voltages; (b) node 890 reactive power outputs; (c) node 844 PCC voltages and (d) node 844 reactive powers outputs. . 85
4.11 Overvoltage test case: PHIL experimental waveforms of the hardware PV inverter reactive power output and PCC voltage. .................................................................................................... 85
4.12 Momentary voltage sag test case: RTDS simulation results of (a) node 844 PCC voltages; (b) node 844 reactive power outputs; (c) node 890 PCC voltages and (d) node 890 reactive power outputs. .......................................................................................................................................... 87
4.13 Momentary voltage sag test case: PHIL experimental waveforms of the hardware PV inverter reactive power output and PCC voltage. ......................................................................... 87
4.14 Islanding detection test circuit. ............................................................................................ 88
4.15 Single-PV-inverter islanding detection test when the unified var controller was disabled. 89
4.16 Single-PV-inverter islanding detection test when the unified var controller was enabled. . 89
4.17 Multiple-PV-inverter islanding detection test when the unified var controller was enabled: simulation waveforms. .................................................................................................................. 90
4.18 Multiple-PV-inverter islanding detection test when the unified var controller was enabled: PHIL experimental waveforms. .................................................................................................... 90
4.19 Multiple-PV-inverter islanding detection test when the unified var controller was disabled: PHIL experimental waveforms. .................................................................................................... 90
B.1 Root locus comparison of the complete model and simplified model. ................................. 97
xii
ABSTRACT
The increasing consumer demand and government incentives are driving the rapid growth
of renewable energy generation. In particularly, the number of distributed photovoltaic (PV)
system installations is increasing quickly. However, the high cost of the PV systems and the
potential impacts on the safe operation of utility grid could become barriers to their future
expansion. To enable the high penetration of distributed PV systems, it is necessary to bring
down the PV system cost and mitigate its adverse impacts on utility grid operation. As the
interface between the renewable sources and the utility grid, advanced power electronics
technologies will play important roles in realizing the above goals.
The transformerless cascaded multilevel inverter (CMI) is considered to be a promising
topology alternative for low-cost and high-efficiency PV systems. This research work presents a
single-phase transformerless PV system based on cascaded quasi-Z-source inverters (qZSI). In
this system, each qZSI module is connected to a single PV panel and serves as a PV module-
integrated converter (MIC). The advantages of the proposed MIC structure include low voltage
gain requirement, single-stage energy conversion, enhanced reliability and good output power
quality. The innovative structure can reduce the cost and increase the efficiency of the power
conversion stage. Furthermore, the enhancement mode gallium-nitride field effect transistors
(eGaN FETs) are employed in the qZSI module for efficiency improvement at higher switching
frequency. Optimized module design is developed based on the derived qZSI ac equivalent
model and power loss analytical model to achieve high efficiency and high power density. A
design example of qZSI module is presented for a 250 W PV panel with 25 V ~ 50 V output
voltage. The simulation and experimental results prove the validity of the analytical models. The
final module design achieves up to 98.06% efficiency with 100 kHz switching frequency. The
peak efficiency can be further improved to 98.66% with synchronous rectification.
Though the tranformerless CMI-based PV systems can achieve high performance and
low cost, the leakage current issue resulted from the parasitic capacitors between the PV panels
and the earth remains a challenging. In this research work, the leakage current paths in PV CMI
are analyzed and the unique features are discussed. Two filter-based suppression solutions are
then presented to tackle the leakage current issue in different PV CMI applications. The first
method is more suitable for the CMIs operated at high switching frequency. The second method
xiii
extends the application to the CMIs operated with lower switching frequency by bringing in
extra wire connections among the cascaded modules and the grid output. Simplified leakage
current analytical models are derived to study the suppression mechanisms and design the
suppression filters. Study cases are demonstrated for each of the solutions. The first solution is
applied to the above presented PV system based on cascaded qZSIs. The second solution is
executed in a PV system with two cascaded H-bridges where each switching device is operated
at 10 kHz. Simulation and experimental results are provided to validate the effectiveness of the
proposed solutions.
To mitigate the adverse impacts on utility grid operation associated with high penetration
level of PV systems, an autonomous unified var controller is proposed to address the system
voltage issues and unintentional islanding problems. The proposed controller features integration
of both voltage regulation (VR) and islanding detection (ID) functions in a PV inverter based on
reactive power control. Compared with the individual VR or ID methods, the function
integration exhibits several advantages in high PV penetration applications: 1) fast voltage
regulation due to the autonomous control; 2) enhanced system reliability because of the
capability to distinguish between temporary grid disturbances and islanding events; 3) negligible
non-detection zone (NDZ) and no adverse impact on system power quality for ID and 4) no
interferences among multiple PV systems during ID. As the VR and ID functions are integrated
in one controller, the controller is designed to fulfill the requirement of VR dynamic
performance and ensure small ID NDZ simultaneously. The interaction among multiple PV
systems during VR is also considered in the design procedure. The feasibility of the proposed
controller and the controller design method is validated with simulation using a real time digital
simulator (RTDS) and a power hardware-in-the-loop (PHIL) testbed.
Finally, conclusions are given and the scope of future work is discussed.
1
CHAPTER ONE
INTRODUCTION
1.1 Research Background
The grid-connected photovoltaic (PV) generation system markets are growing rapidly due
to the environment concerns and government incentives. The cumulative installation of the grid-
connected PV systems in U.S. from 2001 to 2011 is shown in Fig. 1.1 [1]. The total installed
grid-connected PV system capacity was increased to 4GW in 2011. The capacity of PV systems
installed in 2011, 1,845 MWDC, was more than ten times the capacity of PV installed in 2007.
1.1.1 Performance Improvement and Cost Reduction of Next Generation PV Inverters
Despite the fact that the U.S. PV market is developing quickly, the PV generation is still
not cost-competitive compared with the conventional forms of electricity generation. Great effort
0
1000
2000
3000
4000
5000
2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011
MW
DC
Year
Cumulative PV installations
Fig. 1.1 Cumulative U.S. grid-connected PV installations from 2001 to 2010.
2
is needed to reduce the cost of PV systems. The PV system cost can be broken down into three
parts: the PV modules, the PV inverter, installation and the remaining balance of system costs.
Currently, the average price of PV modules decreased dramatically in these years as indicated in
Table. 1.1 [2]. With evolving technologies, the goal of $1 per watt PV cell can be achieved in the
near future if the cells are manufactured at a large scale [3].
Year 1995 2000 2005 2008 2009 2010 2011
Standard module price(s): Typical (Mid-range buyers,
USD/W) $5.01 $3.79 $3.65 $3.65 $2.82 $2.36 $1.67
Best price (Large quantity buyers, USD/W)
$4.90 $2.75 $3.03 $3.25 $2.18 $1.48 $1.28
Because of the downward tendency of the PV module price, the PV inverter cost
becomes more visible in the total. Advanced power electronics technologies need to be
Table 1.1 Typical module prices from 1995 to 2011.
Fig. 1.2 Typical structure of the cascaded multilevel inverter topology.
3
developed to deliver PV power to the grid with high efficiency while reducing the system cost.
In recent years, the cascaded multilevel inverter (CMI) topology has been considered in PV
applications [4]-[6]. The typical structure of the CMI topology is shown in Fig. 1.2. This
topology features separate dc inputs, making possible the string or even panel level maximum
power point tracking. The energy harvest can be maximized in case of mismatch in the PV
panels due to panel aging, shading effect or accumulation of dust in the panel surface. The
cascaded structure also reduces the voltage gain requirement for each module, so it can achieve
single-stage energy conversion and higher equivalent output PWM frequency. In addition,
cheaper power semiconductors with lower voltage rating can be utilized in the CMI compared
with the central/string inverters.
Currently, the CMI has found its applications in both utility-scale and
residential/commercial PV systems. A review of some reported CMI-based PV systems [4], [6]-
[22] is illustrated in Fig. 1.3, where the point of common coupling (PCC) voltage and device
switching frequency information are provided. It is noticed that modified CMI with integrated
high-frequency transformer is usually utilized in large-scale PV systems [4], [6], [7]. The
transformer is necessary for insulation purpose, because the several-kV PCC voltage may impose
directly across the PV panel electrical section and its frame when there is no transformer and it
could cause hazardous dielectric breakdown [4]. Besides, the integrated transformer can isolate
the circulating leakage current paths. On the other hand, for residential/ commercial applications
with low PCC voltages, because there is no aforementioned insulation concern, transformerless
PV CMI is preferred due to the lower cost and higher efficiency. The transformerless CMI
structure can be readily accomplished by extending the number of cascaded modules. However,
removal of the transformer would result in galvanic connections among the grid and the separate
PV panels/ strings interfaced with different cascaded inverters. Due to the parasitic capacitance
between the PV panels and the earth, circulating leakage currents can flow through the panels
and grid ground, leading to increased output harmonic content, higher losses, safety and
electromagnetic interference (EMI) problems. So far, there is rarely publication dealing with the
leakage current issue in transformerless CMI-based PV systems.
4
Another trend in developing next generation PV inverters is to use advanced
semiconductor components, such as silicon carbide (SiC) and gallium nitride (GaN) devices
[23]-[26]. The high frequency operation capability of these new devices can reduce the size and
cost of the passive components in the inverters. The PV inverter efficiency can be potentially
increased due to the new devices’ better switching figure of merit, defined as the semiconductor
switch drain-source on-resistance times the gate-to-drain charge. Fig. 1.4 compares the switching
figure of merit of EPC GaN power transistors with different equivalent silicon MOSFETs [27].
From the figure, the GaN power transistors show distinctive advantage over other equivalent
rated MOSFETs. Moreover, comparing the MOSFETs of 1980 and the state-of-the-art
MOSFETs, the results show that during the past 30 years, the MOSFET switching FOM has
decreased by a factor of 40. In contrast, the GaN transistors could have a 40 times improvement
in an even smaller amount of time.
Fig. 1.3 Brief summary of the CMI in PV applications.
5
1.1.2 Mitigation of Adverse Impacts of the Distributed PV Systems on Utility Grid
Compared with the conventional forms of electricity generation, increasing penetration of
distributed PV systems introduces new integration issues concerning the safe operation of utility
grid. The U.S. Department of Energy (DOE), Electric Power Research Institute (EPRI)
Photovoltaic & Storage Integration Program, and the International Energy Agency (IEA)
Photovoltaic Power Systems Programme (PVPS) launched several programs to identify the
technical and analytical challenges of enabling high penetration levels of distributed renewable
energy technologies [28]-[30]. The studies show that the integration of large amount distributed
PV systems may affect the distribution system coordination operation, grid power quality,
unintentional islanding, and economical operation of the utility. To mitigate the adverse impacts,
evolutions are likely to be made to utility distribution network, PV system and the interface
standards. The evolutions may include advanced coordinated voltage regulation and var
Fig. 1.4 Switching figure-of-merit for different power transistors.
6
management, bulk system coordination of PV for market and bulk system control, integration of
energy storage, advanced islanding control, and adaptive protective relaying schemes. Among
these, the system voltage problem and unintentional islanding are two major impediments of
further increasing the penetration level of renewable resources.
1.1.2.1 System voltage issues. The system voltage problems associated with the
distributed PV systems include the voltage rise caused by reverse power flow, low voltage due to
the sudden loss of distributed PV systems and voltage fluctuations because of the solar
irradiation variation.
The voltage rise phenomenon happens when the PV systems produce more power than
the local loads need. The resulting reverse power flows through the distribution line and causes
negative voltage drop across the line impedance, as shown in Fig. 1.5. If the utility sending-end
voltage is set fairly high, the voltage of the node connected with clustered PV systems may be
higher than the upper limit required by the local utility operator or standards such as ANSI
C84.1.
Fig. 1.5 Overvoltage phenomenon under high PV penetrartion scenarios.
7
The false tripping of distributed PV systems can generate low voltages in the utility
network due to the sudden loss of the PV injected power. In particularly, when the penetration
level is high, the voltage may be out of the nominal range. The inverter false tripping is mainly
initiated by momentary voltage changes in the network. Momentary voltage changes are very
common in the distribution system and the reasons can be lightning, start-up of generations and
so on. The aggressive voltage and frequency protection settings of the PV inverters have been
observed to cause the improper disconnection.
Moreover, the fluctuations of solar irradiance can lead to unpredictable variations of
utility network voltages, especially in weak grids. The induced voltage fluctuations could include
very short variations as they appear close to the edge of a cloud and long fluctuations between
clouds. These voltage fluctuations may cause excessive operation of the utility voltage regulation
devices.
One way to prevent the above voltage issues is to re-plan the distribution network with
low-impedance lines or add more line regulation equipments at the node feeding clustered PV
systems. However, the utility distribution systems typically are designed for a more than 30-year
lifetime, so it is not economical to replace the distribution lines or add extra equipments. One
promising solution is to actively involve distributed PV systems in feeder voltage regulation.
1.1.2.2 Unintentional islanding issues. When the PV systems are disconnected from the
main grid by the utility breaker, the PV inverters must stop generating power immediately.
However, if the power supplied from the PV systems matches with the load consumption, as
shown in Fig. 1.6, the PV systems cannot detect the disconnection of the main grid. This
phenomenon is called unintentional islanding and it should be avoided due to the safety reasons.
Currently, the PV inverter is required to operate at unity power factor while the load
power factor is usually not equal to one, so the chance of unintentional islanding is very small.
However, under high PV penetration conditions, the PV inverter may be allowed or required to
inject reactive power to the grid. Therefore, the unintentional islanding possibility significantly
increases. Moreover, as discussed above, in order to prevent the low voltage problem in the
network, the distributed PV systems are necessary to stay connected to the distribution lines
during momentary voltage events. But this requirement is conflicted with the anti-islanding
protection settings of the PV inverter. In order to ride through the short-time grid disturbances,
loose anti-islanding voltage/frequency trip settings are recommended [31], however it increases
8
the possibility of islanding detection failure. Therefore, the challenge of the islanding detection
in high PV penetration application is to distinguish between the short-time grid disturbances and
real islanding events. Consequently, it is necessary to develop more intelligent islanding
detection algorithms to ride through the voltage disturbances without expanding the islanding
non-detection-zone [32].
1.2 Research Objective and Dissertation Proposal
As discussed above, the advanced power electronics technologies will play key roles in
next generation PV systems. The main objectives of this research work are to explore new cost-
effective and high-efficiency PV inverter topologies, and develop advanced inverter control
systems to mitigate the adverse impacts of the distributed PV systems on utility grid. In order to
achieve the goals, the dissertation will cover three main topics.
The first topic is the proposal of a cost-effective and high-efficiency PV converter based
on cascaded quasi-Z-source inverters (qZSI). As an application example, each qZSI module in
this topology will be connected to one PV panel to serve as a PV module-integrated converter
(MIC). The enhancement mode Gallium-Nitride field effect transistors (eGaN FETs) from EPC
[23] are utilized in the inverter to achieve high efficiency at high switching frequency. The
following tasks will be included:
• Proposal of a single-phase transformerless PV MIC based on cascaded qZSIs;
Fig. 1.6 Unintentional islanding problem.
9
• Development of the ac equivalent circuit model of the qZSI module for quasi-Z-
source LC network design;
• Efficiency-oriented optimization of the proposed cascaded qZSI based on the
developed power loss model;
• qZSI module prototype development according to the optimized design results;
• Experimental test and efficiency measurement of the built qZSI modules.
The second topic is targeted on addressing the leakage current issues in transformerless
PV systems based on cascaded inverters. Two filter-based suppression solutions are presented to
tackle the leakage current issue in different PV CMI applications. The following tasks will be
included:
• Analysis of the leakage current paths in PV CMI;
• Proposal of two leakage current suppression solutions;
• Development of the simplified leakage current analytical models for the PV systems
with the two suppression solutions;
• Study case demonstrations for each of the solutions with filter design example,
simulation and experimental verifications.
The third topic is the proposal of an autonomous unified var controller to address the
system voltage issues and unintentional islanding problems associated with the distributed PV
generation systems. The following tasks will be included:
• Proposal of an autonomous inverter-based control strategy that integrates fast voltage
regulation and islanding detection functions;
• Controller design considering the interaction among multiple PV systems;
• Development of a power hardware-in-the-loop (PHIL) testbed where a PV inverter
prototype is integrated with the rest of the distribution system being simulated in the
real time digital simulator (RTDS) platform;
• Experimental verifications of the proposed controller and controller design
methodology under system level in high PV penetration conditions based on the PHIL
testbed.
10
CHAPTER TWO
PV MODULE-INTEGRATED CONVERTER BASED ON
CASCADED QUASI-Z-SOURCE INVERTERS
This chapter presents a cost-effective and high-efficiency PV converter based on
cascaded quasi-Z-source inverters. As an application example, each qZSI module is connected to
one single PV panel and serves as a PV MIC. Due to the cascaded structure and qZSI topology,
the proposed MIC features low voltage gain requirement, single-stage energy conversion,
enhanced reliability and good output power quality. Furthermore, the eGaN FETs are employed
in the qZSI module for efficiency improvement at higher switching frequency. Optimized
module design is performed based on the derived qZSI ac equivalent model and power loss
analytical model to achieve high efficiency and high power density.
2.1 State-of-the-art PV Module-integrated Converter
2.1.1 Commercial PV MIC
The PV MIC technology is an important trend in next generation PV inverter
development. There are several PV MIC manufactures emerging in these years, such as
Solarbridge, Enphase, Enecsys, Direct Grid, GreenRay and Petra Solar. The two solar industry
leaders, Power-one and SMA also released their MIC products in 2011 and 2012 respectively.
The MIC is a micro-inverter which is normally attached to the reverse side of the PV module, as
shown in Fig. 2.1. It converts the power from single PV panel to the grid. Some PV panel
manufactures directly sell ac PV modules to the customers by integrating the MICs with the
panels in their manufacturing facilities. These ac PV modules make the PV system design,
installation and expansion much easier. The MIC based PV systems can harness more energy
from the PV panels and reduce the installation and balance-of-system costs. As reported in [33],
[34], the MIC based PV systems can capture up to 25% more energy per site over central and
string inverter-based systems due to the module-level maximum power point tracking (MPPT),
11
thus effectively reduces the need for PV modules. Moreover, the MIC can cut field installation
time up to 50% and minimize the training time because of its plug-and-play capability. Dc cables
can be saved if the MIC is mounted directly on the back of the PV panel and there is no need for
bypass and string diodes. The risk of electric arc and fire is reduced because there is no high
voltage dc wiring. Last but not least, each module is connected to the grid independently, so
failure of one module will not affect the operation of other modules. The failure detection
becomes easier as well.
Though the PV MIC can increase the system efficiency by preventing the losses due to
the panel mismatch and partial shading, the MIC power stage conversion efficiency is not as high
as that of the string or central inverters. The specifications of some commercial MICs are listed
in Table 2.1. The reported 96.5% peak efficiency of the commercial MICs is around 1-2% lower
than some high efficiency string inverters [33], [35]-[37]. Moreover, the price of the MICs is still
not competitive with that of the string inverters, the MIC itself costs approximately 100% more
than string inverter on a $/Watt ac basis [38], [39]. Hence the total cost of the MIC based PV
system may not decrease even with the reduced balance-of-system and installation cost.
Considering both the advantages and limitations, the MICs are currently preferred only in
Fig. 2.1 Illustration of the PV MIC technology.
12
residential application. Currently, it is believed that the MIC is cost-effective when the PV
installation capacity is below 2kW [40].
Manufacturer Model Power rating (W)
Efficiency (%) MPPT voltage
range (V)
Ac output voltage
(V)
Warranty (years) Peak CEC
SolarBridge PANTHEON
II 250 95.7 95 25-37 240 25
Enphase M215 215 96.3 96 22-36 208/240 25
Enecsys SMI-
S240W-60-UL
240 94 92 21-35/
27-45 240 20
Direct Grid DGM-S250 250 92 91 24-32 208/230 20
GreenRay SunSine 200 200 N/A* N/A* N/A* 120 20
Petra Solar SunWave 240 N/A** 93 N/A** 120 10
Power-One AURORA
MICRO-0.3 300 96.3 95.5 30-50 208/240 N/A**
SMA OK4U-100 100 94 N/A** N/A** 120 N/A**
* The SunSine 200 is an ac module including both PV panel and inverter part. The information of the inverter is not available from the datasheet. ** Data is not provided in the datasheet.
2.1.2 PV MIC Based on Cascaded Multilevel Inverter
In recent years, multilevel converter topologies have been applied in PV applications [5],
[8], [10], [20]. The cascaded H-bridge inverter, shown in Fig. 2.2 (a), can also support MIC
structure by connecting single PV panel to each H-bridge. The cascaded H-bridge structure can
reduce the voltage gain requirement for each module; and it features single-stage energy
conversion and higher equivalent output PWM frequency. Therefore, the inverter can achieve
higher system efficiency and reduce the output filter size. However, the H-bridge inverter lacks
boost function so that the inverter module must be designed with the lowest voltage of the wide-
Table 2.1 Specifications of the commercial MICs
13
range PV input. Thus high module number is required to match the grid voltage, which causes
the system more complicated and less reliable. In [41], the authors proposed a scalable cascaded
Z-source inverter (ZSI) configuration for MIC application as shown in Fig. 2.2 (b). The proposed
inverter is still a single-stage energy conversion system, but it can cope with the PV wide-range
input voltage due to the boost capability [41], [42]. The module number can be optimized
regarding the inverter efficiency. Moreover, the system reliability is highly enhanced compared
with the cascaded H-bridge inverter, because the ZSI is immune to the shoot-through faults.
(a)
(b)
Fig. 2.2. Gird-connected PV MIC configurations based on (a) cascaded H-bridge inverters; (b) cascaded Z-source inverters.
14
2.2 Proposed PV MIC Based on Cascaded qZSIs
Based on the authors’ previous work [41], this section presents a transformerless PV MIC
based on cascaded quasi-Z-source PV inverters, as shown in Fig. 2.3. The reason of using qZSI
instead of ZSI is that the required capacitance of the passive network can be largely reduced,
which will be explained in detail in Section 2.2.1. In addition, a modified modulation strategy
based on sawtooth carrier method is used to improve the system efficiency under boost operation
mode. The eGaN FETs, which have emerged as promising next generation power switches, are
applied in the inverter. The eGaN based devices have better figure of merit, which is defined as
the switch drain-source on-resistance times the gate charge, than other same-rating power
components based on silicon material [23]. So the switching loss and conduction loss of the
power switches can be reduced. But the ultra low threshold voltage and large reverse bias voltage
drop of the eGaN FETs could degrade the system performance and cause extra loss [23].
However, it will be revealed that the shoot-through capability of qZSI can overcome the issues
and guarantees high system efficiency at high switching frequency.
Fig. 2.3. Proposed gird-connected PV MICs based on cascaded quasi-Z-source inverters.
15
2.2.1 Topology Selection in Z-source Inverter Family
All the inverters of the voltage-fed Z-source inverter family have the boost and shoot-
through functions. This section compares these inverters regarding the required capacitance of
the passive network, since the major difference among the different topologies is the voltage
rating of the Z-source capacitors. The voltage-fed Z-source inverter family includes the
traditional ZSI, qZSI and qZSI with discontinuous input current (qZSId) [43]. The LC network
configurations of the three topologies are shown in Fig. 2.4. Table 2.2 shows the equations of the
capacitors’ voltages as a function of the shoot-through duty cycle shD for all the three topologies
[43].
1cV 2cV
ZSI insh
sh VD
D
21
1
−
− in
sh
sh VD
D
21
1
−
−
qZSI insh
sh VD
D
21
1
−
− in
sh
sh VD
D
21−
qZSId insh
sh VD
D
21− in
sh
sh VD
D
21−
Fig. 2.4 LC network configurations of voltage-fed Z-source inverter family (a) ZSI; (b) qZSI; and (c) qZSId.
Table 2.2 Voltage rating of the capacitors
16
In the single-phase application, electrolytic capacitors are usually required to prevent the
propagation of the double-frequency (120 Hz) power into the PV panel. The topology with less
electrolytic capacitors is preferred. It revealed in [41] that it is better to use the Z-source
capacitors to handle the double-frequency power than the input capacitors paralleled with the PV
panel. So it is assumed that all the double-frequency power will be buffered by the Z-source
capacitors. From Table 2.2, the qZSId features lower voltage rating of both capacitors compared
with the ZSI since 5.00 <≤ shD . Because the energy stored in the capacitor is proportional to the
square of the across voltage and its capacitance, the lower capacitor voltage results in higher
capacitance to buffer the same amount of energy. Particularly, when the inverter does not operate
in boost mode, that is 0=shD , 1cV and 2cV of qZSId equal to zero, so they cannot buffer any
double-frequency power. Therefore the qZSId is not appropriate for the single-phase application.
For the ZSI, both 1C and 2C use electrolytic capacitors due to the same voltage rating of them.
For the qZSI, electrolytic capacitor is only used for 1C due to its higher voltage rating than 2C .
Fig. 2.5 The relationship between the total required electrolytic capacitors and the PV voltage ripple for ZSI and qZSI.
17
Fig. 2.5 shows the relationship between the total required electrolytic capacitors and the
PV input voltage ripple for both ZSI and qZSI. The curve is obtained based on the ac equivalent
models of ZSI and qZSI. The derivation of ZSI ac equivalent model can be found in [41] and the
one of qZSI will be given in Section III. It is evident that the qZSI requires less electrolytic
capacitors. For example, when the PV voltage ripple is designed to be 5%, the required
capacitance of electrolytic capacitors for qZSI is 30% less than ZSI. Therefore, the qZSI is
selected.
2.2.2 Cascaded qZSIs with Modified Modulation Strategy
The configuration of the grid-connected PV inverter based on cascaded qZSI modules is
presented in Fig. 2.6. Each qZSI module is installed on the backside of a PV panel. The eGaN
FETs are applied as the power switches. The parameters of the quasi-Z-source network, inverter
switching frequency, and cascaded module number will be obtained through an optimization
procedure given in Section III.
Fig. 2.6 Configuration of the proposed PV MICs based on cascaded qZSIs.
18
(a) (b)
The modulation of the qZSI is different from the H-bridge inverter because of the shoot-
through state. The way of adding the shoot-through state influences the quasi-Z-source network
design and the system efficiency. Fig. 2.7 (a) shows the traditional PWM modulation strategy for
the single-phase qZSI module [42]. The two phase legs of the full bridge are modulated with
�180 opposed reference waveforms, m and ,m , to generate three-level voltage output. Two
straight lines *pV and *
nV are used to control the shoot through duty ratio. When the triangular
carrier is greater than *pV or the carrier is smaller than *
nV , 41 SS − turn on simultaneously for
shoot-through. It is noticed that each switch needs to switch on and off twice per carrier cycle,
because the shoot-through period is distributed into two parts in each carrier cycle, as shown in
the figure. A modified PWM modulation strategy for the single-phase qZSI is applied here. The
principle of generating the gate signals is the same with the traditional method, but the triangular
carrier is replaced with a sawtooth carrier. The gate signals for the switches are shown in Fig. 2.7
(b). Compared with the triangular carrier based method, the shoot-through period of the modified
method is merged into one part. Hence, each switch turns on and off only once per carrier cycle,
which results in lower switching loss and improved system efficiency during boost operation.
One disadvantage of the sawtooth carrier method is that the current ripples on the inductors will
be doubled because of the merged shoot-through period, the inductor size is therefore increased
Fig. 2.7 Modulation strategies for qZSI (a) traditional method based on triangular carrier; and (b) modified method based on sawtooth carrier.
19
compared to that of the triangular carrier based method in order to keep the same inductor
current ripple. However, since the switching frequency is 100 kHz in the final design, so the
inductor size is not large even with the sawtooth carrier method.
2.3 qZSI Module Design Optimization
In order to achieve high performance of the proposed inverter, the design of a qZSI
module needs to be optimized first. Therefore, the ac equivalent model of a qZSI is derived to
help obtain the current and voltage information of the passive components and active switches.
The power loss analytical model is then developed to evaluate the system efficiency. Based on
the two analytical models, the qZSI module is optimized to achieve high system efficiency and
high power density. The proposed design method can provide the optimal number of cascaded
modules, the inverter switching frequency and the quasi-Z-source network parameters for
different selected PV panel.
2.3.1 Ac Equivalent Model of the qZSI
In order to design the quasi-Z-source network and analyze the power loss, the voltage and
current of the capacitors, inductors and switching devices need to be derived. In single-phase
application, the dc and ac (120 Hz) component of these variables are essential for the theoretical
analysis. Calculation of the dc-component can be found in [42], [43], while the ac-component
calculation is seldom mentioned. In this section, an ac equivalent model of the qZSI is derived.
The qZSI has three different operation states, namely active state, zero state and shoot-
through state. In Fig. 2.6, when 1S , 4S are on or 2S , 3S are on, the qZSI operates in active state;
when 1S , 3S are on or 2S , 4S are on, the qZSI operates in zero state; when 1S - 4S are all on, the
qZSI operates in shoot-through state. The equivalent circuits of the qZSI module during different
modes are given in Fig. 2.8, where the PV panel is treated as a constant current source PVI .
20
The average model of the qZSI over switching frequency is obtained in (2.1) by
integrating the subintervals of the three states.
−=
⋅−⋅−⋅=
⋅−⋅−⋅=
⋅+⋅−=
+−=
1
11
22
2
21
11
1
11
22
2
21
11
1
LPVcin
in
ags
shL
sL
c
ags
shL
sL
c
s
shc
sc
L
s
shc
scin
L
iIdt
vdC
diT
Ti
T
Ti
dt
vdC
diT
Ti
T
Ti
dt
vdC
T
Tv
T
Tv
dt
idL
T
Tv
T
Tvv
dt
idL
(2.1)
The variables with in (2.1) represent average values over the switching frequency; sT
is the switching period; 1T and shT are the non-shoot-through and shoot-through time intervals in
one switching cycle; the grid current is defined as ( )tIi gg ωsin= ; the inverter duty cycle is
( )tMda ωsin= . The non-shoot-through state is the sum of active and zero states. The state-space
equation (2.1) contains both dc and low-frequency ac components. The ac equivalent model can
be extracted from (2.1) by removing the dc components, as given in (2.2).
Fig. 2.8 Different operation modes of the quasi-Z-source inverter (a) active state; (b) zero state and (c) shoot-through state.
21
( )
( )
−=
+−=
+−=
+−=
+−=
1
1122
2
2111
1
1122
2
2111
1
~~
2cos2
1~~~
2cos2
1~~~
~~~
~~~~
Lcin
in
gshLLc
gshLLc
shccL
shccinL
idt
vdC
tMIDiDidt
vdC
tMIDiDidt
vdC
DvDvdt
idL
DvDvvdt
idL
ω
ω (2.2)
The variables with ~ in (2.2) denote the low-frequency ac variables; sTTD 11 = ,
sshsh TTD = . In steady state, 1D and shD are constants. The low-frequency ac ripple in PVI is
neglected because it is much smaller than the ac ripple from the load. An ac equivalent model of
the qZSI, given in Fig. 2.9, can be developed according to (2.2) and Fig. 2.8. As seen from the
model, the double-frequency power source is represented by two independent current sources in
the circuit. The equation set (2.3) can be established based on the model through the Kirchhoff’s
current law (KCL) and Kirchhoff’s voltage law (KVL). '~inv , '
1~
cv , '2
~cv , '
1~Li and '
2~Li are intermediate
variables and their relationships with the original values are given in Fig. 2.9. The analytical
expressions of the double-frequency voltage ripple on the capacitors and the current ripple on the
inductors can be solved through (2.3). By adding the ripple value on the dc-component, the final
expressions for inv , 1cv , 2cv , 1Li , and 2Li can be obtained. The above information is
essential for the quasi-Z-source network design and system efficiency evaluation.
inCD21
211 DL
21
2'2
~ DDv shc ⋅
1C
'2
~Lsh iD
( )tMIg ω2cos2
1
212 shDDL ⋅
31
2
2D
DC sh
31
2'1
~
D
Di shL
( )tMID
Dg
sh ω2cos2
121
⋅1
'~
~D
vv in
in =
11'1
~~LL iDi = 12
'2
~~DDii shLL ⋅=
sh
ccD
Dvv 1
2'2
~~ =1
'1
~~cc vv =
Fig. 2.9 The ac equivalent circuit model of the quasi-Z-source inverter.
22
( ) ( )
( )
+=
−+=
−+=
−−+=
−=
'22
12'2
'1
21
2'2
'12
1
1'1
'
21
31
2'1
'23
1
2
2'2
'2
'11
'1
'1
'21
~2~~
~~2~~
2cos2
1~~2~
2cos2
1~1~2
~
~~2
c
sh
Lc
shccLin
shg
shLc
shL
gLshcL
Linin
vD
DLiv
D
Dvv
D
Liv
D
DtMI
D
Div
D
DCi
tMIiDvCi
ivCD
ω
ω
ωω
ωω
ω
(2.3)
Fig. 2.10 compares the calculated values of 1Li and 2Li with the simulation results of
the designed system at 40 V, 250 W input conditions. The consistence between the calculation
and simulation results verifies the ac equivalent model.
2.3.2 Power Loss Analytical Model
The power loss analytical model can be divided into two parts, the loss in the power
semiconductor devices and the loss in the passive components.
Fig. 2.10 Comparison of the calculated and simulated currents through the quasi-Z-source inductors at 40V 250W input conditions.
23
2.3.2.1 Loss in the power semiconductor devices. a) Loss of the quasi-Z-source diode
There are four eGaN FETs and one diode in each qZSI module. The main loss of the
diode is its conduction loss, because the loss due to the reverse bias leakage current and junction
capacitance is relatively small. The root-mean-square (RMS) current through the diode equals to
the PV current PVI , so the conduction loss of the input diode can be calculated by
PVFDdiode IVP ⋅= (2.4)
where FDV is the forward voltage drop of the diode and its value depends on the current through
the diode.
b) Conduction loss of the eGaN FETs
Since the full bridge outputs a 60 Hz sinusoidal voltage, the loss calculation of the four
eGaN FETs cannot be completed based on one operation point. Instead, the energy loss in the
switches during each switching cycle will be accumulated for one output voltage cycle, 16.67
ms. Then the power loss is calculated by dividing the total energy loss by 16.67 ms.
The current distribution in the full bridge varies in different operation states. At active
and zero states, there are always two switches conducting the load current gi . While during
shoot-through state, four switches conduct current together. The current through two of the
switches equals to 2
21 gLL iii −+ and the current of the other two switches is
2
21 gLL iii ++.
When the PV voltage is higher than the grid voltage amplitude, the qZSI operates in buck
mode without shoot-through state, so the full-bridge conduction loss equals to
dttiRP gdsoncond ∫=ωπ
πω
2
0
2 )( (2.5)
where the drain-source on-state resistance dsonR of all the eGaN FETs is assumed to be the same.
When the PV voltage is lower than the grid voltage amplitude, the inverter operates in
boost mode with shoot-through state. The conduction loss can be calculated by
24
( )
( ) ( ) ( )
( ) ( ) ( )dt
tititi
tititi
RD
dttiRD
P
gLL
gLL
dsonsh
gdsoncond ∫∫
+++
−+
+=ωπωπ
πω
πω
2
02
21
2
21
2
0
21
2
2 (2.6)
c) Switching loss of the eGaN FETs
Switch Period
S1 S2 S3 S4 State
t0-t1 on off on off Zero
t1-t2 on off off
(diode) on Active
t2-t3 off on
(diode) off on Zero
t3-t4 on off
(diode) on
(diode) off Zero
Switching events
(on/off) 2 2 2 2
(a)
Switch Period
S1 S2 S3 S4 State
t0-t1 on on on on Shoot-through
t1-t2 on off on off Zero
t2-t3 on off off
(diode) on Active
t3-t4 off on
(diode) off on Zero
t4-t5 on on on on Shoot-through
Switching events
(on/off) 2 2 2 2
(b)
For the sawtooth carrier based modulation method, the switching sequences of the full
bridge in each switching cycle for both buck and boost operation is shown in Fig. 2.11. There are
four turn-on and four turn-off events per switching cycle for both two operation modes. In order
to simply the analysis, it is assumed that the gate signals of the upper switch and lower switch
have a dead time between them. Under this condition, two turn-on and two turn-off events will
be soft switching due to the body-diode conduction when the qZSI operates in buck mode. The
Fig. 2.11 Switching sequences of the full bridge in each switching cycle for (a) buck mode and (b) boost mode.
25
soft-switching events are pointed out in the figure with “diode” followed after the “on/off”. The
marked soft-switching events in the figure are for the positive output cycle. In negative output
cycle, the soft switching devices are different, but the number of soft switching events does not
change. In boost operation mode, one turn-on and one turn-off events will be soft switching.
The hard switching turn-on and turn-off energy loss can be calculated by (2.7) and (2.8)
[44].
( ) ( ) ( ) ( ) ( )[ ]tttttItVtE fvriddsonsw +⋅=2
1_ (2.7)
( ) ( ) ( ) ( ) ( )[ ]tttttItVtE firvddsoffsw +⋅=2
1_ (2.8)
where rit is the current rise time and fvt is the voltage fall time during turn-on process; rvt is the
voltage rise time and fit is the current fall time during turn-off process; Calculation of these time
periods can refer to [44]. dsV and dI are the voltage and current stress on the device respectively.
dsV equals to the dc-link voltage across the full-bridge. dI equals to gi during the
transients between active state and zero state; and it equals to 2
21 gLL iii −+ or
2
21 gLL iii ++
during the transients between zero state and shoot-through state.
The soft switching turn-on and turn-off energy loss can be calculated in (2.9) and (2.10).
( ) ( ) ( ) ( ) ( ) ( ) ( ) deadtimedFsfvddsondF
sridFonsoft ttIVtttIRtIV
tttIVtE ++
+=2
1.1
2
1_ (2.9)
( ) ( ) ( ) ( ) ( ) ( ) ( ) deadtimedFsrvddsondF
sfidFoffsoft ttIVtttIRtIV
tttIVtE ++
+=2
1.1
2
1_ (2.10)
where FV is the device source-drain forward voltage; deadtimet is the dead time between the gate
signals of the upper and lower switches; srit is the current rise time and sfvt is the voltage fall
time during soft switching turn-on process, srvt is the voltage rise time and sfit is the current fall
time during soft switching turn-off process. Calculation of srit , sfvt , srvt and sfit can also refer to
[44].
According to Fig. 2.11 and (2.7)-(2.10), the total switching loss of the full bridge during
buck operation mode can be obtained in (2.11) based on the above analysis.
26
( ) ( )( ) ( ) dt
tEtE
tEtEP
gdgd
gdgd
iIoffsoftiIonsoft
iIoffswiIonsw
sw ∫
++
+=
==
==ωπ
πω
2
0 __
__
||
||2
2 (2.11)
During boost operation, the total switching loss of the full bridge equals to
( ) ( ) ( )
( ) ( )
( ) ( ) ( )
dt
tEtEtE
tEtE
tEtEtE
P
gdgdgLL
d
gLL
d
gLL
d
gLL
d
gdgd
iIoffsoftiIonsoftiiiI
offsw
iiiI
offswiiiI
onsw
iiiI
onswiIoffswiIonsw
sw ∫
+++
++
++
=
==++=
−+=
++=
−+=
==
ωπ
πω
2
0
__
2
_
2
_
2
_
2
___
|||
||
|||
2
21
2121
21
(2.12)
2.3.2.2 Loss in passive components. a) Quasi-Z-source inductors and output filter
inductor.
The inductor power loss is composed of the core loss and winding loss. In the quasi-Z-
source network, the current through the inductors contains dc, double-frequency and high
frequency ac components. The output filter inductor contains only 60 Hz and high frequency ac
components. The dc and low-frequency ac components mainly cause the winding loss. The high
frequency ac current is related to the core loss.
The inductor winding loss can be calculated as
( )∫=ωπ
πω
2
0
2
2dttiRP LLcopper (2.13)
where LR equals to dc resistance of the inductor’s copper winding; Li equals to switching-
frequency averaged current through the inductor.
The inductor core loss equals to
tnac
mswcore WBkfP = (2.14)
where swf is the inductor current ripple frequency; acB is the high frequency ac flux density; tW
is the weight of the core; the coefficients k , m and n for different core materials can be found
in [45].
b) Quasi-Z-source capacitors and input capacitor
The dielectric loss in the capacitors contains the double-frequency and high frequency ac
components. For 1C , the double-frequency loss can be calculated by
27
( )∫=ωπ
πω
2
0
21_1
~
2dttiRP cesrdLFc (2.15)
where esrdR is the equivalent series resistance (ESR) of 1C at 120 Hz. The information of 1~ci has
already been obtained in section III. A.
The high-frequency loss of 1C equals to
( ) ( )[ ]∫ −=ωπ
πω
2
0
2
11_1~
2dttitiRP ccesrhHFc (2.16)
where esrhR is the equivalent series resistance (ESR) of 1C at selected switching frequency. The
value of 1ci equals to
( )( )( ) ( )( )
−−
−=
statethroughshootduringti
stateactiveduringtiti
statezeroduringti
ti
L
gL
L
c
,
,
,
2
1
1
1 (2.17)
The dielectric loss in 2C and inC can be calculated similar to 1C .
2.3.3 Optimal Design of the qZSI Module
2.3.3.1 Quasi-Z-source network design. The quasi-Z-source inductors are designed to
limit the high-frequency ripple to %ir of the maximum inductor current during shoot-through
state. The voltages across 1L and 2L both equal to ( )shin DDDV −11 in shoot through state. Thus
1L and 2L can be calculated by (2.18) and (2.19) respectively.
( ) max11
11
% Lish
shin
IrDD
TDVL
⋅⋅−= (2.18)
( ) max21
12
% Lish
shin
IrDD
TDVL
⋅⋅−= (2.19)
where max1LI and max2LI are the maximum value of 1Li and 2Li .
As discussed above, 1C is used to buffer the double-frequency ac power. The relationship
between the capacitance of 1C and the PV voltage ripple can be calculated according to (2.3). An
example was shown in Fig. 2.5. 1C can be selected according to the curve.
28
2C is designed to limit the high-frequency voltage ripple to %vr of the maximum value
of 2cv , max2cV . The current through 2C during the shoot-through period equals to 1LI .
Therefore, 2C is calculated
max212
% cv
shL
Vr
TIC
⋅= (2.20)
2.3.3.2 Optimized cascaded qZSI module number and switching frequency. The
number of cascaded modules, N , determines the output voltage rating of each qZSI module
since the total output voltage amplitude is fixed and is close to the grid voltage amplitude. N
also decides the total inverter output current, because the power rating of each module is fixed.
The output voltage and current of the qZSI impact the module efficiencies. Lower cascaded
module number makes the module output voltage amplitude bigger, so the shoot-through time
will be longer. The dc-link voltage of the full bridge will be boosted to a higher level which may
lead to more switching loss. Higher cascaded module number increases the inverter output
current. Since the modules are connected in series, the current flowing through the devices also
increases. So the switching loss and conduction loss of the full bridge could also increase. And
the loss of the output filter inductor will raise. According to the above analysis, an optimal value
of N exists, which can lead to higher efficiencies than other values of N .
Higher switching frequency can reduce the size of 1L , 2L and 2C in the quasi-Z-source
network, but it increases the switching loss of the full bridge. Below the critical frequency, the
switching loss of the full bridge is lower than the conduction loss and the system efficiency is not
a strong function of switching frequency. However, the quasi-Z-source network size will be
large. Above the critical frequency, the switching loss starts to dominate the full bridge loss. The
qZSI efficiency will decrease rapidly with increased frequency. As a trade-off between the
module efficiency and power density, an optimized switching frequency will be chosen to make
the full bridge switching loss and conduction loss close to each other.
2.3.4 Optimal Design Example
A design example of qZSI module for a 250 W PV panel with 25 V ~ 50 V output
voltage is illustrated in this section. The inverter is connected to the 120 Vrms utility grid. The
29
cascaded module number is selected first. Based on the derived ac equivalent model and power
loss analytic model, the module efficiencies with different N can be obtained in Fig. 2.12. The
comparison is made at 75% of module rated power rating and 100 kHz switching frequency. The
reason of choosing 75% power rating is that it weights 53% when rating the California Energy
Commission (CEC) average efficiency. It is seen that 4=N is the optimal cascaded module
number with respect to the efficiencies and it is chosen in the design. The switching frequency is
selected by comparing the full bridge switching loss and conduction loss at different switching
frequencies in Fig. 2.13. The comparison is also made at 75% of module rated power rating. 100
kHz is finally chosen in the design because at this frequency the switching loss is close to the
conduction loss. Thus, high efficiency and high power density can be achieved for the qZSI
module.
Fig. 2.12 Module efficiencies for the systems with different module numbers.
Fig. 2.13 The full bridge loss at different switching frequencies.
With N and switching frequency selected, the quasi-Z-source network parameters can be
given according to (2.18)-(2.20) and Fig. 2.5. The %ir of both 1L and 2L is designed to be 20%
and %vr of 2C is designed to be 1%. The parameters of the module components are shown in
Table 2.3. 1C is selected to make the PV voltage ripple smaller than 5%. Electrolytic capacitors
are needed because of the large capacitance of 1C . However, the electrolytic capacitors have
30
high ESR at high frequency, so in the final design ceramic capacitors are paralleled to provide
path for the high-frequency current. The actual parameters of the components are slightly
different from the designed values depending on the available commercial devices.
Component Designed
parameter Actual device selection Specifications
S1-S4 N/A eGaN FET EPC2001 Vds=100V,
Id=25A
C1 6500uF
Nichicon
UVR1J222MHD×4
TDK C5750X7S2A156M×8
C=2200uF,
Vc=63V
C=15uF,
Vc=100V
C2 175uF TDK
CKG57NX5R1H226M×9 C=22uF, Vc=50V
L1 30uH TDK PC47RM14Z-12 core 39uH
L2 21uH TDK PC47RM14Z-12 core 39uH
2.4 Prototype Development and Experimental Results
2.4.1 qZSI Prototype Development
The 250 W qZSI module prototype was built based on the optimized design, as shown in
Fig. 2.14. The input voltage of this module is from 25 V to 50 V. It is constructed on a four layer
printed circuit board (PCB), integrating the quasi-Z-source network, the full bridge, the driver
circuit and sensors.
Table 2.3 Parameters and selection of the qZSI components
31
The design of the eGaN FET drive circuit needs to consider the device’s ultra low
threshold voltage and absolute maximum gate voltage rating. The minimum threshold voltage
can be as low as 0.7 V and the maximum gate voltage rating is 6 V for the selected EPC2001
eGaN FET. Considering the qZSI devices immunity to shoot-through, the ultra low threshold
voltage which may cause unintended miller turn-on will not be the concern. However, the
overshoot of the gate voltage during turn-on process needs to be limited to guarantee the gate
voltage not to exceed 6 V. In order to minimize the gate overshoot, the stray inductance in the
driver circuit loop should be decreased. Detailed guidalines of decreasing the stray inductance in
the driver circuit loop can be referred to [25], [46], [47]. The LM5113 half-bridge driver in a
LLP package is used to drive the eGaN FETs [48]. The turn-off resistor is 0 � to make fast turn-
off process, while the turn-on resistor is chosen as 5.1 � to further limit the possible gate
overshoot. Fig. 2.15 shows the gate drive voltage of 2S at 45 V and 45 W input condition. There
is no overshoot on the gate voltage during the turn-on transient. At higher power ratings, no
overshoot is observed either. Overshoot is observed on 2S gate voltage, when 2S is on and 1S
is switched to on-state for shoot-through state. The large dtdi / in the power loop couples into
the gate loop through the common source inductance. However, the overshoot is always below 6
V.
Fig. 2.14 Picture of the qZSI module under test.
32
(a) (b)
For the qZSI, there is no dc capacitors right across the full bridge dc-link. The length of
the high frequency power loop, highlighted in Fig. 2.16 (a), is longer than that of the traditional
H-bridge with decoupling capacitors placed right across the dc link. Because of the longer high
��� of �� (2V/div)
100 ns/div
Fig. 2.15 Gate drive voltage of S2 at 45 V and 44 W input.
Fig. 2.16 The high frequency power loop in the qZSI: (a) schematic and (b) PCB layout.
33
frequency loop, the overshoot on the devices will be larger. One way to limit the overshoot is
through layout optimization. Another effective solution is to use a dc rail clamp circuit [49]. In
this work, the layout optimization is performed. In order to reduce the loop stray inductance, 1L ,
2L , 1C , 2C , 1D and the full bridge are placed close to each other. In the layout design, bus 1~4 in
Fig. 2.16 (a) are formed using copper polygon in different layers and there is overlap between
each other, so the spatial area looped by the high frequency power loop will be small. Therefore,
the loop stray inductance can be reduced. The PCB layout of the high frequency power loop is
shown in Fig. 2.16 (b).
2.4.2 Experimental Results
The 250 W qZSI module was tested at 40 V, 45 V and 50 V input under different power
conditions. The module output voltage amplitude is 42 V as N is selected to be 4. The emphasis
of this work is the module efficiency, so the control of qZSI was open-loop and the resistance
load was used. Fig. 2.17 shows the qZSI input and output waveforms under the three input
voltage levels at 180 W. When the input voltage VVPV 45= and VVPV 50= , the qZSI operated in
buck mode; when VVPV 40= , the qZSI operated in boost mode.
(a)
(b)
(c)
The measured efficiency curves of the module at three input voltage levels are provided
in Fig. 2.18. The module efficiency was measured using the digital power analyzer, Yokogawa
Fig. 2.17 The experimental waveforms of the qZSI module at 180 W under (a) 40 V input; (b) 45 V input; and (c) 50 V input.
34
WT3000. The results show that when the input power was higher than 50 W, the system
efficiencies were above 97%. The peak efficiency 98.06% was achieved at 45 V, 140 W input
condition. The uncertainties of the efficiency measurement under different conditions are given
in Fig. 2.19. The efficiency uncertainty was calculated by combining the uncertainties of input dc
power measurement and output ac power measurement [50]. The uncertainties of dc and ac
power measurement can be obtained using the Power Analyzer Accuracy and Basic Uncertainty
Calculator provided by Yokogawa [51]. During the measurement, the auto voltage/current range
was enabled. The measurement range will be increased when the measured value exceeds 110%
of the present measurement range.
In the test, a 26 ns dead time was applied between the upper and lower switch in one
phase leg. Because of the qZSI’s shoot-through capability, the small dead time did not cause
extra power loss. On the contrary, it can increase the system efficiencies because the source-
drain forward voltage of the eGaN FET can be a volt higher than comparable silicon MOSFETs
[46]. When the dead time was adjusted to 65 ns, the peak efficiency at 45 V, 140 W input
condition dropped to 97.88%.
Fig. 2.18 Measured qZSI module efficiency curves at 40 V, 45 V and 50 V.
35
(a)
(b)
In order to prove the validity of power loss model derived in section III, the measured
efficiency is compared with that of calculated result. Since the loss calculation equations of boost
and buck operation mode are different, a 40 V input case and a 45 V input case are selected
because they represent a typical boost and buck operation mode, respectively. The measured
efficiency of 40 V input and 45 V input are compared with their calculated results in Fig. 2.20.
Fig. 2.19 Uncertainties of the module efficiency measurement.
Fig. 2.20 Comparison of the measured and calculated efficiencies for (a) 40 V input; and (b) 45 V input.
36
The consistence between the measured and calculated efficiencies verified the derived ac
equivalent model and power loss analytical model of the qZSI. It also proved the effectiveness of
the optimization procedure.
2.4.3 Efficiency Improvement with Synchronous Rectification
Because the input voltage of the qZSI is low, the loss on the diode is relatively large.
When the input power is higher than 100W, the diode loss can share around 50% of the total
loss. If the diode is replaced with a synchronous rectifier, the system efficiencies can be further
improved.
Fig. 2.21 shows the measured qZSI module efficiencies at 45V input with the diode
replaced by eGaN FET EPC 2001. Compared with the module without the synchronous rectifier,
the efficiencies were improved by around 0.5% over the entire power range. The peak efficiency
was increased from 98.06% to 98.66%. Fig. 2.22 shows the measured qZSI module efficiencies
at 50V input with and without synchronous rectifier. Similarly, the module efficiencies were
improved by around 0.5% over the entire power range. The peak efficiency was increased from
98.03% to 98.53%.
Fig. 2.21 Comparison of the measured qZSI module efficiencies with and without synchronous rectifier at 45V input condition.
37
2.5 Cost Analysis
In this section, we compare the cost of the proposed system with the cost of commercial
PV MICs. Fig. 2.23 shows a widely used two-stage configuration PV MIC for commercial
products. The front-end dc-dc converter with a high-frequency transformer boosts the low PV dc
voltage to a grid-compatible voltage level. It can be flyback converter [52]-[54], isolated full/half
bridge boost converter [39], [55], two-inductor boost converter [56], [57] and resonant converter
[58], [59]. The advantages of this configuration is that the power density and efficiency can be
significantly improved comparing with the configuration with line frequency transformer. The
high-frequency transformer can also isolate the possible leakage current paths.
Fig. 2.22 Comparison of the measured qZSI module efficiencies with and without synchronous rectifier at 50V input condition.
Fig.2.23 Widely used two-stage configuration for commercial PV MICs.
38
However, the complex two-stage structure also contributes to the higher cost of the MIC.
As an example, Fig. 2.24 shows a MIC composed of an isolated half-bridge boost converter and
a full-bridge inverter [55]. This topology is reported to use minimal devices for the configuration
shown in Fig. 2.23. The dc-dc converter mainly consists of two low-voltage high-current
MOSFETs, two high-voltage diodes, one input inductor, a high-turns-ratio isolation transformer
and four high-frequency capacitors. The isolation transformer usually requires customer design,
so the cost is relatively high. The expensive SiC diodes are needed for the high-voltage diodes to
eliminate the reverse recovery loss. The inverter includes four high-voltage MOSFETs and
output filters. All these components, including the MOSFET drivers, could cost around $30. The
prices of the components are all referred to the distributor website lowest price.
Due to the cascaded structure, the proposed system can get rid of the front-end dc-dc
converter, and retain the good features of the MIC. The component cost of the qZSI prototype
shown in Fig. 2.14 is $25.683, which is lower than the cost of the two-stage MIC. It needs to be
pointed out the price of the GaN devices is still very high. The GaN devices used in our
prototype cost $12. The cost saving will be more significant when the GaN device price drops
down.
Due to the high price of the GaN devices in this time period, we also consider to use
conventional Si-MOSFETs in the proposed topology. The 100V 16m� OptiMOS
Fig.2.24 Topology of the MIC composed of an isolated half-bridge boost converter and a full-bridge inverter.
39
(BSZ160N10NS3) from Infineon are considered to substitute the GaN devices. With the
switching frequency kept at 100kHz, the parameters of the quasi-Z-source passive components
therefore remain the same. The component cost of the qZSI with Si-MOSFETs is decreased to
$15.058, which is nearly half of the commercial two-stage MIC.
It is important to mention that it is actually impractical to operate Si-MOSFET based H-
bridge inverter at high switching frequency. This is due to the high reverse recovery charge of
the Si-MOSFET body diode. High reverse recovery current and huge related loss may damage
the devices when the inverter is operated at high switching frequency. However, the qZSI
provides an advantage that can operate Si-MOSFET based inverter at high switching frequency
without causing huge reverse recovery related loss. The reverse recovery current of the MOSFET
body diode is lessened by the quasi-Z-source network. Specifically, the current through the
device is limited to the sum of the two inductor currents in the quasi-Z-source network.
Therefore, it is possible to design a Si-MOSFET based qZSI module operated at 100kHz.
Taking the reverse recovery problem into account, the efficiency of the qZSI module with
Si-MOSFETs is calculated as in Fig. 2.25. Compared with the module with GaN devices, the Si-
MOSFET based module has decreased efficiency due to the higher conduction and switching
loss. However, it can still achieve 97.41% theoretical peak efficiency.
Fig. 2.25 Comparison of the calculated efficiencies of the qZSI modules with Si-MOSFETs and GaN devices
40
2.6 Summary
In this chapter, a cost-effective and high performance PV MIC based on cascaded qZSI
modules was presented. The cascaded structure reduced the voltage gain requirement of the
MIC. The system reliability was also enhanced due to the qZSI shoot-through capability.
Therefore, it is suitable for the application of EPC eGaN FETs which have ultra low threshold
voltage and large reverse bias voltage drop. Small dead time can be selected to increase the
system efficiencies without any damage. In addition, a modified modulation strategy for the
qZSI was proposed to increase the inverter efficiency during boost operation. The module
optimized design can be derived based on the derived qZSI ac equivalent model and power loss
analytical model to achieve high efficiency and high power density. The two analytical models
were verified by simulation and experimental results.
A design example of qZSI module for a 250 W PV panel with 25 V ~ 50 V output
voltage was presented. The design results provided the optimal cascaded module number,
switching frequency and quasi-Z-source network parameters. The final prototype design
achieved a peak efficiency 98.06% at 45 V and 140 W input. When the input power is higher
than 50 W, the efficiency curve was flat and above 97%. The system efficiency can be further
improved if the diode is replaced with SR. The measured peak efficiency was increased to
98.66% at 45 V and 140 W input condition.
Compared with the commercial PV MICs, the MIC with proposed structure has lower
cost. When the high-price eGaN devices are substituted with conventional Si-MOSFETs, the
component cost can be reduced to half of the commercial PV MICs. The qZSI provides another
advantage that can operate Si-MOSFET based inverter at high switching frequency without
causing huge reverse recovery related loss. The module can still achieve 97.41% theoretical peak
efficiency.
41
CHAPTER THREE
ANALYSIS AND SUPPRESSION OF LEAKAGE CURRENT IN
CASCADED-MULTILEVEL-INVERTER BASED PV SYSTEMS
As discussed in Chapter one, the PV CMI with transformerless structure is preferred in
residential/commercial applications due to the lower cost and higher efficiency. However, due to
the parasitic capacitance between the PV panels and the earth, circulating leakage currents can
flow through the panels and grid ground, leading to increased output harmonic content, higher
losses, safety and EMI problems. So far, there is rarely publication dealing with the leakage
current issue in transformerless CMI-based PV systems.
This chapter firstly identifies the leakage current paths in PV CMI. The differences
between the transformerless CMI and string inverter concerning the leakage current behaviors
are also discussed. Then two leakage current suppression solutions are presented for the PV CMI
by adding properly located and designed passive filters in the inverter. The first method is more
suitable for the CMIs operated at high switching frequency. The second method extends the
application to the CMIs operated with lower switching frequency by bringing in extra wire
connections among the cascaded modules and the grid output. Simplified leakage current
analytical models for the PV systems with the two suppression solutions are developed
respectively to demonstrate the principles and introduce the filter design criteria. Finally the
proposed first solution is applied in the PV system based on cascaded qZSIs, which is presented
in Chapter two. The second solution is executed in a PV system with two cascaded H-bridges
where each switching device is operated at 10kHz.
3.1 Leakage Current Analysis in CMI-based PV Systems
As summarized in Fig.1.2, the transformerless CMI-based PV systems can be built based
on basic H-bridge inverters or modified ones, such as Z-source inverter (ZSI) and quasi-Z-source
inverter (qZSI) [19]-[22]. The replacement of the basic H-bridge inverter with the ZSI or qZSI is
42
mainly to cope with the PV wide-range input voltage. Though the topology is slightly different,
the CM characteristics of these CMIs are quite similar. This is because the Z-source/quasi-Z-
source network can offer low-impedance paths for the high-frequency noises. Consequently, the
basic CMI will be used to study the leakage current issue. The conclusions can also be applied to
the ZSI or qZSI based CMI.
(a)
(b)
Fig. 3.1(a) shows a generic diagram of a CMI-based PV system where the parasitic
capacitors are added to study the leakage current issue. The parasitic capacitor for each cascaded
module is designated as pviC , ni ,...,2,1= . There are two symmetrical line inductors L at the total
output of the inverter. The equivalent circuit can be obtained in Fig. 3.1(b) by modeling each
inverter phase leg as a voltage source with respect to the negative terminal of its dc bus. The
phase-leg voltage sources are named as iav and ibv , ni ,...,2,1= . iav and ibv are pulse-width
Fig. 3.1 Basic CMI-based PV system: (a) circuit diagram and (b) equivalent circuit.
43
modulation (PWM) voltages which are composed of dc components, fundamental-frequency
components and baseband harmonics, carrier harmonics and its sideband harmonics [60]. The
carrier harmonics and its sideband harmonics are the main contributors to the leakage current
issue. The magnitudes of these harmonics depend on the inverter input voltages and modulation
strategy.
Due to the parasitic capacitors and several grounding points, multiple circulating leakage
current loops are formed in the CMI. These loops can be divided into two different types and
examples of the two kinds of loops are revealed in Fig. 3.1(b). The first kind of leakage current
loop is formed by the parasitic capacitor, inverter-bridge, line inductor and grid ground. Since
the line inductor and grid ground are involved in the loop, this loop is indicated as module-line
leakage current loop. The other kind of loop is formed among the inverter bridges, so it is
indicated as inter-module leakage current loop. It is a capacitive coupling path with negligible
inductance, so the high-frequency PWM voltages would generate pulsewise leakage current in
the loop. This phenomenon will be demonstrated in later case studies. Compared with the
transformerless string inverter, the inter-module leakage current loop is a unique loop exists in
the PV CMI. And it cannot be eliminated even if there is a transformer at the total output of the
cascaded inverter.
The leakage current suppression techniques for transformerless string inverters have been
well established [61]-[65]. For transformerless string inverter, the leakage current is mainly
determined by the inverter CM output [61], [62]. Several modified inverter topologies and
modulation strategies are proposed to maintain the CM output to be constant to solve the leakage
current issue [61]-[63]. The bipolar modulation strategy can significantly reduce the leakage
current because the common-mode (CM) voltage of the inverter is maintained constant [61],
[62]. But the output current quality is degraded and the conversion efficiency is decreased.
Hence many modified full-bridge topologies, which add extra dc or ac switches, are developed to
address the leakage current issue [62], [63]. Besides, the filter-based solution is also proposed to
compose a bypass loop of which impedance is very low for the high-frequency CM noises,
thereby preventing the leakage current from flowing outside [63], [64]. It is easy to be
implemented because no extra semiconductor device is needed.
In CMI, we can define ibiaDMi vvv −= and ( ) 2ibiaCMi vvv += as the differential-mode
(DM) and CM outputs of the ith module respectively. The system equivalent circuit can be
44
redrawn in Fig. 3.2 by replacing iav and ibv with DMiv and CMiv . Due to the extra inter-module
circulating loops, the leakage currents are no longer determined only by the CM outputs from the
inverter modules. Instead, the DM outputs also contribute. Therefore, the aforementioned
modulation or topology based suppression solutions for transformerless string inverters cannot
be directly applied in CMI to solve the leakage current issue. Therefore, the filter-based method
is very attractive to be considered to address the leakage current issue in CMI.
Different types of circulating current issues are also found in other multi-module systems,
such as CMI-based ac drives [66], [67], CMI-based magnetic resonance imaging systems [68]
and paralleled boost rectifiers [69], [70]. In CMI-based ac drive systems, circulating bearing
current is induced by the inverter CM voltage imposed on the motor stator winding to frame
capacitance [66], [67]. Different modulation schemes are proposed to reduce the inverter CM
Fig. 3.2 System equivalent circuit by replacing the phase-leg voltages with DM and CM voltage sources.
45
voltage to reduce the circulating current. However, these modulation schemes cannot solve the
leakage current issue in PV CMI because the PV parasitic capacitors are distributed at the dc side
instead of the load side. In [68], the authors observed the internal circulating current in CMI
formed by the inverter bus-to-ground parasitic capacitors. The high-amplitude MHz voltage
ringing over the semiconductor device is the main concern in that paper, while the ground
leakage current has not been discussed. For paralleled converters, circulating currents are
generated due to the asynchronous switching operations [69], [70]. In such kind of systems, since
there is no capacitance involved in the circulating loop, most high-frequency circulating currents
can be mitigated by inter-phase inductors. Therefore, only the low-frequency circulating currents
need to be dealt with. This is quite different from the PV CMI where switching-frequency noises
dominate the circulating leakage currents.
The following sections will introduce two filter-based methods to solve the leakage
current issue in PV CMI. The different allocation and design of the suppression filters make the
two solutions fit for different applications.
3.2 Proposed Leakage Current Suppression Solution 1
3.2.1 Description of the Solution
The circuit configuration of a PV CMI with leakage current suppression solution 1 is
illustrated in Fig. 3.3(a). Compared with the basic structure shown in Fig. 3.1, dc-side CM
chokes dccmL _ , CM capacitors cmC , and ac-side CM chokes accmL _ are added in each inverter
module. The voltage across pviC and the current through pviC are denoted as cpviv and Hileaki _ ,
ni ,...,2,1= , respectively. The leakage current flowing into the grid ground is labeled as gleaki _ .
The equivalent circuit of the system is given in Fig. 3.3(b) where the leakage inductance of the
CM chokes is ignored due to its minor impact on the leakage current issue. It is also noticed that
the accmL _ and dccmL _ can be merged to the same position in the equivalent circuit, which
implies that they would have the same contribution on leakage current suppression. accmL _ and
dccmL _ are both used in the circuit is because they can respectively help mitigate the ac-side and
dc-side EMI CM noises due to their same position with the ac and dc side EMI filters. Therefore,
46
the design effort for the ac and dc side EMI filters can be lessened, and this could compensate
the cost of accmL _ and dccmL _ to some extent. Because this work is emphasized on the leakage
issue, accmL _ and dccmL _ will be designed as one choke accmdccm LL __ + . The optimal
distribution of accmL _ and dccmL _ should further consider the EMI problem, because the
requirements for the ac and dc side EMI filters are different.
(a)
(b)
3.2.2 Simplified Leakage Current Analytical Model and Filter Design Criteria
To better understand the suppression mechanism and introduce the filter design criteria,
the analytical expression of the leakage currents is derived based on the equivalent model. The
xth inverter module is selected arbitrarily for the analysis. According to the superposition theory,
Fig. 3.3 The proposed leakage current suppression solution 1: (a) circuit diagram and (b) equivalent circuit.
47
the branch current Zxi through the inductance accmdccm LL __ + of the xth inverter module, which
is labeled in Fig. 3.3(b), can be first calculated as in (3.1).
( )( )( )
( )( ) ( )
( )( )
( )( ) ( )
( )( )∑
∑−
= +−
+−
+
+
= +−
+−
−
−
+−
+−
+⋅
+
−+
+⋅
+
−+
+⋅
+
+=
1
111
111
11
1
2 11
11
11
1
111
111
1
1
////...//////...//
////...//////...//
////...//////...//
////...//////...//
////...//////...//
////...//////...//
////...//////...//
////...//////...//
////...//
n
xi Lixxx
Lixx
LiLni
aiib
x
i Lnxxix
Lnxxi
LniLi
biia
Lnxxx
Lnxx
LnL
nbaZx
ZZZZZZ
ZZZZZ
ZZZZZZ
vv
ZZZZZZ
ZZZZZ
ZZZZZZ
vv
ZZZZZZ
ZZZZZ
ZZZZ
vvi
(3.1)
where ( ) ( )cmpviaccmdccmi
CCjLLjZ
2
1__ +
++=ω
ω , ni ,...,2,1= and LjZL ω= .
As mentioned before, the phase leg voltages contain dc components, fundamental-
frequency components and baseband harmonics, carrier harmonics and its sideband harmonics.
The fundamental-frequency leakage current, of which amplitude is relatively small, can be
simply estimated by shorting the inductors in the circuit due to their low impedances around the
fundamental frequency. At the frequencies of the carrier harmonics, LZ is usually much smaller
than the impedance of the designed iZ , so the values of the terms containing LZ in (3.1) should
be close to the value of LZ . As a result, eq. (3.1) can be simplified as in (3.2).
( ) ( ) ( )
( )Lx
xbxa
n
xi
iaib
x
i
ibia
ZxZZ
vvvvvv
i+
++−+−
≈∑∑+=
−
=
2
1
1
1 (3.2)
The simplified model implies an equivalent circuit shown in Fig. 3.4, which is composed
of a voltage source connected with a LC branch in series. The voltage source is related to the
phase leg voltages of all cascaded inverter modules. The LC circuit is formed by
LLL accmdccm ++ __ and cmpvx CC 2+ . Hxleaki _ can be obtained by (3.3).
cmpvx
pvxZxHxleak
CC
Cii
2_ +
= (3.3)
According to the simplified model, we can design the filters that most high-frequency
harmonic voltages are dropped across the inductance, in which case the high-frequency
harmonics across pvxC are lessened. In order to fulfill the requirement, the resonant frequency of
the formed LC circuit needs to be designed lower than the frequencies of the carrier harmonics,
48
specifically the device switching frequency. The final parameters of the filters can be specified
according to (3.2) and (3.3), providing that iav and ibv ( ni ,...,2,1= ) are known.
Since the value of pvxC highly depends on the weather conditions, cmC is added in the
circuit in case that pvxC gets too small. However, the value of cmC is usually limited by safety
requirements [62], [64], so the resonant frequency of the formed LC filter cannot be designed
very low. Otherwise, large CM inductors are needed. Therefore, the first solution is more
suitable for the cascaded inverter operated at high switching frequency. The applicability of this
solution at pre-selected switching frequency depends on the constraint on the filter size and cost.
3.2.3 Application Example: qZSI-based CMI with 100kHz Switching Frequency
As discussed in Section II, the conclusions obtained for the H-bridge-based CMI
concerning the leakage current behaviors can also be applied to the qZSI-based CMI. The
proposed method 1 is applied in a single-phase PV system consisted of four cascaded qZSIs. The
system was first presented in [19] and the leakage current issue has not been dealt with in that
paper. The system diagram is provided in Fig. 3.5 where each qZSI module is rated at 250W
with 25~50V input voltage range. In order to decrease the size of the quasi-Z-source network and
output line filter, the device switching frequency is chosen to be 100kHz. The 100V low-voltage
Fig. 3.4 Simplified leakage current analytical model for the system with leakage current suppression method 1.
49
GaN FETs from EPC [23] are used to improve system efficiency at high switching frequency.
The sawtooth-carrier based PWM modulation strategy is used for each module and the carrier
waveforms are phase shifted to minimize the total output harmonics. The quasi-Z-source
network is formed by HL �391 = , HL �392 = , mFC 8.81 = , FC �1982 = and 1D . Resistive load is
used in the study instead of the utility grid as in [71]. This load resistance �= 36loadR has minor
contribution to the total impedance of the leakage current loops at the switching frequency. The
inverter total output voltage is 120Vrms and the line inductor is HL �20= .
3.2.3.1 Filter design. The suppression CM filters are designed by calculating the leakage
currents based on (3.2) and (3.3). The calculated results of 1_ Hleaki and gleaki _ with different
values of accmdccm LL __ + and parasitic capacitors are shown in Fig. 3.6, where cmC is selected as
2.2nF. The fundamental-frequency leakage currents are included in the calculated results. It is
seen that the RMS value of gleaki _ slightly decreases with the increased parasitic capacitance.
This is because the impedance of the LC circuit in Fig. 3.4 is increased at the frequencies of the
Fig. 3.5. System diagram of a PV system composed of four cascaded qZSIs with leakage current suppression solution 1.
50
carrier harmonics. The RMS value of 1_ Hleaki increases with the increased parasitic capacitance
when cmpvx CC ≤ , and it becomes almost constant when cmpvx CC >> . In order to limit the
leakage currents below the standard requirement [72] with certain safety margin, 8mH of
accmdccm LL __ + is used.
(a) (b)
3.2.3.2 Simulation verifications. The PV CMI with the designed CM filters is simulated
in PSIM. pviC ( 4,3,2,1=i ) were assumed to be 1nF and the input voltages of the cascaded
modules were 45V. The simulated waveforms of 1cpvv , 2cpvv , gleaki _ , 1_ Hleaki are given in Fig.
3.7. When the suppression method was not applied, there were high-frequency harmonics in
1cpvv and 2cpvv , which induced large leakage currents. 1_ Hleaki was pulsewise current with very
high peak value due to the capacitive inter-module leakage current loop. The peak value of
gleaki _ was smaller because of the line filter L in the module-line leakage current loop, but it still
exceeded the standard requirement. By introducing the suppression method, the high-frequency
harmonics in 1cpvv and 2cpvv were significantly attenuated. The RMS values of 1_ Hleaki and
Fig. 3.6 Design results for the PV system with leakage current suppression solution 1: (a)
1_ Hleaki and (b) gleaki _ .
51
gleaki _ had been reduced to 0.61mA and 8.1mA respectively, which were well below the
standard requirement. Moreover, the simulated leakage current values were consistent with the
calculated values provided in Fig. 3.6. The accuracy of the simplified leakage current analytical
model was confirmed by the simulation results.
(a)
(b)
3.2.3.3 Experimental verifications. Two cascaded qZSI modules using GaN devices are
built in the laboratory, as shown in Fig. 3.8, to validate the performance of the proposed method.
The parameters of the qZSI module are the same as in the simulation. 1pvC and 2pvC were
purposely chosen to be different, nFCpv 301 = and nFCpv 12 = . Fig. 3.9 shows the measured
waveforms and the spectrums of 1cpvv and 2cpvv without the CM filters added in the system. It is
seen that 1cpvv and 2cpvv contained around 0.3pu 100kHz harmonics (normalized values with
Fig. 3.7 Simulation waveforms of the qZSI based PV CMI: (a) without leakage current suppression 1 and (b) with leakage current suppression solution 1.
52
respect to the input dc voltage). When the leakage current suppression was applied, the 100kHz
harmonics in 1cpvv and 2cpvv were readily reduced to 0.003pu and 0.023pu respectively as shown
in Fig. 3.10. Obviously, the carrier harmonics across 1pvC were better attenuated in this case.
This was consistent with the derived simplified leakage current analytical model given in Fig.
3.4. The increased parasitic capacitance leaded to a lower resonant frequency of the formed LC
circuit, so the harmonics in 1cpvv were better attenuated.
(a)
(b)
Fig. 3.8 Photograph of the two cascaded qZSI modules built in the laboratory.
Fig. 3.9 The experimental results without leakage current suppression 1: (a) voltage across the parasitic capacitors and (b) the corresponding spectrums.
53
(a)
(b)
3.3 Proposed Leakage Current Suppression Solution 2
3.3.1 Description of the Solution
The leakage current suppression method 2 is realized by adding dc-side and ac-side CM
chokes dccmL _ and accmL _ , and capacitors dccirC _ and accirC _ , as shown in Fig. 3.11(a). There is
a common connection point among the capacitors dccirC _ of each cascaded module and the ac-
side capacitors accirC _ . The equivalent circuit of the system is given in Fig. 3.11(b), where
internal current circulating paths, as shaded in the figure, are formed by the CM chokes, bridges,
dccirC _ and accirC _ . It is observed that the internal current circulating circuit is quite similar to
the system equivalent circuit with leakage current suppression method 1 shown in Fig. 3.3(b),
except that the capacitance accirC _2 is added in the return path and the capacitance dccirC _2
replaces cmpvx CC 2+ . Unlike the CM capacitors, dccirC _ and accirC _ can be designed relatively
large, so this solution can be applied for the CMI operated with lower switching frequency
without using very large CM chokes.
Fig. 3.10 The experimental results with leakage current suppression solution 1, Cpv1=30nF and Cpv2=1nF: (a) voltage across the parasitic capacitors and (b) the corresponding spectrums.
54
(a)
(b)
3.3.2 Simplified Leakage Current Analytical Model and Filter Design Criteria
According to the equivalent circuit, the leakage current through the parasitic capacitor of
the xth inverter is equal to
accir
pvxaccir
dccir
pvxdcxcirHxleak
C
Ci
C
Cii
__
___
22+= (3.4)
where dcxciri _ is the sum current through the two dccirC _ capacitors of the xth inverter module;
acciri _ is the total current through the two accirC _ capacitors.
Practically dccirC _ and accirC _ are designed much larger than the parasitic capacitance,
so we can get 12 _
<<dccir
pvx
C
C and 1
2 _
<<accir
pvx
C
C. Therefore, Hxleaki _ can be attenuated when the
Fig. 3.11 The proposed leakage current suppression solution 2: (a) circuit diagram and (b) equivalent circuit.
55
values of dcxciri _ and acciri _ are limited. Based on the equivalent circuit, dcxciri _ and acciri _ can
be calculated as in (3.5) and (3.6) by applying the superposition theory.
( )( )( )
( )
( )( )( )
( )Laccir
Laccirn
xi
aiib
x
i Laccir
Laccir
biiaLaccir
nbadcxcir
nZnZZZ
inZZZin
vv
nZnZZZ
iZZZi
vvnZnZZ
vvi
++
−⋅
++−
⋅−+
++
−⋅
++
−⋅−+
++
+=
∑
∑
−
=+
=−
_
_1
1
2 _
_
1_
1_
22
21
22
121
1
22 (3.5)
∑=
=n
idciciraccir ii
1__ (3.6)
where accir
accir CjZ
__ 2
1ω= , ( )
dcciraccmdccm Cj
LLjZ_
__ 21
ωω ++= and LjZL ω= . Because the
parasitic capacitances are much smaller than dccirC _ and accirC _ , they are ignored in the
calculation of dcxciri _ and acciri _ .
The above equations (3.4)-(3.6) are easy to be implemented in computer languages for
filter design. However, it is difficult to envision a simple circuit from the equations to understand
the principle more straightforward. Since accmdccm LL __ + will dominate the impedance of the
leakage current paths at the frequencies of the carrier harmonics, we approximately assume that
Zi
ZZZi
Laccir1
12
1
1_ −
≈++−
and Zin
ZZZin
Laccir −≈++
−1
21
_ in (3.5). Consequently, eq.
(3.5) can be simplified to
( ) ( ) ( )
Laccir
xbxa
n
xi
iaib
x
i
ibia
dcxcirnZnZZ
vvvvvv
i++
++−+−
=∑∑+=
−
=
_
1
1
1_
22
(3.7)
Eq. (3.7) stands for an equivalent circuit composed of a voltage source connected with a
LC circuit in series, which is similar to the one given in Fig. 3.4. The only different is that the LC
circuit is replaced by Laccir nZnZZ ++ _22 . With the simplified model, we can expect that the
switching-frequency noises in dcxciri _ and acciri _ could be limited by designing the resonant
frequency of Laccir nZnZZ ++ _22 lower than the switching frequency. The simplification used in
(3.7) is fair for understanding the principle, but it is not accurate enough because the value of LZ
56
could be comparable to the impedance of accmdccm LL __ + in applications where large dccirC _
and accirC _ are used. More accurate design of the suppression filters needs to refer (3.4)-(3.6).
The application of the solution 2 is limited when the device switching frequency drops
below around 1.5kHz. This is because that if the resonant frequency is designed below the
switching frequency, it may be very close to the frequencies of the baseband harmonics in iav
and ibv . In such a case, the internal circulating circuit could be excited by the baseband
harmonics in iav and ibv , and large circulating current will be generated in the circuit.
3.3.3 Application Example: H-bridge-based CMI with 10kHz Switching Frequency
In order to investigate the performance of the second leakage current suppression
method, it is applied in a single-phase PV system consisted of two cascaded H-bridge inverters.
The system diagram is provided in Fig. 3.12 where each inverter module is rated at 500W with
90~120V input voltage range. The device switching frequency is 10kHz and the sine-triangular
Fig. 3.12. System diagram of a PV system composed of two cascaded H-bridge inverters with leakage current suppression solution 2.
57
PWM modulation strategy is used for each module. The carrier waveforms are phase shifted to
minimize the total output harmonics. Resistive load �= 50loadR is used in the study. The inverter
total output voltage is 120Vrms and the line inductor is mHL 2= .
3.3.3.1 Filter design. The calculated leakage current results derived from (3.4)-(3.6)
under various values of parasitic capacitors and accmdccm LL __ + are shown in Fig. 3.13, where
dccirC _ and accirC _ are fixed at F�5 and F�10 respectively. The fundamental-frequency
leakage currents are also included in the calculation. The design results show that the RMS
values of 1_ Hleaki and gleaki _ both increase with the increased parasitic capacitance. It is different
from the design results of the leakage current suppression solution 1. And this can be explained
based on (3.4). The term accir
accir
dccir
dcxcir
C
i
C
i
_
_
_
_
22+ in (3.4) will be nearly constant once the filter
parameters are determined. Therefore, the increase of pvxC would raise the leakage current value
linearly. In [73], it is mentioned that the parasitic capacitance could raise up to 50-150nF/kW.
Thus 3mH of accmdccm LL __ + is used in the final design according to Fig. 3.13.
(a) (b)
Fig. 3.13 Design results for the PV system with leakage current suppression solution 2: (a)
1_ Hleaki and (b) gleaki _ .
58
3.3.3.2 Simulation verifications. In this simulation study, the input voltages of the two
cascaded modules were 100V and the two parasitic capacitors were both 100nF. The parameters
of the added filters were obtained from the above design process. The simulation results of the
system with and without leakage current suppression are provided in Fig. 3.14 (a) and (b)
respectively. It is clearly seen in Fig. 3.14(a) that there were a lot of carrier harmonics in 1cpvv
and 2cpvv which induced huge leakage currents in the circuit. 1_ Hleaki was pulsewise current due
to the capacitive inter-module leakage current loop. When the leakage current suppression was
applied, the high-frequency noises in 1pvC and 2pvC were significantly reduced. Therefore,
1_ Hleaki and gleaki _ can be reduced to 4.2mA and 5.8mA respectively which were below the
standard requirement and consistent with the calculated results.
(a) (b)
Fig. 3.14 Simulation waveforms of the PV system consisted of two cascaded H-bridge inverters: (a) without leakage current suppression 2 and (b) with leakage current suppression solution 2.
59
3.3.3.3 Experimental verifications. The above system is built in the laboratory to
validate the performance of the proposed method 2. The prototype picture is shown in Fig. 3.15.
The parameters of the inverter module are the same as in the simulation. 1pvC and 2pvC were
chosen to be different, nFC pv 1001 = and nFC pv 102 = . Fig. 3.16 shows the measured waveforms
and the spectrums of 1cpvv and 2cpvv without the suppression filters added in the system. It is seen
that 1cpvv and 2cpvv contained around 0.38pu 10kHz and 0.17pu 20kHz harmonics. When the
leakage current suppression was applied, the 10kHz and 20kHz harmonics in both 1cpvv and 2cpvv
were attenuated to very low level as shown in Fig. 3.17, specifically around 0.0047pu and
0.0024pu. Unlike the first method, the value of the parasitic capacitor had minor effect on
harmonic attenuation in 1cpvv and 2cpvv due to the much larger dccirC _ and accirC _ . Since the
high-frequency components in 1pvC and 2pvC were almost eliminated, the leakage currents
would be mainly the low-frequency components with small values.
Fig. 3.15 Photograph of the two cascaded H-bridge inverter modules built in the laboratory.
60
(a)
(b)
(a)
(b)
Because the inductance of the CM chokes can be reduced by choosing larger dccirC _ and
accirC _ , the internal circulating current could increase accordingly and the associated additional
power loss becomes a concern. Therefore, 1_ dcciri was measured and the waveform is shown in
Fig. 3.18. The RMS value of 1_ dcciri was 0.24A, which was small compared with the rated
Fig. 3.16 The experimental results without leakage current suppression 2: (a) voltage across the parasitic capacitors and (b) the corresponding spectrums
Fig. 3.17 The experimental results with leakage current suppression solution 2, Cpv1=100nF and Cpv2=10nF: (a) voltage across the parasitic capacitors and (b) the corresponding spectrums
61
current through the inverter circuit. Therefore, the internal circulating current in this design
would not cause noticeable inverter efficiency drop.
3.4 Summary
The leakage current issue in PV CMI features inter-module leakage current loops formed
among the cascaded inverter modules. The inter-module leakage current loop exists even there is
a transformer at the total output of the CMI and it prevents the existed string inverter leakage
current suppression techniques to be directly applied in the CMI. Two leakage current
suppression solutions were presented for the PV CMI by constructing LC filters in the leakage
current paths to attenuate the high-frequency noises. Since the solution 1 utilizes the low-
capacitance CM capacitors and parasitic capacitors as part of the LC filters, it is more suitable
for the CMI operated at high switching frequency. The applicability of this solution at pre-
selected switching frequency depends on the constraint on the filter size and cost. In solution 2,
capacitors dccirC _ and accirC _ are added to form LC filters with the CM chokes. This solution is
applicable for CMI with device switching frequency above around 1.5 kHz. However, extra
wires are needed to connect all the capacitors dccirC _ and accirC _ to a common point and it
would increase the balance of system costs. In conclusion, the solution 1 is preferred in PV CMI
Fig. 3.18 The measured waveform and the RMS value of 1_ dcciri .
62
operated with high switching frequency. When the switching frequency decreases to a level that
the size and cost of the CM chokes go beyond the design requirement, the solution 2 should be
applied. The suppression filters utilized in the two solutions can be designed based on the
simplified leakage current analytical models. Design examples were provided and the design
results from the derived models were consistent with the simulation results. Hardware prototypes
were built and tested to validate the effectiveness of the proposed leakage current solutions.
63
CHAPTER FOUR
INTEGRATED AUTONOMOUS VOLTAGE REGULATION AND
ISLANDING DETECTION
Increasing penetration of distributed PV systems introduces new integration issues
concerning the safe operation of distribution systems [74], [75]. The voltage rise due to the
reverse power flow and voltage fluctuations associated with the irradiation variation have been
envisioned from field observations and research results [76]-[78]. Possible false tripping of mass
distributed PV systems as a result of the tight anti-islanding voltage/frequency settings could
lead to unacceptable low voltage [74]. These problems impose more stress on the utility voltage
regulation (VR) devices, and even cause them to malfunction. Therefore, it is important to
research effective methods to mitigate the impact of the distributed PV systems on the feeder
voltage profiles. Moreover, in order to ride through the grid disturbances, loose anti-islanding
voltage/frequency trip settings are recommended [31], but it increases the possibility of islanding
detection (ID) failure. Consequently, it is necessary to develop more intelligent active ID
algorithms to ride through voltage disturbances without expanding the islanding non-detection-
zone (NDZ) [32].
4.1 State-of-the-art Voltage Regulation and Islanding Detection Methods
To actively involve distributed PV systems in feeder voltage regulation is one of the
promising solutions for the potential voltage issues [79]-[83]. In fact, they can assist and
coordinate with the low-speed utility VR devices to form a two-layer (low and high speed) VR
system [74]. The state-of-the-art inverter-based VR methods mainly include power curtailment
[76], [80], volts/var droop control [80], [81] and communication-based PI control [82], [83].
However, there are possibilities of operation conflicts between VR and active ID algorithms
implemented in the same PV inverter. On one hand, some VR and ID methods cannot be realized
simultaneously because the same control variable is employed for different objectives. Typically,
the frequency positive feedback ID method [84] cannot work with the reactive-power-based VR
64
method [80]-[83], since they control the reactive power based on voltage frequency and
amplitude feedback respectively. On the other hand, an incorrect response of VR or ID
algorithms to the instantaneous voltage variation without distinguishing the cause may result in
function failures. This possibility is due to the fact that both islanding and short-duration voltage
events [85] could induce an instantaneous voltage change. For example, if there is a voltage sag
event, the voltage positive feedback ID [84] method will reduce the inverter real power output
which leads to further feeder voltage decrease. Moreover, improper VR at the islanding instant
may increase the chance of unintentional power matching between the load and source [86],
which would increase the risk of ID failure. Communication is thus considered to be applied
between the utility and PV systems [32], [81]. However, it will add extra cost and require a
backup scheme during communication failure.
In addition, the interference among different PV systems with respect to the VR and ID
performances is also of high interest. It is reported in [82] that inverter-based VR may lead to
feeder voltage instability, so an adaptive PI controller design is given in that paper. However, the
method needs communication to obtain an ideal voltage response curve for adjusting controller
gains in real-time. For active ID, the effectiveness may be compromised because of the
interference, as discussed in [32], [87]. Another disadvantage shared by most active ID methods
is the possible degradation of system power quality [32]; some even can cause stability problems
when there is large number of PV systems [88].
Reference [89] pointed out that it is beneficial to implement the PI-based voltage
controller and the rate of change of frequency (ROCOF) ID method together. They can
coordinate with each other to realize the VR function and decrease the ID NDZ. However,
communication device is required for practical implementation as the PI-based voltage controller
usually requires communication to give the PCC voltage reference. Moreover, this reference
discussed the ID performance based on fixed controller parameters but did not provide any
further study of the impact of the controller parameters on the VR stability and ID NDZ. An
autonomous controller was proposed by the authors in [90] to integrate the VR and ID functions
in a PV inverter. It can be applied in the PV systems that are not equipped with communication
device or when the communication device failed, which is an advantage when compared to those
controllers that require communication capability. But the design of the controller is difficult due
65
to the non-linear programmed limiter in the controller; and it may cause unnecessary reactive
power consumption during voltage regulating.
Based on the previous work [90], an unified var controller is proposed in this chapter to
address the VR and ID issues in high PV penetration application. The non-linear programmed
limiter is eliminated to simplify the controller design; and the volts/var droop curve [80] is
integrated in the proposed controller to prevent unnecessary reactive power consumption. The
unified var controller integrates the VR and ID functions in a PV inverter through reactive power
control. It can discriminate between islanding and short-duration voltage events readily, so it
enables the capabilities to ride through the short-duration voltage events and help mitigate the
potential voltage issues. Moreover, the anti-islanding protection can be realized with no impact
on the system power quality. The ID performance is also not degraded in multiple-PV scenarios,
because all the PV systems can be synchronized by the proposed controller as will be explained
later. Theoretical analysis has also been done to give the controller design criterion according to
the VR dynamic performance and its effect on the ID NDZ.
To validate the proposed control strategy and controller design method, a modified IEEE
34 node test feeder model [91] and the IEEE anti-islanding test circuit [92] with multiple PV
systems are developed in the RTDS. Several test cases, including overvoltage, voltage sag and
islanding, are conducted in RTDS simulation. A power hardware-in-the-loop (PHIL) testbed is
built in the laboratory where a PV inverter prototype is developed and integrated with the rest of
the distribution system being simulated in the RTDS platform. Therefore, the proposed controller
can be verified experimentally under system level in high penetration conditions.
4.2 Proposed PV Control System Description
4.2.1 Principle of integrating VR and ID
In high PV penetration conditions, advanced interconnection technologies are required to
operate PV systems safely with the utility and yield benefits for the customers. The concept of
integrating VR and ID through a unified controller is proposed in this research. Fig. 4.1 shows a
generic diagram of a PV system connected to the distribution system, where the PV array is
connected to the PCC through the inverter and a passive filter. A triac is used as the static
66
transfer switch (STS) to enable/disable the connection between the PV system and the grid. For
simplicity, the local load is lumped as a parallel RLC circuit; and the distribution system is
represented by an infinite voltage source with an equivalent line impedance ss jXR + . The PV
inverter output power, local load power, and the power from grid are denoted as PVPV jQP + ,
LL jQP + , and gg jQP + , respectively.
In grid-connected mode where the utility disconnect switch (UDS) is closed, the PCC
frequency f is clamped by the infinite bus 1v . The PCC voltage amplitude PCCV can be
calculated by (4.1).
( )( )
( )( )PCC
SSLPV
PCC
SSLPVPCC
V
RXQQ
V
XRPPVV
δδ
δδ
sincos
sincos1
+−+
−−+=
(4.1)
where 1V is the amplitude of 1v ; δ is the phase difference between PCCv and 1v . The
detailed derivation of (4.1) is shown in Appendix A. As required by the local utility operator or
standards such as ANSI C84.1, PCCV needs to be maintained within the permitted voltage range
by certain measures. Eq. (4.1) illustrates that PCCV can be regulated through adjusting PVP and
PVQ from distributed PV systems. The real power control is usually employed to eliminate PCC
overvoltage by forcing the PV system operation away from the maximum power point [76], [80].
Fig. 4.1 A local PV system connected to the distribution system.
67
The reactive power control can contribute to network voltage regulating both dynamically and
statically [80]-[83].
Subsequent to an islanding event when the UDS is open, the PCC voltage deviation
directly depends on the power mismatch between the PV and the load. If 'PCCV and 'f are
defined as the new PCC voltage and frequency after islanding, and
( ) ( )LPVLPV QQjPPQjP −+−=(+( is the power mismatch between the PV and load, the
relationship between them can be described as (4.2) and (4.3) [93].
2'
2
1PCC
PCC
PV V
V
P
P−=
( (4.2)
1tan
1'
2
2''
−+
−=
(−
(f
fQ
f
f
Q
Q
P
P
f
f f
PVPV ϕ (4.3)
where ϕ is the inverter output phase angle and fQ is the quality factor of the local load [94].
When the power mismatch is within specified thresholds, 'PCCV and 'f will remain within the
nominal ranges even after the grid is disconnected, in which case the islanding network is
difficult to be detected. From this understanding, control of PVP or PVQ after the grid is
disconnected can push 'PCCV or 'f out of the nominal ranges.
As shown above, both VR and ID control need the PCC information and can be
implemented by means of real/reactive power variation, which provides a possibility to integrate
both functions.
4.2.2 PV Control System with the Proposed Unified Var Controller
A distribution network including multiple PV systems equipped with the proposed
control system is shown in Fig. 4.2. One of the PV systems is depicted in detail. The PV control
system is mainly composed of the grid-current controller, root-mean-square (RMS) and phase-
locked loop (PLL) blocks, over/under voltage (OV/UV) and over/under frequency (OF/UF)
protection block, and the proposed unified var controller. The grid-current controller ensures
high quality sinusoidal current injected into the grid by tracking the current reference synthesized
from the real and reactive power reference. The modulation index is then sent to the PWM
generator to drive the inverter. The RMS and PLL blocks generate PCCV and f information to
68
manage the STS on-off operation through the OV/UV and OF/UF protection block. The unified
var controller realizes VR and ID functions through reactive power control. It consists of the
voltage controller and the adaptive voltage reference generator, including the instantaneous
voltage reference compensator (IVC) and the average voltage reference compensator (AVC).
They are introduced as follows.
4.2.2.1 Voltage controller. The voltage controller, which is an integral regulator, ∫dtK I ,
is the key component of the unified var controller to integrate the VR and ID functions. The
reference of the voltage controller is *PCCV and the feedback signal is the measured PCCV . When
the grid is connected, the voltage controller adjusts *PVQ to regulate PCCV . If the islanding forms,
control of *PVQ can no longer change PCCV , hence the voltage controller will integrate the error
between *PCCV and PCCV , which leads to rapid increase of | *
PVQ |. Consequently, a sudden
reactive power injection can be initiated to break the power balance inside the islanding network.
In this case, the islanding and temporary grid disturbances can be discriminated readily. The
Fig. 4.2 Proposed PV control system applied to multiple distributed PV systems.
69
proposed controller does not need to perturb the real/reactive power output for ID during grid-
connected conditions. The ID function is seamlessly triggered when islanding occurs, so it has no
adverse impact on system power quality. Detail design of the voltage controller regarding the VR
dynamic performance and NDZ of ID will be discussed in section III and IV.
4.2.2.2 Adaptive voltage reference generation. In the proposed controller, *PCCV is
generated autonomously by an adaptive voltage reference generation mechanism. This is
different from the communication-based PI control, in which case *PCCV is sent from a central
controller through communication and the reference dispatching for each PV system should be
solved by optimization algorithms, such as the multiagent-based scheme [95]. In this work, *PCCV
is created by adding an initial value (for example the PCC rated voltage nV =1.0pu) with the
compensation part, compV , which includes the instantaneous part insV and the average part aveV .
insV is generated from the IVC, which is composed of a proportional controller P_insK and
limiter 1. When *pvQ is beyond the saturation value of limiter 1, the exceeded value will lead to
quick voltage reference adjustment insV through P_insK . In case PVQ reaches the limit value at
the moment of islanding, the saturation value of limiter 1 is set to be smaller than the final output
Fig. 4.3 Volts/var curve for the AVC.
70
limiter (limiter 2). For example, if the limiter 2 saturation value is pu5.0± , the limiter 1
saturation value could be set to pu45.0± . The reserved 0.05pu reactive power is required for the
reactive power variation for ID. The function of IVC is similar to anti-windup with back-
calculation, so selection of insK can refer to the anti-windup design [96].
aveV is generated from AVC, which is used to prevent unnecessary reactive power
consumption by including the volts/var droop curve [80]. The AVC includes a low-pass filter, an
integral controller ∫ dtK I_ave and a volts/var curve. A desired reactive power value *desQ is output
from the volt/var curve block and compared with *pvQ to adjust aveV through ∫ dtK I_ave . The
volts/var curve is shown in Fig. 4.3. There is a dead band in the curve with 0* =desQ when PCCV
is in the vicinity of ( ) ( )puDD +− 1~1 . The length of the dead band can be different depending on
the inverter locations. Usually the inverter at the end of the distribution feeder will have narrower
dead band [80]. *desQ increases/decreases to the limit value when PCCV is at the threshold service
voltage level. The low-pass filter 22
2
2 cc
c
ss ωζω
ω
++ is used to filter the short-time voltage
transient, so the AVC does not interfere with the voltage controller operation. Selection of IaveK
and the second order filter parameters is a trade-off between AVC not affecting the voltage
controller performance and the settling time not being too slow to interfere with the low-speed
utility VR devices.
4.3 Voltage Controller Design Methodology
Since the VR and ID functions are integrated in the unified var controller, the controller
design must fulfill the requirement of VR dynamic performance and ensure small ID NDZ area
simultaneously. Compared with the IVC and AVC, the voltage controller has a significant effect
on the performance of the two functions, thus design of the voltage controller is important. In
order to achieve small ID NDZ, higher voltage controller gain is always preferred, but it may
degrade the dynamic performance of VR. Consequently, the voltage controller design needs to
71
be performed according to the VR requirement first. The ID NDZ can then be examined
afterwards.
In this section, a PV system model is developed first to investigate the limitations of VR
dynamics. Based on the analysis, a voltage controller design criterion is then obtained to achieve
optimized dynamic performance of VR. In addition, the influence of the interaction among
multiple PV systems on the VR dynamics should be taken into consideration. Thus, a typical
system including two PV systems is applied to investigate the performance of the designed
voltage controller.
4.3.1 Voltage Controller Design Based on Single PV system
In order to elaborate the voltage controller design, a single PV system model is developed
in Fig. 4.4 under the synchronous rotating d-q reference frame aligned with the grid voltage. The
single PV system model includes the control stage and the power stage. In this work, only q-axis
model is described because of the interest in the control effect of reactive power on PCC voltage.
The d-axis model can be built in similar manner, but it is out of scope of this section. In this
model, the voltage controller outputs the reference of the q-axis component of the grid current gi
, which is defined as *gqi . *
gqi is directly related to *PVQ in d-q reference frame. The voltage
controller feedback is generated through the RMS block. The RMS block has a calculation delay
caused by the o90 delay that is introduced to create the imaginary orthogonal phase in single-
phase application [97]. This delay can be imitated by a first order component ( )11 +sτ . The
Fig. 4.4 The single PV system model block diagram.
72
current controller includes a proportional-integral (PI) regulator ( )cPC sK τ11+ and associated
sampling and transport delay ( )11 +ssτ [98].
In the power stage, gqi is generated through the inverter PWM gain PWMK and the
inverter filter inductor fL . PVQ is then obtained by multiplying gqi with PCCV5.0 . The
relationship between PVQ and PCCV can be expressed in (4.4), which is derived from (4.1) by
setting 1cos ≈δ and 1sin ≈δ as the phase difference δ is usually small in distribution systems
[91].
( )PCC
sPVb
PCC
sPV
PCC
sLsLPVPCC
V
XQV
V
XQ
V
XQRPPVV +=+
−−+≅ 1 (4.4)
where ( )
PCC
sLsLPVb
V
XQRPPVV
−−+= 1 represents the system disturbance that affects the PCC
voltage.
Because the purpose of VR is to compensate the system disturbance, the PCC voltage
disturbance rejection capability is of great interest. It can be described in (4.5) according to Fig.
4.4.
( )( ) SIcb
PCC
XKsGss
ss
V
V
⋅⋅+++
=)(5.01
1
ττ
(4.5)
where )(sGc is the transfer function of the current control loop, which can be expressed as
( )PWMPCcPWMPCfcfcs
cPWMPC
gq
gqc
KKsKKsLsL
sKK
i
isG
+++
+==
ττττ
τ23
*1
)( (4.6)
The dynamic performance of VR is constrained by the RMS calculation delay as seen
from (4.5). This constrain can be firstly assessed by assuming ideal current control loop (
1)( =sGc ) in (4.5). Under this assumption, the system poles are calculated as
τ
τ
2
211 SI XKs
−±−= (4.7)
When 021 ≥− SI XKτ , the voltage regulating response is overdamped and the response
settling time equals to SI
SXK
tττ211
8
−−= . In this case, St can be decreased by increasing IK .
However, when 021 <− SI XKτ , SI XKτ21− becomes the imaginary part of the pole and further
73
increase of IK only increases the response oscillation frequency. Therefore, the voltage
response settling time is limited to τ8=St due to the RMS calculation delay.
In addition, since the current control loop has finite bandwidth, its influence on VR
response can be illustrated in Fig. 4.5 by examining the system root loci. The root loci were
derived based on the selected PV system parameters given in Table 4.1. It is indicated that St can
be further decreased as compared with τ8 , but this is accompanied by a higher frequency
response oscillation. Moreover, the voltage response oscillation may become undamped when
IK is even larger, in which case the voltage controller poles move to the right-hand plane.
PV inverter
Filter inductor fL 5mH
Sampling delay sτ 0.1ms
+
cPC s
K τ11
14.0=PCK 3103.1 −×=iτ
PWM gain PWMK 280
PK 0
RMS calculation delay τ 5ms
Line impedance SX �096.0
Table 4.1 Parameters of a single PV system
Fig. 4.5 Root locus of a single PV system.
74
In practical implementation, the required settling time of VR does not need to be as short
as τ8 . Also, PCC voltage oscillation is not desired during voltage regulating. Therefore, the
optimized VR performance can be achieved by designing the voltage controller poles on the real
axis, as seen from Fig. 4.5. With this design criterion, the coupling between the voltage control
and the current control loop becomes negligible. Detailed explanation is provided in Appendix
B. Consequently, the voltage controller design procedure can be simplified by employing an
ideal current control loop. The condition of assigning the voltage controller poles on the real axis
can be implemented as
021 ≥− SI XKτ (4.8)
4.3.2 VR Interaction among Multiple Systems
The effectiveness of the above voltage controller design criterion needs to be further
verified by investigating the VR interaction among multiple PV systems. A typical network with
two PV systems is provided in Fig. 4.6. The subscripts i and j are affiliated to identify two
different PV systems.
The two PV systems are coupled through the impedance network. The network model
describing the relationship between the PV injected active/reactive power and the PCC voltages
is given in (4.9). The detail derivation of (4.9) can be found in Appendix A.
Fig. 4.6 A distribution network with two PV systems.
75
( )
+−−
+≅
++≅
PCCj
sjPVj
PCCj
sjLjsjLjPVjPCCiPCCj
PCCj
siPVj
PCCi
siPVibPCCi
V
XQ
V
XQRPPVV
V
XQ
V
XQVV
(4.9)
where ( ) ( )
PCCj
siLjsiLjPVj
PCCi
siLisiLiPVib
V
XQRPP
V
XQRPPVV
−−+
−−+= 1 . The PCC voltages’ phase angle
iδ and jδ are ignored in the network model derivation.
The disturbance bV is selected as the system input. The system output variables include
all PCC voltages. Thus, the transfer function of PCCiV and PCCjV versus input bV can be obtained
in (4.10) and (4.11) by incorporating (4.9) and the control systems.
( )( ) ( ) )()(25.0
)(15.0
2 sGsGXKKsCsC
sGssXK
V
V
cjciSiIjIiji
cjiSjIj
b
PCCi
−
+=
τ (4.10)
( )( )( ) ( ) )()(25.0
11
2
2j
sGsGXKKsCsC
sss
V
V
cjciSiIjIiji
ji
b
PCC
−
++=
ττ (4.11)
where ( ) ( ) )(5.01 sGXKsssC ciSiIiii ++= τ and ( ) ( ) ( ) )(5.01 sGXXKsssC cjSjSiIjjj +++= τ .
It is noticed the two subsystems share the same characteristic equation, which equals to
the sum of the term )()(25.0 2 sGsGXKK cjciSiIjIi− and the multiplication of each single system’s
characteristic equation. The additional term, )()(25.0 2 sGsGXKK cjciSiIjIi− , is the result of system
interaction and is affected by both the network impedance and controller parameters. Moreover,
extra system zeros, which are contributed by the simultaneous response of multiple systems to
reject the disturbance, are added in each subsystem. These added zeros could lead to faster VR
dynamics. Nevertheless, undesired VR overshoot may also exist. It is unavoidable when there is
no communication between systems. To further look into the system stability, the dynamic of the
current control loop can be ignored because it has minor affect on the VR stability, if the above
voltage controller design criterion is met. Accordingly, the two-PV system characteristic
equation is simplified to
( )[ ] ( ) ( )[ ] 225.05.015.01)( SiIjIiSjSiIjjSiIii XKKXXKssXKsssC −+++++= ττ (4.12)
76
Since the same RMS calculation method is applied in the two PV systems, thus
τττ == ji , the system poles can be calculated as
ττ
ττ
ττ
ττ
22
1
22
1
22
1
22
1
4
3
2
1
BAp
BAp
BAp
BAp
−+−=
++−=
−−−=
+−−=
(4.13)
where ( )ττ SjSiIjSiIi XXKXKA +−−=1 and ( )[ ] 225.05.02 SiIjIiSjSiIjSiIi XKKXXKXKB ++−= τ .
The calculated poles 1p - 4p are all in the left-hand plane because 1<+ BA and 1<− BA .
Therefore, the interaction does affect the VR dynamics but the system stability is still
guaranteed, which implies that the voltage controller design criteria obtained in single-PV case
can be applied for multiple-PV case. The following aspects have been considered in the analysis.
1. The influence of iδ and jδ are neglected because of the small values, but in fact iδ and
jδ will dynamically change during voltage regulating because of the PV reactive power
injection. If the change of iδ and jδ during voltage regulating becomes significant, then
more detailed analysis should be performed. However this is the rare case which happens
only when the change of PV reactive power is comparable to load power in the network.
2. The current control dynamic is neglected in the analysis due to the loose coupling
between the voltage control and the current control loop. However, the interaction among
multiple current control loops could also cause system instability [99]. Therefore, the
current control loop stability should be ensured first in the design process. Detailed
discussion of the current control loop design considering the system interaction can be
found in [99], [100].
77
4.4 Islanding Detection Characteristic Analysis
4.4.1 NDZ of the Proposed Method
After IK is identified according to the requirement of VR dynamics, it is necessary to
examine its effect on the ID performance. The NDZ is the primary index to evaluate the ID
performance. There are several approaches to define the NDZ, such as the power mismatch
space, RLC load space, and the fQ versus load resonant frequency space. The power mismatch
space represented by the space formed by the PVPP( and PVPQ( boundaries [101] is used
here to determine the NDZ of the proposed ID method.
As a comparison, the NDZ of the passive ID without the proposed controller is firstly
calculated in (4.14) and (4.15) based on the OV/UV and OF/UF settings [101]
11
2
min
2
max
−
≤
(≤−
V
V
P
P
V
V n
PV
n (4.14)
−≤
(≤
−
2
max
2
min
11f
fQ
P
Q
f
fQ f
PVf (4.15)
where minV and maxV are the OV/UV protection thresholds; minf and maxf are the OF/UF
protection thresholds.
The proposed unified var controller facilitates the ID through reactive power injection at
the islanding moment. If in the prescribed islanding clearing time, the reactive power is
accumulated to a value outside of the region defined in (4.15), the islanding network can be
detected. From the control block diagram shown in Fig. 4.4, the accumulative reactive power
output after grid disconnection is
( )
( )∫
∫−≅
−=(
dtVVVK
dtVVVK
Q
PCCPCCnI
PCCPCCPCCI
PV
*
*
2
2 (4.16)
where the integral part does not include the initial value obtained before islanding.
It is shown that both IK and the PCC voltage deviation PCCPCCPCC VVV −=( * at the
islanding instant determines the value of PVQ( . When IK is fixed, there will be a range of
PCCV( between which the islanding cannot be detected. In addition, as shown in (4.2), the value
78
of PCCV( depends on the real power mismatch between PV and load, P( , at the islanding
moment, so the proposed controller has a different real power mismatch region comparing with
the passive ID. Based on the analysis and (4.14)-(4.16), the new real power mismatch region can
be calculated as
12
12
2
12
2
2
22
2
−
+≤
(≤−
+cI
n
n
PV
cIn
n
tK
QV
V
P
P
tK
QV
V (4.17)
where ct is the required islanding clearing time,
−⋅=
2
min1 1
f
fQPQ fPV and
−⋅=
2
max2 1
f
fQPQ fPV . The above real power mismatch region strongly depends on the
value of IK and PVP . To exhibit the performance improvement of the proposed ID method, the
system provided in Table 4.1 is employed as an example to specify the NDZ.
According to the IEEE std. 1547 [94], the OV/UV and OF/UF protection thresholds are
set as
nmax %110 VV ⋅= , nmin %88 VV ⋅= , Hzf 5.60max = , and Hzf 3.59min =
The required islanding clearing time is stc 2= . If 5.2=fQ , kWPPV 10= and IK is
selected as SXτ2
5.0 , that is half of the critical value given in (4.8), the NDZ of the passive ID
and the proposed method can be specified in Fig. 4.7 (a). It is obvious that the NDZ is largely
reduced by using the proposed strategy. For the proposed controller, higher fQ leads to larger
NDZ. For example, when fQ is decreased to 1, the NDZ decreases from
%016.0%011.0 ≤(
≤−PVP
P, %11.4%94.5 ≤
(≤−
PVP
Q to %006.0%004.0 ≤
(≤−
PVP
P,
%11.4%94.5 ≤(
≤−PVP
Q.
The simulation study shows that the simulated NDZ is even smaller than the theoretical
NDZ. The main reason for the difference is that the theoretical analysis treats the PLL block as
an ideal one. However, the PLL block does generate errors when the PCC voltage frequency
79
changes quickly under islanding conditions. The generated error in PLL block leads to extra real
power output, which could change PCCV( and thus accelerate the change of PVQ( . Fig. 4.7(b)
shows one simulation case of 0≈(
PVP
Q and %011.0−=
(
PVP
P, which corresponds to a point at the
edge of the theoretical NDZ. When the controller was not enabled, the PCC voltage kept nearly
the same before and after the islanding event; when the controller was enabled, the PCC voltage
frequency drifted away and reached the threshold Hz3.59 after around ms400 . In practical
conditions, there is always some real power mismatch during islanding and there is voltage
sensing noise as well, so the ID NDZ of the proposed method becomes negligible.
To enable the PV system’s fault-voltage ride-through capability, the OV/UV and OF/UF
protection settings need to be widened comparing with the settings given in the IEEE std. 1547.
As seen from (4.15) and (4.17), only the OF/UF protection settings have an influence on the
NDZ of the proposed controller. If the OF/UF settings recommended in [31], Hzf 2.62max = and
Hzf 8.57min = , are adopted, the new NDZ is depicted in Fig. 4.7(c). Moreover, to coordinate with
the re-closers in the distribution systems, the required islanding clearing time may be less than
2s. In Fig. 4.7(b), the NDZ of the proposed controller with mstc 500= and mstc 100= are also
given. The NDZ increases with the widen OV/UV settings and the decreased clearing time, but it
is still much smaller than the NDZ of the passive method.
4.4.2 Coordination of Multiple PV Systems in ID
Coordination of multiple PV systems is vital for ID effectiveness. During the islanding
event, the reactive power injection from multiple systems should be synchronized both in time
and direction. This can be readily realized with the proposed unified var controller. The total
reactive power injection from the PV systems is calculated as
( )∑ ∫∑==
−=(=(n
x
PCCxPCCxPCCxIx
n
x
PVxPVtotal dtVVVK
QQ1
*
12
(4.18)
where the subscript x is used to identify different PV systems; n is the number of PV systems.
Each PV system outputs the reactive power according to the value of ( )PCCxPCCx VV −* .
When the islanding occurs, the PCC voltages PCCxV ( nx ,,2,1 ⋅⋅⋅= ) would have the same direction
80
of deviation at the same time. This allows for the reactive power outputs from different PV
systems to be synchronized autonomously.
(a) (b)
(c)
Fig. 4.7 NDZ of the passive anti-islanding method and the proposed method (a) theoretical analysis according to the IEEE std. 1547 requirement; (b) simulation validation; and (c) theoretical analysis with widened protection settings and with different clearing time.
81
4.5 RTDS Simulation and PHIL Experimental Verification
In order to validate the effectiveness of the proposed unified var controller and
demonstrate the performance of the voltage controller design method, typical scenarios
including overvoltage, voltage sag and unintentional islanding in distribution system with
multiple PV systems have been selected and studied using RTDS simulation and the PHIL
experimental testbed respectively.
4.5.1 The RTDS Simulation Platform and PHIL Testbed
To accurately model the distribution system transients, multiple distributed PV systems,
distributed loads, distribution lines, substation transformers and control systems should be
included in the simulation models. As a result, the simulation speed becomes an issue due to the
large number of components. RTDS provides a good simulation platform when the system
becomes complicated. It features the capability of simulating electromagnetic power system
models in real time with a typical time step of 50�s. The 14 RTDS racks installed in the
laboratory can simulate electrical networks of up to 784 electrical nodes.
Fig. 4.8 PHIL testbed for experimental verification under high PV penetration conditions.
82
In addition, the RTDS simulation platform can integrate with the hardware device to
perform PHIL closed-loop testing. A PHIL testbed has been built in the laboratory as shown in
Fig. 4.8. It is composed of the simulated power system built in RTDS, a 1kW PV inverter
prototype [18], and an interface voltage amplifier. The interface voltage amplifier is a back-to-
back converter system and employs the ABB Power Electronics Building Block (PEBB). The PV
inverter prototype is connected to the interface point in the simulated power system through the
voltage amplifier, where the voltage type ideal transformer model [102] is applied as the
interface algorithm. The interface point voltage signal is sent to the PEBB’s control system
through the digital/analog converter (DAC) and reproduced at the PEBB inverter stage output.
The actual PV inverter output current is measured and fed back into the simulated circuit through
the analog/digital converter (ADC). A coefficient k in series with the ADC is used to virtually
scale up/down the PV inverter power rating [103]. The proposed unified var controller is
implemented in both the PV inverter hardware and rest of the PV inverters simulated in RTDS.
Therefore, the PHIL testbed provides an environment in which not only the proposed controller
can be verified experimentally, but also the interaction among multiple PV systems can be
investigated. In addition, the PHIL experimental results are also compared with pure RTDS
software simulation results and they are consistent with each other.
4.5.2 Overvoltage and Momentary Voltage Sag Test Cases
4.5.2.1 IEEE 34 node test feeder. The IEEE 34 node test feeder characterized as a very
long feeder requiring voltage regulation [91] is chosen as the testing environment. Some
modifications have been made on the standard test feeder in this research. As shown in Fig. 4.9,
clustered single-phase PV systems are installed at the nodes 844 and 890 (indicated as 844N and
890N ) with the total PV penetration level reaching to approximately 20%. Selection of 844N
and 890N for PV installation is due to the heavy load on the two nodes. Besides, secondary line
impacts are taken into account by adding the customer service transformer and 15.24 meters of
service line for each customer. In the simulation model, the PV systems connected to one node
are lumped and modeled as a controlled current source for simplicity. The PCC voltages and the
reactive power output from the PV systems at 844N and 890N are denoted as 844V , 890V and
844Q , 890Q respectively. Affixes a, b and c will be added in the subscript to represent phase A, B
83
and C in the following descriptions. The unified var controller parameters for the PV inverters at
844N and 890N are given in Table 4.2.
4.5.2.2 Overvoltage test. In this test case, the voltage rise phenomenon was created at
890N by the reverse power flow from the PV systems. The purpose of this test is to demonstrate
the static voltage regulation capability and fast response speed of the proposed controller. The
influence of the interaction among the PV systems on VR dynamics can also be investigated.
Fig. 4.10 shows the RTDS simulation results of the PCC voltages and the reactive power
response at 844N and 890N . In the beginning, the unified var controllers in all PV systems were
enabled except the one at aN 890 . As shown in the results, bV890 and cV890 were regulated at
1.046pu and 1.039pu respectively and they were still under the ANSI upper service voltage limit
Fig. 4.9 One-line diagram of the modified IEEE 34 node test feeder with high penetration PV systems.
84
1.05pu. In contrast, aV890 experienced an overvoltage issue. For the PV systems at 844N ,
reactive power outputs were small because aV844 , bV844 , and cV844 were inside the defined
volts/var curve deadband 0.88pu ~ 1.02pu. At t=12s, the unified var controller in the aN 890 PV
system was enabled, aV890 was reduced into the nominal voltage range in around 0.5s. At the
same time, it is observed that the regulation of the aN 890 PV system had interactive influence
on other nodes, especially for aN 844 . The influence on phase B and C inverters caused by the
phase mutual impedance was much smaller. Nevertheless, there were no high-frequency voltage
oscillations when multiple PV systems tried to regulate their own PCC voltage.
In the PHIL test, the PV system at aN 890 was replaced with the PV inverter prototype.
The coefficient k in Fig. 4.8 was selected as 75, thus the 1kW PV inverter can be virtually scaled
up to a 75kW inverter. The PHIL experimental results are given in Fig. 4.11. The upper two
waveforms are the instantaneous PCC voltage and output current of the PV inverter hardware.
The lower two waveforms are the PCC voltage RMS value and PV inverter reactive power
output. The noise on the PCC voltage RMS value waveform was from measurement, which did
not affect the system operation. Once the unified var controller was enabled, the PV inverter
absorbed reactive power to reduce the PCC voltage from 1.065pu to 1.042pu in 0.5s, which is the
same as in the simulation.
844N 890N
Voltage controller
IK 2380 980
Limiter 2 saturation value
±0.5pu (1pu=67.5kW)
±0.5pu (1pu=75kW)
IVC insPK _ 0.05 0.05
Limiter 1 saturation value
±0.45pu ±0.45pu
AVC
aveIK _ 6105 −× 6105 −×
D
0.02pu (1pu=120V)
0.02pu (1pu=120V)
cω , ζ
188rad/s, 0.8 188rad/s, 0.8
Table 4.2 The unified VAR controller parameters for the PV inverters at N844 and N890
85
(a)
(b)
(c)
(d)
Fig. 4.10 Overvoltage test case: RTDS simulation results of (a) node 890 PCC voltages; (b) node 890 reactive power outputs; (c) node 844 PCC voltages and (d) node 844 reactive powers
outputs.
Fig. 4.11 Overvoltage test case: PHIL experimental waveforms of the hardware PV inverter reactive power output and PCC voltage.
86
4.5.2.3 Momentary voltage sag test. The momentary voltage sag test aims to
demonstrate the proposed controller’s capability of distinguishing between the short-duration
voltage disturbances and islanding events. A 90% voltage sag lasting for 3s was assumed at the
substation, node 800. The simulation results are shown in Fig. 4.12. The unified var controller in
every PV system was enabled in the beginning. Before the voltage sag event, aQ844 , bQ844 , and
cQ844 were nearly zero because the node voltages were in the volts/var curve deadband. The PV
systems at 890N had injected reactive power resulting from the relatively low PCC voltage.
When the voltage sag happened, all the PV systems output around 0.45pu reactive power to
support the voltage. However, because of the limited reactive power rating, aV890 , bV890 , and
cV890 were still below 0.88pu (the undervoltage protection threshold defined in [94]) during the
voltage sag. It has been illustrated in section IV that the passive protection settings can be
widened when the proposed controller is employed. Hence those PV inverters could ride through
the voltage sag event as shown in Fig. 4.12. If the unified var controller was not enabled in the
PV systems, the PCC voltages could be much lower and the PV systems may disconnect from
the grid because of the tight passive protection settings.
In the PHIL test, the PV system at aN 844 was replaced with the PV inverter prototype.
The reason for selecting aN 844 is that its reactive power response during voltage sag is more
noticeable. The scale coefficient k in Fig. 4.8 was chosen as 67.5. Fig. 4.13 shows the
experimental waveforms of the instantaneous PCC voltage, inverter output current, PCC voltage
RMS value, and inverter reactive power output. During the voltage sag, the PV inverter output
0.46pu capacitive reactive power to support the grid. At the end of the voltage sag event, the
reactive power output decreased dramatically and even became inductive. This is caused by the
IVC having brought the PCC voltage reference to a low level during the voltage sag. When the
voltage sag ended, the voltage controller tried to track the old voltage reference, thus the reactive
power decreased. When the reactive power was lower than the saturation value of limiter 1, the
voltage reference compensation from the IVC vanished. Finally, the reactive power output was
restored to zero due to the AVC.
87
(a)
(b)
(c)
(d)
Fig. 4.12 Momentary voltage sag test case: RTDS simulation results of (a) node 844 PCC voltages; (b) node 844 reactive power outputs; (c) node 890 PCC voltages and (d) node 890
reactive power outputs.
Fig. 4.13 Momentary voltage sag test case: PHIL experimental waveforms of the hardware PV inverter reactive power output and PCC voltage.
88
4.5.3 Islanding Detection Test Case
The ID test cases were conducted based on a standard test circuit, shown in Fig. 4.14.
There are two reasons of using this circuit instead of the IEEE 34 node test feeder. First, the
circuit given in Fig. 4.14 is a standard inverter anti-islanding test circuit adopted in IEEE std.
1547, IEEE std. 929 and UL 1741. The same circuit was also widely used by researchers
studying ID algorithms [104]-[107]. Second, by changing the RLC load power rating and quality
factor, the circuit can represent the islanding networks formed in the IEEE 34 node test feeder.
As explained in section IV, higher fQ leads to larger NDZ. Therefore a relatively high
5.2=fQ is selected in the following test and the RLC load was adjusted to resonate at 60Hz .
The PV inverter 2 and 3 were used during multiple-PV-inverter ID test cases. The voltage
controller gain was selected to be SXτ21.0 in all the three inverters.
4.5.3.1 Single-PV-inverter ID test. In this test, the PV inverter 1 real power output
matched with the load at 1kW. Fig. 4.15 and Fig. 4.16 show the experimental waveforms during
the islanding event when the proposed controller was disabled and enabled, respectively. In the
two figures, the upper two waveforms are the instantaneous PCC voltage and inverter output
current, and the lower two waveforms are the PCC voltage frequency and inverter output
Fig. 4.14 Islanding detection test circuit.
89
reactive power. From the zoomed view in Fig. 4.15, the PCC voltage amplitude kept nearly the
same before and after the islanding event occured at 3.8s. The PCC voltage frequency dropped to
59.7Hz which was still in the nominal range, hence the islanding network cannot be detected. In
the case when the unified var controller was used, the inverter reactive power output was around
zero in the beginning, as seen from Fig. 4.16, because the PCC voltage was 1.0pu. When the
UDS was switched off at 3.8s, the reactive power output quickly reached to its maximum value
of 0.5pu. Accordingly, the network frequency dropped to 53Hz, which was far beyond the
nominal range.
Fig. 4.15 Single-PV-inverter islanding detection test when the unified var controller
was disabled.
Fig. 4.16 Single-PV-inverter islanding detection test when the unified var controller
was enabled.
4.5.3.2 Multiple-PV-inverter ID test. This test is to demonstrate the coordination of
multiple PV systems during ID. The load was rated at 3kW to match with the PV generated
power from the three inverters. Fig. 4.17 shows the simulation results during the test. The
waveforms of the instantaneous PCC voltage, PCC voltage frequency and reactive power outputs
from the three inverters are provided. It is seen that when islanding occurred, the three inverters
injected capacitive reactive power at the same time. The PCC voltage frequency drifted to
54.5Hz in 2s. Fig. 4.18 provides the PHIL experimental results of the test where the PV inverter
1 was replaced with the PV inverter prototype. When islanding happened, the PV inverter
90
injected 0.5pu reactive power and the PCC voltage frequency dropped to 54Hz. It is noticed that
the reactive power injection in the experiment was faster. This is due to the larger PCC voltage
amplitude deviation at the islanding moment in the experiment. Fig. 4.19 shows the PHIL
experimental waveforms without the unified var controller enabled. The PCC frequency was
stabilized at 59.9Hz when the UDS was switched off, so the islanding network cannot be
detected.
Fig. 4.17 Multiple-PV-inverter islanding detection test when the unified var controller
was enabled: simulation waveforms.
Fig. 4.18 Multiple-PV-inverter islanding detection test when the unified var controller was
enabled: PHIL experimental waveforms.
Fig. 4.19 Multiple-PV-inverter islanding detection test when the unified var controller was disabled: PHIL experimental waveforms.
91
4.6 Summary
Theoretical analysis revealed that the VR and ID functions can be integrated in a PV
inverter by means of real/reactive power control. The unified var controller, composed of the
voltage controller and adaptive voltage reference generator, was presented to achieve the
function integration autonomously. With the proposed controller implemented in the distributed
PV systems, the potential system voltage issues can be mitigated and the false tripping of the PV
systems can be avoided. The feasibility and advantages of the proposed controller were validated
in the RTDS and PHIL testbed. The voltage controller design criterion was provided by
investigating the limitations of VR dynamics based on a single PV system model. The analysis
illustrated that the design criterion is applicable in multiple-PV scenario as well, which was
confirmed by the simulation/PHIL test results. Several design considerations for IVC and AVC
were also given.
92
CHAPTER FIVE
CONCLUSIONS AND FUTURE WORK
5.1 Conclusions
In this dissertation, new cost-effective and high-performance inverter topologies and
advanced inverter control systems were researched and developed for next generation PV
systems.
Firstly, a transformerless PV MIC structure based on cascaded qZSI modules was
presented. The cascaded structure reduced the voltage gain requirement of the MIC, so the front-
end dc-dc converter which is necessary in conventional MICs can be eliminated. The removal of
the dc-dc converter improved the MIC power stage efficiency and reduced the cost. Moreover,
the system reliability was also enhanced due to the qZSI shoot-through capability. Because of
this, it is very suitable for the application of new generation eGaN FETs which have ultra-low
threshold voltage and large reverse bias voltage drop. Small dead time can be selected to increase
the system efficiencies without any damage.
Hardware prototype of the proposed module was developed based on the optimized
design results. The module achieved a peak efficiency 98.06% at 45 V and 140 W input, which
was around 1.5% improvement over the peak efficiency of conventional MICs. The peak
efficiency can be further improved to 98.66% when the quasi-Z-source diode was replaced with
SR. When the high-price eGaN devices are substituted with conventional Si-MOSFETs, the
component cost can be reduced to half of the commercial PV MICs. The module can still achieve
97.41% theoretical peak efficiency.
Secondly, the ground leakage current issue in CMI-based PV system was studied. The
removal of the transformer resulted in galvanic connections among the grid and the separate PV
panels/ strings interfaced with different cascaded inverters. The inter-module leakage current
loop formed among the cascaded inverter modules is a unique feature for PV CMI. It prevents
the existed string inverter leakage current suppression techniques to be directly applied in the PV
CMI. A filter-based leakage current suppression method, which is suitable for the cascaded
inverter with high switching frequency, was presented. It was successfully applied in the PV
93
cascaded qZSIs operated at 100 kHz switching frequency. The method can be extended to the PV
CMIs operated with lower switching frequency by bringing in extra wire connections among the
cascaded modules and the grid output. The suppression filters utilized in the two solutions can be
designed based on the simplified leakage current analytical models. Design examples were
provided and the design results from the derived models were consistent with the simulation
results. Experimental results were provided to validate the effectiveness of the proposed leakage
current solutions.
Finally, an autonomous unified var controller was presented to address the system
voltage issues and unintentional islanding problems associated with the high penetration level of
PV systems. The proposed controller is composed of a voltage controller and an adaptive voltage
reference generator. It can achieve the integration of VR and ID autonomously. With the
proposed controller implemented in the distributed PV systems, the potential system voltage
issues can be mitigated and the false tripping of the PV systems can be avoided. The islanding
detection can be realized with negligible NDZ and no adverse impact on system power quality.
Moreover, there is no interference among multiple PV systems during ID. The voltage controller
design criterion was provided by investigating the limitations of VR dynamics based on a single
PV system model and the influence of the interaction among multiple PV systems on the VR
dynamics. The feasibility and advantages of the proposed controller were validated in the RTDS
and PHIL testbed. Typical scenarios including overvoltage, voltage sag and unintentional
islanding in distribution system with multiple PV systems had been selected and tested.
5.2 Future Work
Based on the research presented above, future work may emphasize on the following:
1) The control system of most CMI-based PV system is usually highly centralized and
relies on high-bandwidth communication system. However, in order to achieve real modular
design, distributed control with cheap low-bandwidth communication is required. The individual
MPPT function with distributed control needs to be investigated when there is partial shading on
PV panels. In order to meet the total ac output voltage requirement, the interaction between boost
function and modulation control among qZSI modules should be considered.
94
2) The operations of the cascaded qZSI modules are dependent to each other. This is
different from the commercial MIC which works independently. Therefore, the fault detection
and fault tolerance capability should be investigated for the proposed PV MIC based on CMIs. It
means that in the event of failure of one cascaded module or even multiple modules, the system
should still be able to output power.
3) Utilization of eGaN device as the SR can highly improve the inverter efficiency. But
the system reliability is reduced due to the high speed switching and the device ultra low
threshold voltage. Inverter damage may occur during the switching transient. Si-MOSFET is
recommended to replace the eGaN device for SR to enhance the system reliability.
4) The modified IEEE 34 node test feeder was used as the testing environment to test the
proposed unified var controller. It will be more significant if real utility grid model with high
penetration PV systems is employed as the test environment.
95
APPENDIX A
DERIVATION OF THE RELATIONSHIP BETWEEN QPV AND
VPCC
According to Fig. 4.1, the relationship between between PVQ and PCCV is derived as
follows.
( ) ( ) ( )
( ) ( )[ ]( )( )PCC
ssLPVLPV
ssPCC
LPVLPVPCC
V
jXRjQQjPPV
jXRV
QQjPPVV
++−−−+=
+−∠
−−−+=∠
δδ
δδ
sincos1
1
(A.1)
The amplitude of PCCv can be calculated approximately by
( )( )
( )( )PCC
SSLPV
PCC
SSLPVPCC
V
RXQQ
V
XRPPVV
δδ
δδ
sincos
sincos1
+−+
−−+≅
(A.2)
For the two-PV system shown in Fig. 4.6, the network model is derived as follows.
( ) ( ) ( ) ( )( )
( ) ( )[ ]( )( )
( ) ( )[ ]( )( )PCCj
sisijjLjPVjLjPVj
PCCi
sisiiiLiPViLiPVi
sisijPCCj
LjPVjLjPVj
iPCCi
LiPViLiPViiPCCi
V
jXRjQQjPP
V
jXRjQQjPPV
jXRV
QQjPP
V
QQjPPVV
++−−−+
++−−−+=
+
−∠
−−−+
−∠
−−−+=∠
δδ
δδ
δδδ
sincos
sincos1
1
(A.3)
By assuming 1coscos ≈≈ ji δδ and 0sinsin ≈≈ ji δδ , the amplitude of PCCiv can be
calculated approximately by
( )
( )PCCj
siPVj
PCCi
siPVi
PCCj
siLjsiLjPVj
PCCi
siLisiLiPViPCCi
V
XQ
V
XQ
V
XQRPP
V
XQRPPVV
++−−
+
−−+≅ 1
(A.4)
Similarly,
96
( ) ( ) ( )sjsjjPCCj
LjPVjLjPVjPCCijPCCj jXR
V
QQjPPvV +
−∠
−−−+=∠
δδ (A.5)
( )PCCj
sjPVj
PCCj
sjLjsjLjPVjPCCiPCCj
V
XQ
V
XQRPPVV +
−−+≅ (A.6)
97
APPENDIX B
INFLUENCE OF THE CURRENT CONTROL LOOP ON THE
VOLTAGE CONTROL LOOP
When the current control loop is assumed to be ideal, the loci of the voltage controller
poles are redrawn to be compared with the complete system.
It is noticed that the two curves share the same loci along the real-axis segment. The
breakaway points at the real axis of the two curves are both at τ21
−=s . The IK values at the
breakaway point are calculated as follows:
( )MX
VK n
I += 14τ
for the complete model (B.1)
X
VK n
I τ4= for the simplified model (B.2)
where )2(4
)2(
2cPWMPC
fcs
KK
LM
τττ
τττ
−
−= .
Fig. B.1 Root locus comparison of the complete model and simplified model.
98
With typical current control design [98], M is usually much smaller than 1. For the
system in Table 4.1, it is 0019.0=M . Therefore, when the voltage controller poles are designed
to be positioned on the real axis, the current control loop can be considered to be ideal if only the
voltage dynamic is concerned.
99
REFERENCES
[1] L. Sherwood, "U.S. Solar Market Trends 2011," Interstate Renewable energy Council, Latham, NY, Aug. 2012.
[2] K. Ardani, "National Survey Report of PV Power Applications in the United States 2011," National Renewable Energy Laboratory, Washington, Jun. 2012.
[3] S. Hegedus, "Thin film solar modules: The low cost, high throughput and versatile alternative to si wafers," Prog Photovoltaics Res Appl, vol. 14, no. 5, pp. 393-411, 2006.
[4] L. Liu, H. Li and Y. Xue, "A coordinated active and reactive power control strategy for grid-connected cascaded photovoltaic (PV) system in high voltage high power applications," in Proc. IEEE APEC, Mar. 17-21, 2013, pp. 1301-1308.
[5] M. Calais and V.G. Agelidis, "Multilevel converters for single-phase grid connected photovoltaic systems-an overview," in Industrial Electronics, 1998. Proceedings. ISIE '98. IEEE International Symposium on, 1998, pp. 224-229 vol.1.
[6] S. Essakiappan, H.S. Krishnamoorthy, P. Enjeti, R.S. Balog and S. Ahmed, "Independent control of series connected utility scale multilevel photovoltaic inverters," in Proc. IEEE ECCE, Sep. 15-20, 2012, pp. 1760-1766.
[7] S. Rivera, S. Kouro, B. Wu, J.I. Leon, J. Rodriguez and L.G. Franquelo, "Cascaded H-bridge multilevel converter multistring topology for large scale photovoltaic systems," in Proc. IEEE ISIE, Jun. 27-30, 2011, pp. 1837-1844.
[8] E. Villanueva, P. Correa, J. Rodriguez and M. Pacas, "Control of a single-phase cascaded H-bridge multilevel inverter for grid-connected photovoltaic systems," IEEE Trans. Ind. Electron., vol. 56, no. 11, pp. 4399-4406, Nov. 2009.
[9] F. Filho, Yue Cao and L.M. Tolbert, "11-Level cascaded H-bridge grid-tied inverter interface with solar panels," in Proc. IEEE APEC, Feb. 21-25, 2010, pp. 968-972.
[10] X. Bailu, F. Filho and L.M. Tolbert, "Single-phase cascaded H-bridge multilevel inverter with nonactive power compensation for grid-connected photovoltaic generators," in Proc. IEEE ECCE, Sep. 17-22, 2011, pp. 2733-2737.
[11] S.A. Khajehoddin, A. Bakhshai and P. Jain, "The Application of the Cascaded Multilevel Converters in Grid Connected Photovoltaic Systems," in Proc. IEEE Canada Electrical Power Conference, Oct. 25-26, 2007, pp. 296-301.
100
[12] O. Alonso, P. Sanchis, E. Gubia and L. Marroyo, "Cascaded H-bridge multilevel converter for grid connected photovoltaic generators with independent maximum power point tracking of each solar array," in Proc. IEEE PESC, Jun. 15-19, 2003, pp. 731-735 vol.2.
[13] C. Cecati, F. Ciancetta and P. Siano, "A multilevel inverter for photovoltaic systems with fuzzy logic control," IEEE Trans. Ind. Electron., vol. 57, no. 12, pp. 4115-4125, Dec. 2010.
[14] M. Calais, V.G. Agelidis and M.S. Dymond, "A cascaded inverter for transformerless single-phase grid-connected photovoltaic systems," Renewable Energy, vol. 22, no. 1, pp. 255-262, Jan. 2001.
[15] J.J. Negroni, F. Guinjoan, C. Meza, D. Biel and P. Sanchis, "Energy-Sampled Data Modeling of a Cascade H-Bridge Multilevel Converter for Grid-connected PV Systems," in Proc. IEEE International Power Electronics Congress, Oct. 16-18, 2006, pp. 1-6.
[16] G. Brando, A. Dannier and R. Rizzo, "A Sensorless Control of H-bridge Multilevel Converter for Maximum Power Point Tracking in Grid Connected Photovoltaic Systems," in Proc. IEEE ICCEP, May 21-23, 2007, pp. 789-794.
[17] X. Lu, K. Sun, Y. Ma, L. Huang and S. Igarashi, "High efficiency hybrid cascade inverter for photovoltaic generation," in Proc. IEEE TENCON, Jan. 23-26, 2009, pp. 1-6.
[18] L. Liu, H. Li, Z. Wu and Y. Zhou, "A cascaded photovoltaic system integrating segmented energy storages with self-regulating power allocation control and wide range reactive power compensation," IEEE Trans. Power Electron., vol. 26, no. 12, pp. 3545-3559, Dec. 2011.
[19] Y. Zhou, L. Liu and H. Li, "A high-performance photovoltaic module-integrated converter (MIC) based on cascaded quasi-Z-source inverters (qZSI) using eGaN FETs," IEEE Trans. Power Electron., vol. 28, no. 6, pp. 2727-2738, Jun. 2013.
[20] L. Liu, H. Li, Y. Zhao, X. He and Z.J. Shen, "1 MHz cascaded Z-source inverters for scalable grid-interactive photovoltaic (PV) applications using GaN device," in Proc. IEEE ECCE, Sep. 17-22, 2011, pp. 2738-2745.
[21] D. Sun, B. Ge, F.Z. Peng, A.R. Haitham, D. Bi and Y. Liu, "A new grid-connected PV system based on cascaded H-bridge quasi-Z source inverter," in Proc. IEEE ISIE, May 28-31, 2012, pp. 951-956.
[22] Y. Liu, B. Ge, H. Abu-Rub and F.Z. Peng, "A modular multilevel space vector modulation for photovoltaic quasi-Z-source cascade multilevel inverter," in Proc. IEEE APEC, Mar. 17-21, 2013, pp. 714-718.
[23] J. Strydom and A. Lidow. (Mar. 2011). Driving eGaN transistors for maximum performance [Online]. available: http://www.digikey.com/Web%20Export/Supplier%20Content/EfficientPowerConversion_917/PDF/EPC_Driving_eGaN_Transistors.pdf?redirected=1.
101
[24] Z. Liang, B. Lu, J.D. van Wyk and F.C. Lee, "Integrated CoolMOS FET/SiC-diode module for high performance power switching," IEEE Trans. Power Electron., vol. 20, no. 3, pp. 679-686, May 2005.
[25] D. Reusch, D. Gilham, Yipeng Su and F.C. Lee, "Gallium Nitride based 3D integrated non-isolated point of load module," in Applied Power Electronics Conference and Exposition (APEC), 2012 Twenty-Seventh Annual IEEE, 2012, pp. 38-45.
[26] M.J. Scott, Ke Zou, Jin Wang, Chingchi Chen, Ming Su and Lihua Chen, "A gallium-nitride switched-capacitor circuit using synchronous rectification," in Energy Conversion Congress and Exposition (ECCE), 2011 IEEE, 2011, pp. 2501-2505.
[27] J. Strydom. (2010, Sep.). eGaNTM-Silicon Power Shoot-Out: Comparing Figure of Merit (FOM) [Online]. available: http://www.ed-china.com/ARTICLE_IMAGES/201106/20110620_IC_ICD_TS_54.PDF?SOURCES=DOWNLOAD.
[28] Department of Energy. (2010, Sep. 07). Department of Energy Announces $8.5 Million to Advance Solar Energy Grid Integration Systems [Online]. available: http://energy.gov/articles/department-energy-announces-85-million-advance-solar-energy-grid-integration-systems.
[29] EPRI. (2011, Jan. 24). EPRI Continues Research on Photovoltaic & Grid Storage Integration Program [Online]. available: http://www.china-power-transformer.com/EPRI-Continues-Research-on-Photovoltaic-Grid-Storage-Integration-Program-28.html.
[30] IEA. Homepage of IEA-PVPS [Online]. available: http://www.iea-pvps.org/index.php?id=1.
[31] R. Hudson, "PV Inverters with VAR Control, LVRT, and Dynamic Control," BEW Engineering, High Penetration Photovoltaics Workshop, Denver, CO, May 2010.
[32] W. Bower and M. Ropp, "Evaluation of Islanding Detection Methods for Photovoltaic Utility-Interactive Power Systems," International Energy Agency, Photovoltaic Power Systems Program, Rep. Rep. IEA-PVPS T5-09, Mar. 2002.
[33] SolarBridge Technologies. (2012). Pantheon II Integrated Microinverter [Online]. available: http://solarbridgetech.com/wp-content/uploads/2012/07/sb-pantheon-ii-datasheet.pdf.
[34] H. Oldenkamp and I. de Jong, "The return of the AC-module inverter," in 24th European Photovoltaic Solar Energy Conference, Hamburg, Germany, 2009, pp. 1-4.
[35] Power One. (2011, Feb. 02). Aurora Microinverter [Online]. available: http://www.power-one.com/sites/power-one.com/files/micro-0.25_0.3-i_en_3.pdf.
102
[36] Enphase Energy. M215 - Mircoinverter [Online]. available: http://enphase.com/wp-uploads/enphase.com/2011/10/Enphase-Datasheet-M215-Microinverter.pdf.
[37] SMA. Homepage of SMA Solar Technology [Online]. available: http://www.sma-america.com/en_US.html;.
[38] A. Wilkins. (2012, Mar. 08). Cost-Benefit of Microinverters vs Maximizers / String Inverters [Online]. available: http://www.renewableenergyworld.com/rea/blog/post/2012/03/cost-benefit-of-microinverters-vs-maximizers-string-inverters.
[39] Q. Li and P. Wolfs, "A review of the single phase photovoltaic module integrated converter topologies with three different DC link configurations," IEEE Trans. Power Electron., vol. 23, no. 3, pp. 1320-1333, May 2008.
[40] E. Wesoff. (2011, Sep. 19). SMA's Microinverter to Land in 2012 [Online]. available: http://www.greentechmedia.com/articles/read/smas-microinverter-to-land-in-2012/.
[41] L. Liu, H. Li, Y. Zhao, X. He and Z.J. Shen, "1 MHz cascaded Z-source inverters for scalable grid-interactive photovoltaic (PV) applications using GaN device," in Energy Conversion Congress and Exposition (ECCE), 2011 IEEE, 2011, pp. 2738-2745.
[42] Yi Huang, Miaosen Shen, F.Z. Peng and Jin Wang, "Z-source inverter for residential photovoltaic systems," IEEE Trans. Power Electron., vol. 21, no. 6, pp. 1776-1782, Nov. 2006.
[43] J. Anderson and F.Z. Peng, "Four quasi-Z-Source inverters," in Power Electronics Specialists Conference, 2008. PESC 2008. IEEE, 2008, pp. 2743-2749.
[44] Fairchild. (2006, Jan. 04). Synchronous buck MOSFET loss calculations with Excel model [Online]. available: http://www.fairchildsemi.com/an/AN/AN-6005.pdf.
[45] Colonel Wm. T. McLyman, Transformer and inductor design handbook, 3rd ed. Idyllwild, CA, Kg Magnetics Inc., 2004.
[46] J. Strydom. The eGaN FET-silicon power shoot-out: 2: drivers, layout [Online]. available: http://powerelectronics.com/images/eGanFetSiliconPower.pdf.
[47] Youhao Xi, Min Chen, K. Nielson and R. Bell, "Optimization of the drive circuit for enhancement mode power GaN FETs in DC-DC converters," in Applied Power Electronics Conference and Exposition (APEC), 2012 Twenty-Seventh Annual IEEE, 2012, pp. 2467-2471.
[48] National Semiconductor. 5A, 100V Half-Bridge Gate Driver for Enhancement Mode GaN FETs [Online]. available: http://www.ti.com/lit/ds/symlink/lm5113.pdf.
103
[49] M. Shen, A. Joseph, Y. Huang, F.Z. Peng and Z. Qian, "Design and Development of a 50kW Z-Source Inverter for Fuel Cell Vehicles," in Proc. Int. Conf. Power Electroni. Motion Control, Aug. 14-16, 2006, pp. 1-5.
[50] F. Baumgartner, H. Schmidt, B. Burger, R. Brundlinger, H. Haberlin and M. Zehner, "Status and relevance of the dc voltage dependency of the inverter efficiency," in 22nd European Photovoltaic Solar Energy Conference and Exhibition, Sep. 2007, pp. 1-7.
[51] Yokogawa Electric Corporation. Power Analyzer Accuracy and Basic Uncertainty Calculator [Online]. available: http://tmi.yokogawa.com/us/service-support/faqs/power-analyzer-accuracy-and-basic-uncertainty-calculator/.
[52] D. Cruz Martins and R. Demonti, "Photovoltaic energy processing for utility connected system," in Industrial Electronics Society, 2001. IECON '01. The 27th Annual Conference of the IEEE, 2001, pp. 1965-1969 vol.3.
[53] N. Kasa, T. Iida and A.K.S. Bhat, "Zero-Voltage Transition Flyback Inverter for Small Scale Photovoltaic Power System," in Power Electronics Specialists Conference, 2005. PESC '05. IEEE 36th, 2005, pp. 2098-2103.
[54] A. Fernandez, J. Sebastian, M.M. Hernando, M. Arias and G. Perez, "Single Stage Inverter for a Direct AC Connection of a Photovoltaic Cell Module," in Power Electronics Specialists Conference, 2006. PESC '06. 37th IEEE, 2006, pp. 1-6.
[55] J. Shuai, C. Dong, F.Z. Peng and Y. Li, "Grid-connected boost-half-bridge photovoltaic micro inverter system using repetitive current control and maximum power point tracking," in Applied Power Electronics Conference and Exposition (APEC), 2012 Twenty-Seventh Annual IEEE, 2012, pp. 590-597.
[56] Q. Li and P. Wolfs, "The power loss optimization of a current fed ZVS two-inductor boost converter with a resonant transition gate drive," IEEE Trans. Power Electron., vol. 21, no. 5, pp. 1253-1263, Sep. 2006.
[57] L. Yan and B. Lehman, "An integrated magnetic isolated two-inductor boost converter: Analysis, design and experimentation," IEEE Trans. Power Electron., vol. 20, no. 2, pp. 332-342, Mar. 2005.
[58] A. Lohner, T. Meyer and A. Nagel, "A new panel-integratable inverter concept for grid-connected photovoltaic systems," in Industrial Electronics, 1996. ISIE '96., Proceedings of the IEEE International Symposium on, 1996, pp. 827-831 vol.2.
[59] C. Prapanavarat, M. Barnes and N. Jenkins, "Investigation of the performance of a photovoltaic AC module," Generation, Transmission and Distribution, IEE Proceedings-, vol. 149, no. 4; given. Throughout, the choices of system components are supported with analysis and simulation, as well as experimental tests using a solar emulator test system, pp. 472-478, 2002.
104
[60] D. Holmes and T. Lipo, "Carrier-based PWM of multilevel inverters," in Pulse Width Modulation for Power Converters: Principles and Practice, Anonymous . Hoboken, NJ: Wiley-IEEE Press, 2003, pp. 95-153.
[61] E. Gubía, P. Sanchis, A. Ursúa, J. López and L. Marroyo, "Ground currents in single-phase transformerless photovoltaic systems," Prog Photovoltaics Res Appl, vol. 15, no. 7, pp. 629-650, Nov. 2007.
[62] H. Xiao and S. Xie, "Leakage current analytical model and application in single-phase transformerless photovoltaic grid-connected inverter," IEEE Trans. Electromagn. Compat., vol. 52, no. 4, pp. 902-913, Nov. 2010.
[63] M.C. Poliseno, R.A. Mastromauro and M. Liserre, "Transformer-less photovoltaic (PV) inverters: A critical comparison," in Proc. IEEE ECCE, Sep. 15-20, 2012, pp. 3438-3445.
[64] D. Dong, F. Luo, D. Boroyevich and P. Mattavelli, "Leakage current reduction in a single-phase bidirectional AC–DC full-bridge inverter," IEEE Trans. Power Electron., vol. 27, no. 10, pp. 4281-4291, Oct. 2012.
[65] Y. Koyama, J. Tsuda and H. Mochikawa, "Grid-tie inverter," U.S. patent 2012/0275201 A1, Jul 12, 2012.
[66] A.K. Gupta and A.M. Khambadkone, "A space vector modulation scheme to reduce common mode voltage for cascaded multilevel inverters," IEEE Trans. Power Electron., vol. 22, no. 5, pp. 1672-1681, Sep. 2007.
[67] D.A. Rendusara, E. Cengelci, P.N. Enjeti, V.R. Stefanovic and J.W. Gray, "Analysis of common mode voltage-“neutral shift” in medium voltage PWM adjustable speed drive (MV-ASD) systems," IEEE Trans. Power Electron., vol. 15, no. 6, pp. 1124-1133, Nov. 2000.
[68] R. Lai, M.H. Todorovic and J. Sabate, "Analysis and suppression of a common mode resonance in the cascaded H-bridge multilevel inverter," in Proc. IEEE Energy Convers. Congr. Expo., Sep. 12–16, 2010, pp. 4564-4568.
[69] Z. Ye, D. Boroyevich, J. Choi and F.C. Lee, "Control of circulating current in two parallel three-phase boost rectifiers," IEEE Trans. Power Electron., vol. 17, no. 5, pp. 609-615, Sep. 2002.
[70] Y. Liao, H. Chen and H. Cheng, "Common mode and differential mode circulating-current control in paralleled single-phase boost rectifiers," in Proc. IEEE APEC, Mar. 17-21, 2013, pp. 361-367.
[71] T. Kerekes, R. Teodorescu, P. Rodriguez, G. Vazquez and E. Aldabas, "A new high-efficiency single-phase transformerless PV inverter topology," IEEE Trans. Ind. Electron., vol. 58, no. 1, pp. 184-191, Jan. 2011.
105
[72] "Automatic disconnection device between a generator and the public low-voltage grid," Standard DIN V VDE V 0126-1-1, 2006.
[73] T. Kerekes, R. Teodorescu and U. Borup, "Transformerless Photovoltaic Inverters Connected to the Grid," in Proc. IEEE APEC, Feb. 25 - Mar. 1, 2007, pp. 1733-1737.
[74] B. Kroposki, R. Margolis, G. Kuswa, J. Torres, W. Bower, T. Key and D. Ton, "Renewable Systems Interconnection: Executive Summary," National Renewable Research Laboratory, U.S. Department of Energy, Golden, Colorado, Rep. Tech. Rep. NREL/TP-581-42292, Feb. 2008.
[75] T. Ehara, "Overcoming PV grid issues in urban areas," International Energy Agency, Photovoltaic Power Systems Program, Rep. IEA-PVPS T10-06-2009, Oct. 2009.
[76] R. Hara, H. Kita, T. Tanabe, H. Sugihara, A. Kuwayama and S. Miwa, "Testing the technologies," Power and Energy Magazine, IEEE, vol. 7, no. 3, pp. 77-85, 2009.
[77] E. Liu and J. Bebic, "Distribution System Voltage Performance Analysis for High-Penetration Photovoltaics," GE Global Research, Niskayuna, NY, Rep. NREL/SR-591-42298, Feb. 2008.
[78] A. Woyte, V. Van Thong, R. Belmans and J. Nijs, "Voltage fluctuations on distribution level introduced by photovoltaic systems," IEEE Trans. Energy Convers., vol. 21, no. 1, pp. 202-209, Mar. 2006.
[79] J.D. Kueck, B.J. Kirby, L.M. Tolbert and D.T. Rizy, "Tapping distributed energy resources: Reactive power is the key to an efficient and reliable grid," Public Utilities Fortnightly, vol. 142, no. 9, pp. 47-51, Sep. 2004.
[80] E. Demirok, D. Sera, R. Teodorescu, P. Rodriguez and U. Borup, "Evaluation of the voltage support strategies for the low voltage grid connected PV generators," in Energy Conversion Congress and Exposition (ECCE), 2010 IEEE, 2010, pp. 710-717.
[81] B. Seal, "Specification for Smart Inverter Interactions with the Electric Grid Using International Electrotechnical Commission 61850," Electric Power Research Institute, Rep. Tech. Rep. 1021674, Oct. 2010.
[82] H. Li, F. Li, Y. Xu, D.T. Rizy and J.D. Kueck, "Adaptive voltage control with distributed energy resources: Algorithm, theoretical analysis, simulation, and field test verification," IEEE Trans. Power Syst., vol. 25, no. 3, pp. 1638-1647, Aug. 2010.
[83] Y.A.-.I. Mohamed and E.F. El Saadany, "Hybrid variable-structure control with evolutionary optimum-tuning algorithm for fast grid-voltage regulation using inverter-based distributed generation," IEEE Trans. Power Electron., vol. 23, no. 3, pp. 1334-1341, May 2008.
106
[84] P. Du, Z. Ye, E.E. Aponte, J.K. Nelson and L. Fan, "Positive-feedback-based active anti-islanding schemes for inverter-based distributed generators: Basic principle, design guideline and performance analysis," IEEE Trans. Power Electron., vol. 25, no. 12, pp. 2941-2948, Dec. 2010.
[85] "IEEE recommended practice for monitoring electric power quality," IEEE Std 1159-2009 (Revision of IEEE Std 1159-1995), pp. c1-81 2009.
[86] P.M.S. Carvalho, P.F. Correia and L.A.F. Ferreira, "Distributed reactive power generation control for voltage rise mitigation in distribution networks," IEEE Trans. Power Syst., vol. 23, no. 2, pp. 766-772, May 2008.
[87] L.A.C. Lopes and Y. Zhang, "Islanding detection assessment of multi-inverter systems with active frequency drifting methods," IEEE Trans. Power Del., vol. 23, no. 1, pp. 480-486, Jan. 2008.
[88] X. Wang, W. Freitas, V. Dinavahi and W. Xu, "Investigation of positive feedback anti-islanding control for multiple inverter-based distributed generators," IEEE Trans. Power Syst., vol. 24, no. 2, pp. 785-795, May 2009.
[89] H.H. Zeineldin, E.F. El-Saadany and M.M.A. Salama, "Impact of DG interface control on islanding detection and nondetection zones," IEEE Trans. Power Del., vol. 21, no. 3, pp. 1515-1523, Jul. 2006.
[90] Y. Zhou, L. Liu and H. Li, "Autonomous control integrating fast voltage regulation and islanding detection for high penetration PV application," in Proc. IEEE APEC, Mar. 6-11, 2011, pp. 606-612.
[91] W.H. Kersting. IEEE Radial Test Feeders [Online]. available: http://ewh.ieee.org/soc/pes/dsacom/testfeeders.html.
[92] "IEEE recommended practice for utility interface of photovoltaic (PV) systems," IEEE Std 929-2000, pp. i 2000.
[93] A. Woyte, K.D. Brabandere, D.V. Dommelen, R. Belmans and J. Nijs, "International harmonization of grid connection guidelines: Adequate requirements for the prevention of unintentional islanding," Progr. Photovoltaics, Res. Appl., vol. 11, pp. 407-424, 2003.
[94] "IEEE standard for interconnecting distributed resources with electric power systems," IEEE Std 1547-2003, pp. 1-16 2003.
[95] M.E. Baran and I.M. El-Markabi, "A multiagent-based dispatching scheme for distributed generators for voltage support on distribution feeders," IEEE Trans. Power Syst., vol. 22, no. 1, pp. 52-59, Feb. 2007.
107
[96] Youbin Peng, D. Vrancic and R. Hanus, "Anti-windup, bumpless, and conditioned transfer techniques for PID controllers," Control Systems, IEEE, vol. 16, no. 4, pp. 48-57, 1996.
[97] R. Zhang, M. Cardinal, P. Szczesny and M. Dame, "A grid simulator with control of single-phase power converters in D-Q rotating frame," in Power Electronics Specialists Conference, 2002. pesc 02. 2002 IEEE 33rd Annual, 2002, pp. 1431-1436 vol.3.
[98] D.G. Holmes, T.A. Lipo, B.P. McGrath and W.Y. Kong, "Optimized design of stationary frame three phase AC current regulators," IEEE Trans. Power Electron., vol. 24, no. 11, pp. 2417-2426, Nov. 2009.
[99] Jian Sun, "Impedance-based stability criterion for grid-connected inverters," IEEE Trans. Power Electron., vol. 26, no. 11, pp. 3075-3078, Nov. 2011.
[100] L. Harnefors, M. Bongiorno and S. Lundberg, "Input-admittance calculation and shaping for controlled voltage-source converters," IEEE Trans. Ind. Electron., vol. 54, no. 6, pp. 3323-3334, Dec. 2007.
[101] Z. Ye, A. Kolwalkar, Y. Zhang, P. Du and R. Walling, "Evaluation of anti-islanding schemes based on nondetection zone concept," in Power Electronics Specialist Conference, 2003. PESC '03. 2003 IEEE 34th Annual, 2003, pp. 1735-1741 vol.4.
[102] W. Ren, M. Steurer and T.L. Baldwin, "Improve the stability and the accuracy of power hardware-in-the-loop simulation by selecting appropriate interface algorithms," IEEE Trans. Ind. Appl., vol. 44, no. 4, pp. 1286-1294, Jun. 2008.
[103] M. Steurer, C.S. Edrington, M. Sloderbeck, W. Ren and J. Langston, "A megawatt-scale power hardware-in-the-loop simulation setup for motor drives," IEEE Trans. Ind. Electron., vol. 57, no. 4, pp. 1254-1260, Apr. 2010.
[104] J. Kim, J. Kim, Y. Ji, Y. Jung and C. Won, "An islanding detection method for a grid-connected system based on the goertzel algorithm," IEEE Trans. Power Electron., vol. 26, no. 4, pp. 1049-1055, Apr. 2011.
[105] D. Velasco, C. Trujillo, G. Garcera and E. Figueres, "An active anti-islanding method based on phase-PLL perturbation," IEEE Trans. Power Electron., vol. 26, no. 4, pp. 1056-1066, Apr. 2011.
[106] A. Yafaoui, Bin Wu and S. Kouro, "Improved active frequency drift anti-islanding detection method for grid connected photovoltaic systems," IEEE Trans. Power Electron., vol. 27, no. 5, pp. 2367-2375, May 2012.
[107] H.H. Zeineldin, "A Q-f droop curve for facilitating islanding detection of inverter-based distributed generation," IEEE Trans. Power Electron., vol. 24, no. 3, pp. 665-673, Mar. 2009.
108
BIOGRAPHICAL SKETCH
Yan Zhou received the B.S. and M.S. in Electrical Engineering from Huazhong
University of Science and Technology, China in 2007 and 2009, respectively. He started his
Ph.D. program in Department of Electrical and Computer Engineering at the Florida State
University from July 2009. Meanwhile, he worked as a graduate research assistant at Center for
Advanced Power Systems (CAPS). His research interests include grid-connected PV system
control, PV micro-inverter, post-silicon device application and high PV penetration integration
issues.
He has six journal and conference publications listed below since 2009.
[1] Yan Zhou, Liming Liu, and Hui Li, “A High Performance Photovoltaic Module-Integrated
Converter (MIC) Based on Cascaded Quasi-Z-Source Inverters (qZSI) using eGaN FETs,” IEEE
Trans. Power Electron., vol.28, no.6, pp.2727-2738, Jun. 2013.
[2] Yan Zhou, Hui Li, and Liming Liu, “Integrated Autonomous Voltage Regulation and
Islanding Detection for High Penetration PV Applications,” IEEE Trans. Power Electron.,
vol.28, no.6, pp.2826-2841, Jun. 2013.
[3] Liming Liu, Hui Li, Zhichao Wu, and Yan Zhou, “A Cascaded Photovoltaic System
Integrating Segmented Energy Storages With Self-Regulating Power Allocation Control and
Wide Range Reactive Power Compensation,” IEEE Trans. Power Electron., vol.26, no.12,
pp.3545-3559, Dec. 2011.
[4] Yan Zhou, Liming Liu, and Hui Li, “High Efficiency Cascaded Quasi-Z-Source
Photovoltaic Inverter Module using eGaN FETs,” IEEE Energy Conversion Congress and Expo
(ECCE), 2012, Raleigh, NC, USA, pp. 1615-1621.
[5] Yan Zhou, Liming Liu, and Hui Li, “Autonomous Control Integrating Fast Voltage
Regulation and Islanding Detection for High Penetration PV Application,” IEEE Applied Power
Electronics Conference and Exposition (APEC) 2011, Fort Worth, TX, USA, pp. 606-612.
[6] Yan Zhou, Liming Liu, Hui Li, and Lei Wang, "Real time digital simulation (RTDS) of a
novel battery-integrated PV system for high penetration application," IEEE International
Symposium on Power Electronics for Distribution Generation Systems (PEDG), 2010, pp. 786 –
790.
![Encrypted Search: Leakage Suppression - Brown University · 2019. 10. 4. · How Should we Handle Leakage? • Approach #3: Rebuild [K.14] • Rebuild encrypted structure after t](https://img.dokumen.tips/doc/110x75/61424cd255c1d11d1b341b71/encrypted-search-leakage-suppression-brown-university-2019-10-4-how-should.jpg)
![Surface Erosion Studies on Polymer Insulators Used for High ......IEC-60587, 2007. [5] S. Kumagai, “Leakage current suppression and resistance to tracking and erosion of HTV silicone](https://img.dokumen.tips/doc/110x75/613b3d6bf8f21c0c8268e3a5/surface-erosion-studies-on-polymer-insulators-used-for-high-iec-60587-2007.jpg)
