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JK, T, and D Flip-Flops
Dept. of CSIE, Fu Jen Catholic UniversityCAD Laboratory
(SF-640)2010/5
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JK Flip-Flop with Synchronous Reset
Input J, K, Clock, and Reset (Active Low)
Output
Function Table positive-edge triggered
Qand Q
2011/5/2 2
J K Qn
0 0 Q
0 1 0
1 0 1
1 1 Q
J Q
K >clk Q
Reset
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Verilog Code for JK Flip-Flop (Behavioral Modeling)(1/3)module
JK-FF-B(); // behavioral style
always @(posedge Clock) begin // positive-edge triggered
if (!Reset) // synchronous reset, active lowQ
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Verilog Code for JK Flip-Flop (Behavioral Modeling)(2/3)always
@(posedge Clock) begin // positive-edge triggered
if (!Reset) // synchronous reset, active lowQ
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Verilog Code for JK Flip-Flop (Behavioral Modeling)(3/3)always
@(posedge Clock) begin // positive-edge triggered
if (!Reset) // synchronous reset, active lowQ
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Verilog Code for JK Flip-Flop (Dataflow Modeling)module
JK-FF-D(); // dataflow style
wire Qn; // the next state Qnalways @(posedge Clock) begin
if (!Reset) // synchronous reset, active lowQ
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T Flip-Flop with Asynchronous Preset
Input T, Clock, and Preset (Active High)
Output
Function Table negative-edge triggered
Qand Q
2011/5/2 7
T Qn
0 Q
T Q
>clk Q
Preset1 Q
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Verilog Code for T Flip-Flop (Behavioral Modeling)(1/3)module
T-FF-B(T, Preset, Clock, Q, Qbar); // behavioral style
always @(negedge Clock or posedge Preset) begin //negative-edge
triggered
if (Preset) // asynchronous preset, active highQ
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Verilog Code for T Flip-Flop (Behavioral Modeling)(2/3)
always @(negedge Clock or posedge Preset) begin //negative-edge
triggered
if (Preset) // asynchronous preset, active highQ
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Verilog Code for T Flip-Flop (Behavioral Modeling)(3/3)always
@(negedge Clock or posedge Preset) begin // positive-edge
triggered
if (Preset) // asynchronous preset, active highQ
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Verilog Code for T Flip-Flop (Dataflow Modeling)module T-FF-D(T,
Prest, Clock, Q, Qbar); // dataflow style
wire Qn; // the next state Qnalways @(negedge Clock or posedge
Preset)// negative-edge triggered
if (Preset) // asynchronous preset , active highQ
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D Flip-Flop with Synchronous Reset and Preset
Input D, Clock, Reset and Preset (both Active Low)
Output
Function Table positive-edge triggered
Qand Q
2011/5/2 12
Reset Preset D Qn Qn
0 X X 0 1
D Q
>clk Q
Preset
Reset
1 0 X 1 0
1 1 0 0 1
1 1 1 1 0
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Verilog Code for D Flip-Flop (Behavioral Modeling)
Exercised by students
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Verilog Code for D Flip-Flop (Dataflow Modeling)
Exercised by students
2011/5/2 14
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Functional Simulation of Flip-Flops
Exercised by students. Compare the simulation results for
each
type of flip-flops modeled by behavioral and dataflow modeling.
Add a XOR gate which connects the outputs
of two flip-flops (e.x. T-FF-B and T-FF-D). (See Next Slide) It
should be 0 for all input values of T and Preset.
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Checking the Output Difference of Two Flip-Flops Logic schematic
for checking the equivalence of
two T flip-flops. The other types of flip-flops can be checked
in the same way.
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T QDataflow
>clk Q
T QBehavioral
>clk Q
Preset
T F
Clock
JK, T, and D Flip-FlopsJK Flip-Flop with Synchronous
ResetVerilog Code for JK Flip-Flop (Behavioral
Modeling)(1/3)Verilog Code for JK Flip-Flop (Behavioral
Modeling)(2/3)Verilog Code for JK Flip-Flop (Behavioral
Modeling)(3/3)Verilog Code for JK Flip-Flop (Dataflow Modeling)T
Flip-Flop with Asynchronous PresetVerilog Code for T Flip-Flop
(Behavioral Modeling)(1/3)Verilog Code for T Flip-Flop (Behavioral
Modeling)(2/3)Verilog Code for T Flip-Flop (Behavioral
Modeling)(3/3)Verilog Code for T Flip-Flop (Dataflow Modeling)D
Flip-Flop with Synchronous Reset and PresetVerilog Code for D
Flip-Flop (Behavioral Modeling)Verilog Code for D Flip-Flop
(Dataflow Modeling)Functional Simulation of Flip-FlopsChecking the
Output Difference of Two Flip-Flops
