First Principle Simulations of Various Magnetic Tunnel Junctions $\kern-2pt$ for$\kern-2pt$ Applications in Magnetoresistive Random Access Memories

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Abstract— This paper reports the First Principle simulations

of Fe/MgO/Fe, Fe/Y2O3/Fe, Fe/HfO2/Fe and Fe/Al2O3/Fe

Magnetic Tunnel Junctions (MTJs). From the device level and

circuit level simulations carried out in this work, the Fe/MgO/Fe

configuration has been found to be the best. From the device level

simulations, all the four configurations of MTJs have been

compared with regards to the bias dependence of Tunnel

Magnetoresistance Ratios (TMR), insulator thickness dependence

of TMR and insulator thickness dependence of parallel and anti

parallel state resistances. Finally, from the circuit level

simulations, the static and switching power dissipations have

been computed along with the delay time estimation.

Index Terms— Magnetic Tunnel Junction, Density Functional

Theory (DFT), MRAM, Local Spin Density Approximation

(LSDA)

I. INTRODUCTION

Magnetic Tunnel Junction (MTJ) is a stack of three layers, one on top of the other. The top and the bottom layers are essentially made up of ferromagnetic materials

like Fe, Co, Ni, or even the Heusler alloys [1] and there is an insulating layer sandwiched in between the two ferromagnetic layers. These ferromagnetic layers are thin films with a thickness of around 10 nm. The insulator can be MgO, Al2O3, SiO2 or even the high κ materials like HfO2, ZrO2 etc. [2]. The thickness of the insulating layer is around 2 nm. As the top and bottom layers are ferromagnetic, they possess their own magnetizations respectively. There can be situations when the relative magnetization of the top ferromagnetic layer has parallel or antiparallel alignment with respect to the alignment of magnetization of the bottom ferromagnetic layer. As the insulating layer is very thin, electrons from one ferromagnetic layer can tunnel through to reach the other metal layer when a bias voltage is applied across the MTJ and the tunnel current depends upon the relative orientation of magnetization of the two ferromagnetic layers. This phenomenon is called Spin Dependent Tunneling (SDT) or Spin Polarized Tunneling. The effect was originally discovered in 1975 by M. Jullière

Mayank Chakraverty is with IBM as a System Engineer, working at

Bangalore, India (e-mail: [email protected]) Harish M Kittur is with the School of Electronics Engineering, as a

Professor at VIT University, Vellore, India (e-mail: [email protected]) P. Arun Kumar is with the School of Electronics Engineering, as an

Assistant Professor, at VIT University, Vellore, India (e-mail: [email protected])

(University of Rennes, France) in Fe/Ge-O/Co-junctions at 4.2 K [7]. SDT can be understood in terms of the spin split, i.e. spin up and spin down Density of States (DOS) of the ferromagnetic materials. The MTJs can be used to store binary data in the form of relative magnetization of the ferromagnetic layers and can effectively be used as non volatile memories. Also the read-heads of modern computer hard disk drives work on the basis of magnetic tunnel junctions. When the magnetizations of the two ferromagnetic layers are parallel, it can be said that a low resistance path exists through the MTJ and electrons can tunnel more often through the insulator from the top to the bottom ferromagnetic layer. This state corresponds to writing a bit 0. But when the magnetizations of the two layers are anti parallel, electrons can tunnel less often through the insulator, a high resistance path is said to exist through the MTJ and in such cases, most of the voltage drops across the MTJ. This state corresponds to writing a bit 1. In this way, storing a binary bit (either 1 or 0) can be realized using an MTJ [3, 4, and 5]. This led to the conception and development of MTJ based Magnetoresistive Random Access Memories (MRAMs). An MTJ based MRAM cell consists of a transistor with the MTJ on top of it. It accomplishes the write operation using the MTJ and the read operation is accomplished using a Field Effect Transistor (FET). The FET used in MRAMs is an n-channel MOSFET (NMOS).

The MRAM, primarily because of its non-volatility and secondarily due to lower power requirements, is claimed to be a Universal Memory [3]. The DRAM requires regular refreshing of the memory and both the DRAM and the SRAM lose data on powering down the memory chip. Unlike the DRAM and the SRAM, since the MRAM stores the binary data in the relative magnetization of the two ferromagnetic layers, it remains unaffected by the read operation or even by the intentional or unintentional shutting down of the chip power. The programming/write operation of the MRAM is accomplished by switching the magnetization of the free layer of the MTJ and the read operation is accomplished by activating the NMOS transistor. The most advanced method of switching the magnetization of the free layer is based on spin induced switching wherein a suitable current density from a polarizing layer switches the magnetization of the free layer.

MTJ’s made up of different materials exhibit SDT in various proportions. MTJ’s made up of ferromagnetic

First Principle Simulations of various Magnetic Tunnel Junctions for applications in

Magnetoresistive Random Access Memories

Mayank Chakraverty, Harish M. Kittur, P. Arun Kumar

A



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materials with very high spin polarizations exhibit higher SDT. The first measurements of the spin polarization of some of the ferromagnetic materials were reported in the seminal work of Tedrow and Meservey [6]. In order to quantify the percentage change in the junction resistance, a Tunnel Magnetoresistance Ratio (TMR) has been defined, in terms of the junction resistances in the parallel and the anti-parallel magnetized states RP and RAP respectively as:

%100%100 ×=×∆

=−

AP

PAP

AP R

RR

R

RTMR (1)

II. SIMULATION SET UP

In this paper, four different MTJ configurations have been built and they have been simulated for I-V curves and transmission spectra with both parallel and anti parallel magnetization states separately. The set up used for all the four sets of simulations is shown in Fig. 1. The left electrode is grounded while a bias voltage is applied to the right electrode. The magnetization of the ferromagnetic layers is in the plane perpendicular to the tunnel current. Since the I-V curves are a result of spin polarized electron transport, the exchange correlation used is LSDA (Local Spin Density Approximation). The length of each MTJ is around 30 Ǻ. The insulating layer is 6 atomic layers thick in the (100) direction of the BCC crystal. On an average, the thickness of the insulating layers in each of the four MTJs is of the order of 10 – 12 angstroms, the reason for variation in the thickness of each of the insulating layers from 10 – 12 angstroms is that the type of materials and their atomic sizes that make up the insulating regions in the four MTJs differ. Once the structure is built, the calculation has to be set so as to calculate the I-V characteristics. Here, the calculator used is “ATK-DFT (Device)” with an electron temperature of 300 K. The device configuration in terms of global repetition is 1 × 2 in each of the four MTJs. The total number of atoms comprising each of the six MTJs is 48. The cross sectional areas of the MTJs differ depending upon the lattice constant of the electrode and the atomic radii. As the transport of electrons through the MTJ is essentially due to the availability of electronic states and depends on the direction of orientation of magnetization of the atoms in the two ferromagnetic layers, the exchange correlation selected here is LSDA (Local Spin Density Approximation) as spin polarized transport occurs in MTJs. The mesh cut off chosen for all the six sets of simulations is 150 Rydberg. In the LCAO basis set, the basis type for ferromagnetic atoms is selected to be Single Zeta Polarized while for non ferromagnetic atoms, it is chosen as Double Zeta Polarized. The k point sampling along the X, Y and Z directions have been fixed at 1, 1 and 100 respectively. The left electrode voltage is fixed at 0 V and the positive right electrode voltage is taken for the simulations. To obtain the transmission spectrum the energy range selected in from -5 eV to 5 eV. Simulating each MTJ gives the I-V plot, dI/dV-V and the transmission spectrum of the simulated device. As MTJ involves spin polarized transport, Initial State has to be selected and the spin has to be enabled as User Spin. The

relative spin is 1 for ferromagnetic atoms and 0 for non magnetic atoms. As the system is made up of ferromagnetic material/insulator/ferromagnetic material, the spin of all the ferromagnetic atoms on both side of the insulator have to be fed as 1 representing parallel magnetization of the two magnetic layers thereby resulting in a spin alignment of 1/0/1. To represent anti parallel magnetization, the spin of the bottom half of the ferromagnetic atoms is changed to -1 thereby ending up with a spin alignment of 1/0/-1. The simulations for parallel and anti parallel magnetization have to be carried out separately.

An atomic scale description of an electronic device requires a detailed model of the interaction between the electrons and the individual atoms. At the atomic scale such a description must be based on a quantum mechanical model. The most fundamental description is through the Schrodinger equation involving all the electrons and the ionic cores of the atoms. The main numerical problem with the Schrodinger equation is that it couples the motion of the electrons and this makes a general solution intractable. A very popular strategy for avoiding solving the full Schrodinger equation is using a mean field (MF) model, where each electron is described as an independent particle interacting with the MF from all the other electrons. This is usually calculated through the total electron density and since the electron density is determined from the electron wave functions the MF approach gives rise to a set of coupled equations that must be solved self-consistently. One of the most successful MF approaches is density functional theory (DFT) invented by Kohn and co-workers [12], [13]. In DFT each electron is influenced by a MF determined from the total electron density through a classical electrostatic contribution, the so called Hartree potential, and an additional term, the exchange–correlation potential, which arises from the quantum mechanical nature of the electrons. The exchange–correlation potential can only be calculated approximately, and there is a strong effort to develop new and improved exchange–correlation functionals.

The NEGF-DFT description of electron transport used in the simulations carried out in this paper is based on the Kohn–Sham equations which introduce an equation of motion for each electron through the one-electron Schrodinger equation. The DFT equations have mainly been solved for isolated systems like molecules where fixed boundary conditions can be applied or periodic systems like crystals where it is possible to use periodic boundary conditions. Such a system is called a two-probe system. To treat the two probe system, it is divided into three regions, left electrode, central region and right electrode. It is assumed that the electrode parts have bulk properties and for metallic electrodes this condition is easily met by including a few metallic layers in the central region. The first step in the two-probe technique is to calculate the properties of the electrodes using standard DFT techniques for periodic systems. The solution for the electrodes then sets up boundary conditions for the central region and the DFT equations for this region is then solved self-consistently. In order to be able to decompose the one-electron Schrodinger equation into three regions, the one electron wave function is expanded in basis functions that are localized around each atom.



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Fig. 1. Set up used for simulation

The local density approximation (LDA) states that, for

regions of a material where the charge density is slowly varying, the exchange correlation energy at that point can be considered the same as that for a locally uniform electron gas of the same charge density. The spin polarized variation (local spin density approximation, or LSDA) replaces the spin averaged energy density in the above statement with the energy density for a polarized homogeneous electron gas. LSDA is based on the results of quantum Monte Carlo (MC) calculations for a homogeneous electron gas of different densities. The LSD approximation also requires results for a spin-polarized system and a means of interpolating for one with partial polarization.

The insulator layer separation and the inner layer separation

of the four MTJ configurations are tabulated in TABLE I along with the electrode/oxygen distance, all values are in angstroms.

TABLE I

MTJ INTERNAL DIMENSIONS

MTJ Configuration

Insulator Layer

Separation (Ǻ)

Inner Layer

Separation (Ǻ)

Electrode/Oxygen Distance (Ǻ)

Fe/MgO/Fe 2.09525 0.520 1.85 Fe/Y2O3/Fe 1.74897 0.542 1.87 Fe/HfO2/Fe 1.99719 0.9645 1.98 Fe/Al2O3/Fe 2.19535 0.533 1.85

III. SIMULATION RESULTS

The Fig. 2 (a) and Fig. 2 (b) give the I-V plots of the four

MTJs in the parallel and anti parallel magnetized states respectively. The Fig. 2(a) shows that, for the parallel magnetized state, the magnitude of the tunnel current through the Fe/MgO/Fe junction is the least and is independent of the applied bias. For the antiparallel state, the Fig. 2 (b) again shows that, the magnitude of the tunnel current is the lowest through the Fe/MgO/Fe junction and is independent of the bias. From these I-V curves, the TMR (%) v/s bias voltage plots have been obtained for all the four MTJs, as shown in Fig. 3. The TMR ratios have been calculated using (1). It is clear that the Fe/MgO/Fe tunnel junction exhibits TMR ratios of near 100 % for a large bias voltage range from -1.5 V to 1.5

Volts which is not seen in case of the other MTJs. Also to be noted is that the Fe/MgO/Fe MTJ exhibits negative TMR ratios when the bias voltage is increased beyond 1.5 V, indicating that for bias voltages greater than 1.5V the resistance of the antiparallel state is less than that of the parallel state i.e. the spin split bands are so aligned that the tunnel current for the antiparallel state is more than that for the parallel state. The latter observation has to our knowledge not been reported before.

(a)

(b)

Fig. 2. I-V curves of the four MTJs in (a) Parallel State; and (b) Anti Parallel State

The TMR values exhibited by Fe/Y2O3/Fe and Fe/Al2O3/Fe

MTJs are though high but not as high as those of Fe/MgO/Fe and Fe/HfO2/Fe. The Fe/HfO2/Fe MTJ exhibits near 100 % TMR values but the bias voltage range for which it is nearly 100 % is smaller than that of the Fe/MgO/Fe tunnel junctions.



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In order to study the suitability of the insulator used in these MTJs, the thickness of the insulator has been varied from 4 to 10 atomic layers and the corresponding I-V plots have been obtained at 0.5 Volt for parallel and anti parallel magnetized cases. From these plots, the resistances in parallel and anti parallel states have been plotted against increasing insulator thickness as shown in Fig. 4(a) and (b) respectively. Contrary to the basic tunneling theory prediction that with an increase in the insulator thickness an exponential increase in resistance occurs, it is seen from the plots that HfO2 based MTJ

Fig.3. TMR (%) v/s Bias Voltage Plots for the four MTJs

does not exhibit an exponential increase in resistance (both parallel and anti parallel) with an increase in insulator thickness. In fact, the resistance drops for certain insulator thicknesses. This may be due to the presence of resonant channels within the insulator which may cause a sudden drop in resistance values. Even the plots pertaining to Al2O3 hints about the presence of resonant channels as the resistances do not increase exponentially with increase in insulator thickness. Nearly exponential increase in resistances can be observed in case of MgO and Y2O3, though the resistance values with MgO are much higher than with Y2O3.

(a)

(b)

Fig.4. Resistance v/s Insulator Thickness plots for (a) parallel; and (b) anti parallel states

The Figure 5 depicts the plot of TMR (%) with increasing

insulator thickness calculated at a bias voltage of 0.5 Volt. It can be seen from the plot that Fe/MgO/Fe MTJ exhibits near 100% TMR ratios constantly even when the insulator thickness is increased from 4 atomic layers to 10 atomic layers. Fe/HfO2/Fe also exhibits a similar feature but for the other two MTJs simulated, the case is not the same. Oscillatory and damped oscillatory dependence of the TMR on the insulator thickness is to be noted in the case of Al2O3 and Y2O3 based MTJ’s respectively.



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Fig. 5. TMR (%) v/s Insulator Thickness for the four MTJs

As the existing circuit simulating tools do not have a library

file that can be used to represent an MTJ in an MRAM circuit, we use a resistor and a capacitor connected in parallel as an equivalent circuit of MTJ. The resistance and capacitance values can be obtained from the device geometry and device level simulations. For a particular bias voltage, we can have two resistance values, RP and RAP, respectively. But capacitance is independent of voltage and depends only on the device dimensions. Now, the device that has been simulated is very small in size as it is made up of only 48 atoms and the central insulating layer consists of six atomic layers. The cross sectional area of the simulated MTJs is in the range of 0.16 nm2. As the simulation tool cannot simulate a device comprising of as many number of atoms as present in a practically realizable MTJ, we calculate the resistances, both RP and RAP, for the 0.16 nm2 cross section structures at a voltage of 1 V. As resistance is inversely proportional to cross sectional area, we divide the calculated resistance values by a certain factor (factor by which cross sectional area increases) so that we get resistance values corresponding to the device with 525.7 nm2 cross sectional area. The resistance and capacitance values corresponding to the four MTJs obtained for 1 V are shown in TABLE II. The static power dissipation in the MTJ and corresponding write energy (time =20 ns, V = 1 V) are calculated and tabulated in TABLE III. Using these R and C values, the circuit level simulations of an MTJ based MRAM cell have been performed using Mentor Graphics Design Architect. The schematic of the circuit is shown in the form of a block diagram in Fig. 6. The circuit is operated at 1 Volt. The comparator compares the output of the MTJ with the reference voltage and provides a LOW or HIGH output. For Fe/MgO/Fe MTJ, small spikes have been observed in the output of the MTJ that goes to the comparator, when simulated with RAP and CMTJ. This implies that the CMTJ, though very small, cannot be ignored, particularly for Fe/MgO/Fe MTJ

since RAP is very large and this increases the RC time constant. This behavior is not observed in the other MTJs as the values of RP and RAP are quite smaller. From the circuit simulations, the delay, rise time and fall time have been

TABLE II

RP, RAP AND CMTJ VALUES AT 1 VOLT

MTJ RP (Ohms)

RAP (Ohms)

CMTJ

(Farads)

Fe/MgO/Fe 1280 13.9 ×106 40.8 ×10-18

Fe/Y2O3/Fe 24 105.8 76.3×10-18

Fe/HfO2/Fe 12 73.6 106.0×10-18

Fe/Al2O3/Fe 33 1600 41.6×10-18

obtained separately at the outputs of each of these four MTJs. From these data, the switching power dissipation (power dissipated in charging the MTJ capacitor) and work done in charging the MTJ capacitor are computed and presented in TABLE IV as obtained using the fall times of MTJ output with RP and RAP respectively. The rise time, fall time, rise delay and fall delay corresponding to the four MTJ based MRAM circuits in parallel and anti parallel magnetization states respectively are shown in TABLE V.

From TABLE II, it is clear that only Fe/MgO/Fe exhibits a large difference between RP and RAP so that the comparator can detect the corresponding MTJ outputs easily. The static power dissipation and write energy per bit are the least for Fe/MgO/Fe MTJ. The switching power and work done in charging the MTJ capacitance with RP and RAP respectively are also impressive. The circuit level simulations with Fe/MgO/Fe MTJ dissipated a static power of 20.2119 pW with RP and 20.4367 pW with RAP respectively. Therefore, we conclude that Fe/MgO/Fe is the best suited MTJ for use in MTJ based Magnetoresistive RAMs though Fe/Y2O3/Fe MTJs too could be a strong contender for use in MRAMs.

Fig. 6. Schematic of MTJ based MRAM



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TABLE III

STATIC POWER DISSIPATION & WRITE ENERGY PER BIT

MTJ Power dissipated in parallel state, PP

(Watts)

Power dissipated in anti parallel state, PAP

(Watts)

Write energy per bit in parallel state, WP (nJ)

Write energy per bit in anti parallel state,

WAP (nJ)

Fe/MgO/Fe 7.8×10-4 7.2×10-8 0.015 1.4×10-4

Fe/Y2O3/Fe 4.11×10-2 9.45×10-3 0.82 0.189

Fe/HfO2/Fe 7.95×10-2 1.36×10-2 1.59 0.271

Fe/Al2O3/Fe 3.05×10-2 6.25×10-4 0.61 0.0125

TABLE IV

SWITCHING POWER AND WORK DONE IN CHARGING CMTJ

TABLE V

DELAY TIME ESTIMATIONS

Sl. No.

MTJ Rise Delay with RP (ps)

Rise Delay with RAP (ps)

Fall Delay with RP

(ps)

Fall Delay with RAP

(ps)

Rise time with RP

(ps)

Rise time with RAP (ps)

Fall time with RP

(ps)

Fall time with RAP

(ps)

1 Fe/MgO/Fe 316.86 201.78

329.45 0.010 344.59 0.011 320.98 58.44

2 Fe/Y2O3/Fe 314.62

314.86

330.40 331.73

340.45 400.93

317.65 318.04

3 Fe/HfO2/Fe 314.76

314.87

330.52 331.72

340.58 401.14

317.78 318

4 Fe/Al2O3/Fe 314.76 315.50

330.48 330.9

340.61 370.06

317.80 321.19

No. MTJ Power dissipated in parallel

state, PP(J/s)

Power dissipated

in anti parallel state,

PAP(J/s)

Work done in charging

CMTJ in parallel state, WP(J)

Work done in charging CMTJ in anti

parallel state, WAP(J)

1 Fe/MgO/Fe 9.26×10-10 3.49×10-7 2.97×10-19 2.04×10-17

2 Fe/Y2O3/Fe 6.52×10-13 1.25×10-11 2.07×10-22 3.94×10-21

3 Fe/HfO2/Fe 2.44×10-13 8.33×10-12 7.76×10-23 2.65×10-21

4 Fe/Al2O3/Fe 6.29×10-13 1.44×10-9 1.99×10-22 4.64×10-19



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IV. CONCLUSIONS

In this paper, the LSDA band structure simulations have

been carried out for four different magnetic tunnel junctions - Fe/MgO/Fe, Fe/Y2O3/Fe, Fe/HfO2/Fe and Fe/Al2O3/Fe to obtain the I-V curves in parallel and anti parallel magnetization states for each of the tunnel junctions. From the I-V curves of each MTJ, the TMR ratios have been computed and plotted against the bias voltages. Fe/MgO/Fe MTJ exhibits very high TMR ratios for the widest range of bias voltage when compared to the other simulated MTJs. Also, for a fixed bias voltage of 0.5 Volt, all the four MTJs have been simulated for increasing insulator thicknesses to obtain I-V curves for both parallel and anti parallel magnetization states. An exponential increase in parallel as well as anti parallel magnetization state resistance with increase in insulator thickness is observed in Fe/MgO/Fe MTJ while the increase is not exponential in case of the other MTJs. A plot of TMR ratio versus insulator thickness has been plotted for all the MTJs. A block diagram of the schematic of MTJ based MRAM cell circuit has been proposed and the schematic has been simulated for each of the four MTJs by extracting the resistance and capacitance values from the device level calculations. From the circuit level simulations, the static power dissipation and write energy per bit have been found to be the least in case of Fe/MgO/Fe MTJ which also exhibits impressive switching power dissipation and work done in charging the MTJ capacitor in both parallel and anti parallel magnetization states respectively. The delay time estimation suggests that Fe/MgO/Fe has a relatively lower switching time when compared to the other MTJs thereby proving Fe/MgO/Fe MTJs to be faster than the others. Therefore, it can be concluded that Fe/MgO/Fe MTJ maybe the best suited MTJ for MRAMs owing to its very high TMR ratios for a wider voltage range, good quality of insulator as seen from the exponential increase in parallel and anti parallel resistances with increasing insulator thickness, least static power dissipation and write energy per bit and impressive switching power dissipation, work done in charging the capacitor, rise delay, fall delay, rise time and fall time. Therefore, MTJ based MRAMs are a strong contender to replace the age old flash memories being used in cell phone architectures and other low power, high speed applications since they can be scaled down to a much greater extent to attain a feature size that is much smaller than DRAMs and other existing memory technologies. MTJ based MRAMs do not need to be periodically refreshed like DRAMs, they are non volatile, very small in size, much faster than modern day memories, consumes much less power and operates faster than other memory technologies.

ACKNOWLEDGMENT

The authors would like to thank Prof. Dr. J.P.Raina,

Director, Centre for Nanotechnology Research, VIT University, Vellore, India, for his whole hearted

encouragement and support throughout the period of their work. They would also like to thank all the faculty members of Nanoelectronics Division, School of Electronics Engineering, VIT University, Vellore, India, for providing them with the computing facilities available to carry out the simulation work. The authors would also like to thank Dr. Marcus Yee, Quantumwise A/S, Denmark, for providing them with the license of Quantumwise Atomistix Tools Kit for carrying out the first principle LSDA band structure calculations.

REFERENCES [1] T. Block, M. J. Carey, B. A. Gurney, O. Jepsen (2004), Physical

Review 70: 205114. [2] S. S. P. Parkin et al. (2004), Nat. Mat. 3 (12): 862–867 & S. Yuasa et.

al.(2004), Nat. Mat. 3 (12):868-871 [3] Johan Åkerman, Science, Vol. 308. no. 5721 (22 April 2005), pp. 508 –

510 [4] William J. Gallagher and Stuart S. P. Parkin, IBM, 24 January 2006 [5] Y. Huai, AAPPS Bulletin, December 2008, vol. 18, no. 6, p.33 [6] P. M. Tedrow and R. Meservey, Phys. Rev. Lett. 26, 192(1971). [7] M. Julliere (1975), Phys. Lett. 54A: 225–226. [8] S. S. P. Parkin, C. Kaiser, A. Panchula, P. M. Rice, B. Hughes, M.

Samant, and S.-H. Yang, Nano Lett. 3, 862 (2004). [9] D. Djayaprawira, K. Tsunekawa, M. Nagai, H. Maehara, S.

Yamagata,N. Watanabe, S. Yuasa, Y. Suzuki, and K. Ando, Appl. Phys. Lett. 86, 092502 (2005).

[10] C. Tiusan, J. Faure-Vincent, C. Bellouard, M. Hehn, E. Jouguelet, and A. Schuhl, Phys. Rev. Lett. 93, 106602 (2004).

[11] S. Yuasa, T. Nagahama, A. Fukushima, Y. Suzuki, and K. Ando, Nano Lett. 3, 868 (2004).

[12] Parr, Robert G.; Yang, Weitao (1994). Density-Functional Theory of Atoms and Molecules. Oxford University Press. ISBN 978-0195092769

[13] Kohn, Walter; Sham, Lu Jeu (1965). "Self-Consistent Equations Including Exchange and Correlation Effects". Physical Review 140 (4A): A1133–A1138.

Authors Mr. Mayank Chakraverty received the Bachelor of Engineering degree in Electronics and Communication Engineering from Anna University, Chennai, India, in 2009. He received the Master of Technology degree in Nanotechnology (specialization in Nanoelectronics) from VIT University, Vellore, India, in 2011.

His areas of interest include Solid State Electronics, Memory Design, Digital IC Design, Nano Scale Electronic Devices and Circuits, MEMS, IC Process Technology and Reliability Issues in Device Designs. He has published several papers on Digital Design, Memory Design, MEMS and nano scale device designs in International Journals and International Conferences of repute. He is currently working with IBM, Bangalore, India, as a System Engineer. He is also pursuing Master of Science (MS) in Microelectronics from Manipal University, India.



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Dr. Harish M. Kittur received the Bachelor of Science Degree in Physics, Mathematics and Electronics from the Karnataka University, Dharwad, India in 1994, Master of Science Degree in Physics from the Indian Institute of Technology, Mumbai, in 1996, Master of Technology Degree in Solid State Technology in the year 1999 from the

Indian Institute of Technology, Madras, and Ph. D. in Physics from the RWTH Aachen, Germany, in the year 2004. His areas of interest include semiconductor device physics, VLSI Design, magnetoelectronics, nanoelectronics, and memory design. He was awarded the DAAD Academic Exchange Fellowship to pursue Masters Project Work in Germany. He is currently Professor, Division Chair and Chairperson of the M. Tech VLSI Design Program of the VLSI Division, School of Electronics Engineering, VIT University, Vellore, India.

Mr. Arun Kumar P received the Bachelor of Technology Degree in Electrical and Electronics Engineering from Regency Institute Of Technology, Yanam, India. He received the Master of Technology degree in VLSI Design from SASTRA University, Thanjavur, India. His areas of interest include VLSI Testing, Memory Design, and

Low Power Design. He is currently Assistant Professor in the VLSI Division of the School of Electronics Engineering, VIT University, Vellore, India.

Documents

First Principle Simulations of Various Magnetic Tunnel Junctions $\kern-2pt$ for$\kern-2pt$ Applications in Magnetoresistive Random Access Memories