Upload
vuquynh
View
253
Download
1
Embed Size (px)
Citation preview
Fire Protection Flash MCU
BA45F0082
Revision: V1.00 Date: st 1 01st 1 01
Rev. 1.00 st 1 01 Rev. 1.00 3 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Table of Contents
Features ............................................................................................................ 6CPU Featres ......................................................................................................................... 6Peripheral Featres ................................................................................................................. 6
General Description ......................................................................................... 7Block Diagrams ................................................................................................ 7Pin Assignment ................................................................................................ 8Pin Description ................................................................................................ 8Absolute Maximum Ratings .......................................................................... 10D.C. Characteristics ....................................................................................... 10
Operatin Voltae Characteristics ......................................................................................... 10Operatin Crrent Characteristics ......................................................................................... 10Standby Crrent Characteristics ............................................................................................11
A.C. Characteristics ....................................................................................... 12Hih Speed Internal Oscillator Freqency ccracy ............................................................. 1Low Speed Internal Oscillator Characteristics – LIRC .......................................................... 1Operatin Freqency Characteristic Crves ......................................................................... 13System Start Up Time Characteristics .................................................................................. 13
Input/Output Characteristics ........................................................................ 14Memory Characteristics ................................................................................ 14A/D Converter Electrical Characteristics ..................................................... 15Reference Voltage Characteristics ............................................................... 15LVD/LVR Electrical Characteristics .............................................................. 15Power-on Reset Characteristics ................................................................... 16System Architecture ...................................................................................... 17
Clockin and Pipelinin ......................................................................................................... 1Proram Conter ................................................................................................................... 18Stack ..................................................................................................................................... 18rithmetic and Loic Unit – LU ........................................................................................... 19
Flash Program Memory ................................................................................. 19Strctre ................................................................................................................................ 19Special Vectors ..................................................................................................................... 0Look-p Table ........................................................................................................................ 0Table Proram Example ........................................................................................................ 0In Circit Prorammin ......................................................................................................... 1On-Chip Deb Spport – OCDS .........................................................................................
Data Memory .................................................................................................. 23Strctre ................................................................................................................................ 3General Prpose Data Memory ............................................................................................ 3Special Prpose Data Memory ............................................................................................. 4
Rev. 1.00 st 1 01 Rev. 1.00 3 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Special Function Register Description ........................................................ 25Indirect ddressin Reisters – IR0 IR1 ......................................................................... 5Memory Pointers – MP0 MP1 .............................................................................................. 5Bank Pointer – BP ................................................................................................................. 6ccmlator – CC ............................................................................................................... 6Proram Conter Low Reister – PCL .................................................................................. 6Look-p Table Reisters – TBLP TBHP TBLH ..................................................................... 6Stats Reister – STTUS ....................................................................................................
EEPROM Data Memory .................................................................................. 29EEPROM Data Memory Strctre ........................................................................................ 9EEPROM Reisters .............................................................................................................. 9Readin Data from the EEPROM ......................................................................................... 30Writin Data to the EEPROM ................................................................................................ 31Write Protection ..................................................................................................................... 31EEPROM Interrpt ................................................................................................................ 31Prorammin Considerations ................................................................................................ 3
Oscillators ...................................................................................................... 33Oscillator Overview ............................................................................................................... 33System Clock Configurations ................................................................................................ 33Internal Hih Speed RC Oscillator – HIRC ........................................................................... 34Internal 3kHz Oscillator – LIRC ........................................................................................... 34
Operating Modes and System Clocks ......................................................... 34System Clocks ...................................................................................................................... 34System Operation Modes ...................................................................................................... 35Control Reisters .................................................................................................................. 36Operatin Mode Switchin .................................................................................................... 38Standby Crrent Considerations ........................................................................................... 4Wake-p ................................................................................................................................ 4
Watchdog Timer ............................................................................................. 43Watchdo Timer Clock Sorce .............................................................................................. 43Watchdo Timer Control Reister ......................................................................................... 43Watchdo Timer Operation ................................................................................................... 44
Reset and Initialisation .................................................................................. 45Reset Fnctions .................................................................................................................... 45Reset Initial Conditions ......................................................................................................... 48
Input/Output Ports ......................................................................................... 51Pll-hih Resistors ................................................................................................................ 51Port Wake-p ..................................................................................................................... 5I/O Port Control Reisters ..................................................................................................... 5Pin-shared Fnctions ............................................................................................................ 53I/O Pin Strctres .................................................................................................................. 55Prorammin Considerations ................................................................................................ 55
Rev. 1.00 4 st 1 01 Rev. 1.00 5 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Timer Modules – TM ...................................................................................... 56Introdction ........................................................................................................................... 56TM Operation ........................................................................................................................ 56TM Clock Sorces ................................................................................................................. 56TM Interrpts ......................................................................................................................... 56TM External Pins ................................................................................................................... 5TM Inpt/Otpt Pin Control ................................................................................................. 5Prorammin Considerations ................................................................................................ 58
Standard Type TM – STM .............................................................................. 59Standard TM Operation ......................................................................................................... 60Standard Type TM Reister Description ............................................................................... 60Standard Type TM Operatin Modes .................................................................................... 66
Analog to Digital Converter ......................................................................... 76/D Converter Overview ....................................................................................................... 6/D Converter Reister Description ...................................................................................... /D Converter Operation ....................................................................................................... 9/D Converter Reference Voltae ......................................................................................... 80/D Converter Inpt Sinals .................................................................................................. 81Conversion Rate and Timin Diaram .................................................................................. 81Smmary of /D Conversion Steps ...................................................................................... 8Prorammin Considerations ................................................................................................ 83/D Conversion Fnction ...................................................................................................... 83/D Conversion Prorammin Examples .............................................................................. 84
Interrupts ........................................................................................................ 86Interrpt Reisters ................................................................................................................. 86Interrpt Operation ................................................................................................................ 89External Interrpts ................................................................................................................. 90LVD Interrpt ......................................................................................................................... 91/D Converter Interrpt ......................................................................................................... 91Time Base Interrpts ............................................................................................................. 91EEPROM Write Interrpt ....................................................................................................... 9STM Interrpts ...................................................................................................................... 9Interrpt Wake-p Fnction ................................................................................................... 93Prorammin Considerations ................................................................................................ 93
Low Voltage Detector – LVD ......................................................................... 94LVD Reister ......................................................................................................................... 94LVD Operation ....................................................................................................................... 95
Instruction Set ................................................................................................ 96Introdction ........................................................................................................................... 96Instrction Timin .................................................................................................................. 96Movin and Transferrin Data ............................................................................................... 96rithmetic Operations ............................................................................................................ 96Loical and Rotate Operation ............................................................................................... 9Branches and Control Transfer ............................................................................................. 9
Rev. 1.00 4 st 1 01 Rev. 1.00 5 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Bit Operations ....................................................................................................................... 9Table Read Operations ......................................................................................................... 9Other Operations ................................................................................................................... 9
Instruction Set Summary .............................................................................. 98Table Conventions ................................................................................................................. 98
Instruction Definition ................................................................................... 100Package Information ................................................................................... 109
16-pin NSOP (150mil) Otline Dimensions ..........................................................................110
Rev. 1.00 6 st 1 01 Rev. 1.00 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Features
CPU Features• OperatingVoltage
♦ fSYS=2/4MHz:2.2V~5.5V
• Upto1μsinstructioncyclewith4MHzsystemclockatVDD=5V
• Powerdownandwake-upfunctionstoreducepowerconsumption
• Oscillatortypes:♦ InternalHighSpeedRC–HIRC♦ InternalLowSpeed32kHzRC–LIRC
• Multi-modeoperation:FAST,SLOW,IDLEandSLEEP
• Fullyintegratedinternaloscillatorsrequirenoexternalcomponents
• Allinstructionsexecutedinoneortwoinstructioncycles
• Tablereadinstructions
• 63powerfulinstructions
• 6-levelsubroutinenesting
• Bitmanipulationinstruction
Peripheral Features• FlashProgramMemory:2K×15
• RAMDataMemory:128×8
• TrueEEPROMMemory:64×8
• WatchdogTimerfunction
• 14bidirectionalI/Olines
• Twopin-sharedexternalinterrupt
• MultipleTimerModulesfortimemeasurement,inputcapture,comparematchoutputorPWM outputorsinglepulseoutputfunction
• DualTime-Basefunctionsforgenerationoffixedtimeinterruptsignals
• Multi-channel12-bitresolutionA/Dconverter
• Lowvoltageresetfunction
• Lowvoltagedetectfunction
• Packagetype:16-pinNSOP
Rev. 1.00 6 st 1 01 Rev. 1.00 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
General DescriptionTheBA45F0082isaFlashmemorytype8-bithighperformanceRISCarchitecturemicrocontroller,designedespecially fornetworking fireproductperipheral applications.Offeringusers theconvenienceofFlashmemorymulti-programmingfeatures,thedevicealsoincludesawiderangeofflexiblefunctionsandfeatures.OthermemoryincludesanareaofRAMDataMemoryaswellasanareaoftrueEEPROMmemoryforstorageofnon-volatiledatasuchasserialnumbers,calibrationdataetc.
Analogfeaturesincludeamulti-channelAnalogtoDigitalconverter.MultipleandextremelyflexibleTimerModulesprovidetiming,pulsegeneration,captureinput,comparematchoutput,singlepulseoutputandPWMgenerationfunctions.ProtectivefeaturessuchasaninternalWatchdogTimer,LowVoltageResetandLowVoltageDetectorcoupledwithexcellentnoiseimmunityandESDprotectionensurethatreliableoperationismaintainedinhostileelectricalenvironments.
Thedevicealso includes fully integratedhighand lowspeedoscillatorswhichcanbeflexiblyusedfordifferentapplications.Theabilitytooperateandswitchdynamicallybetweenarangeofoperatingmodesusingdifferentclocksourcesgivesusers theabilitytooptimisemicrocontrolleroperationcanminimumpowerconsumption.TheusualHoltekMCUfeaturessuchaspowerdownandwake-upfunctions,oscillatoroptions,programmablefrequencydivider,etc.combinetoensureuserapplicationsrequireaminimumofexternalcomponents.
WhiletheinclusionofflexibleI/Oprogrammingfeatures,Time-Basefunctionsalongwithmanyotherfeaturesensure that thedevicewill findexcellentuse infireprotectionperipheralproductapplicationssuchas temperaturealarms, Input/Outputmodules, sound-lightalarms, firedoormonitoringinadditiontomanyothers.
Block Diagrams
STM0
Phase Protect
Interrupt Controller
BusM
UX
VDD
SYSCLK
Reset Circuit
LVD/LVR
Stack6-Level
RAM128×8
ROM2K×15
EEPROM64×8
WatchdogTimer
Port ADriver
HIRC2/4MHz
LIRC32kHz
MU
X
Analog Digital Converter
Timers
INT0~INT1
AN0~AN7
Pin-SharedWith Port A&B
Pin- SharedWith Port A&B
Port BDriver
PA0~PA7
VREF
Clock System
Time Bases
Digital Peripherals
HT8 MCU Core
PB0~PB4, PB6
Auto Converter
10-bit PWM
Phase Detect
STP0
STP1
VBG12-bitADC
Analog Peripherals
I/O
: Pin-Shared Node
STM1
Phase Protect
16-bit PWM
Phase Detect
GND
Pin-SharedFunction
Pin-SharedWith Port B
RES
Rev. 1.00 8 st 1 01 Rev. 1.00 9 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Pin Assignment
BA45F0082/BA45V008216 NSOP-A
VSS&AVSSPA1/STP0/VREFPA3/STCK0/AN4PA4/INT0
PB2/STP1I/AN2
VDD&AVDD
PA0/ICPDA/OCDSDAPB0/STP1/AN0
PA2/ICPCK/OCDSCK
PA6/AN6PA5/STP0I/AN5PB1/STCK1/AN1
PB6/INT1PA7/AN7PB3/AN3
PB4/RES
161514131211109
12345678
Notes:1.Ifthepin-sharedpinfunctionshavemultipleoutputs,thedesiredpin-sharedfunctionisdeterminedbythecorrespondingsoftwarecontrolbits.
2.VDD&AVDDmeanstheVDDandAVDDarethedoublebonding.VSS&AVSSmeanstheVSSandAVSSarethedoublebonding.
3.TheOCDSDAandOCDSCKpinsareusedas theOCDSdedicatedpinsandonlyavailable for theBA45V0082devicewhichistheOCDSEVchipoftheBA45F0082.
4.For lesspin-countpackage types therewillbeunbondedpinsofwhichstatusshouldbeproperlyconfiguredtoavoidthecurrentconsumptionresultingfromaninputfloatingcondition.Refer to the“StandbyCurrentConsiderations”and“Input/OutputPorts”sections.
Pin DescriptionThefunctionofeachpinislistedinthefollowingtable,howeverthedetailsbehindhoweachpinisconfigurediscontainedinothersectionsofthedatasheet.
Pin Name Function OPT I/T O/T Description
P0/ICPD/OCDSD
P0 PWUPPU ST CMOS General prpose I/O. Reister enabled pll-p and
wake-pICPD — ST CMOS ICP Data Line
OCDSD — ST CMOS On Chip Deb System Data Line (OCDS EV only)
P1/STP0/VREFP1
PWUPPUPS0
ST CMOS General prpose I/O. Reister enabled pll-p and wake-p
STP0 PS0 — CMOS STM0 otptVREF PS0 N — /D Converter reference voltae inpt
P/ICPCK/OCDSCK
P PWUPPU ST CMOS General prpose I/O. Reister enabled pll-p and
wake-pICPCK — ST — ICP Clock Line
OCDSCK — ST — On Chip Deb System Clock Line (OCDS EV only)
P3/STCK0/N4
P3PWUPPUPS0
ST CMOS General prpose I/O. Reister enabled pll-p and wake-p
STCK0 PS0STM0C0 ST — STM0 clock inpt
N4 PS0 N — /D Converter inpt channel 4
P4/INT0P4 PWU
PPU ST CMOS General prpose I/O. Reister enabled pll-p and wake-p
INT0 INTEG ST — External interrpt inpt
Rev. 1.00 8 st 1 01 Rev. 1.00 9 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Pin Name Function OPT I/T O/T Description
P5/STP0I/N5
P5PWUPPUPS1
ST CMOS General prpose I/O. Reister enabled pll-p and wake-p
STP0IPS1
STM0C0STM0C1
ST — STM0 captre inpt pin
N5 PS1 N — /D Converter inpt channel 5
P6/N6P6
PWUPPUPS1
ST CMOS General prpose I/O. Reister enabled pll-p and wake-p
N6 PS1 N — /D Converter inpt channel 6
P/NP
PWUPPUPS1
ST CMOS General prpose I/O. Reister enabled pll-p and wake-p
N PS1 N — /D Converter inpt channel
PB0/STP1/N0PB0 PBPU
PBS0 ST CMOS General prpose I/O. Reister enabled pll-p and wake-p
STP1 PBS0 — CMOS STM1 otptN0 PBS0 N — /D Converter inpt channel 0
PB1/STCK1/N1
PB1 PBPUPBS0 ST CMOS General prpose I/O. Reister enabled pll-p and
wake-p
STCK1 PBS0STM1C0 ST — STM1 clock inpt
N1 PBS0 N — /D Converter inpt channel 1
PB/STP1I/N
PB PBPUPBS0 ST CMOS General prpose I/O. Reister enabled pll-p and
wake-p
STP1IPBS0
STM1C0STM1C1
ST — STM1 captre inpt pin
N PBS0 N — /D Converter inpt channel
PB3/N3PB3 PBPU
PBS0 ST CMOS General prpose I/O. Reister enabled pll-p and wake-p
N3 PBS0 N — /D Converter inpt channel 3
PB4/RESPB4 PBPU ST CMOS General prpose I/O. Reister enabled pll-pRES RSTC ST — External reset pin
PB6/INT1PB6 PBPU ST CMOS General prpose I/O. Reister enabled pll-pINT1 INTEG ST — External interrpt inpt
VDD&VDD*VDD — PWR — Diital Positive power spply
VDD — PWR — nalo positive power spply
VSS&VSS**VSS — PWR — Diital neative power spply
VSS — PWR — nalo neative power spply
Legend:I/T:Inputtype; O/T:Outputtype; OPT:Optionalbyregisteroption; PWR:Power; ST:SchmittTriggerinput; CMOS:CMOSoutput; AN:Analogsignal; *:VDDisthedevicedigitalpowersupplywhileAVDDistheanalogpowersupply.TheAVDDpinisbondedtogetherinternallywithVDD.
**:VSSisthedevicedigitalgroundpinwhileAVSSistheanaloggroundpin.TheAVSSpinisbondedtogetherinternallywithVSS.
Rev. 1.00 10 st 1 01 Rev. 1.00 11 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Absolute Maximum RatingsSupplyVoltage................................................................................................VSS−0.3VtoVSS+6.0VInputVoltage..................................................................................................VSS−0.3VtoVDD+0.3VStorageTemperature....................................................................................................-50˚Cto125˚COperatingTemperature..................................................................................................-40˚Cto85˚CIOLTotal..................................................................................................................................... 80mAIOHTotal....................................................................................................................................-80mATotalPowerDissipation......................................................................................................... 500mW
Note:Theseare stress ratingsonly.Stressesexceeding the range specifiedunder "AbsoluteMaximumRatings"maycausesubstantialdamageto thedevices.Functionaloperationofthedevicesatotherconditionsbeyondthose listed in thespecification isnot impliedandprolongedexposuretoextremeconditionsmayaffectdevicereliability.
D.C. CharacteristicsFordatainthefollowingtables,notethatfactorssuchasoscillatortype,operatingvoltage,operatingfrequency,pin loadconditions, temperatureandprograminstruction type,etc.,canallexertaninfluenceonthemeasuredvalues.
Operating Voltage CharacteristicsTa= -40°C~85°C
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VDDOperatin Voltae (HIRC)
fSYS = MHz . — 5.5V
fSYS = 4MHz . — 5.5Operatin Voltae (LIRC) fSYS = 3kHz . — 5.5 V
Operating Current CharacteristicsTa= -40°C~85°C
Symbol Normal OperationTest Conditions
Min. Typ. Max. UnitVDD Conditions
IDD
SLOW Mode (LIRC).V
fSYS = 3kHz— 8 16
μA3V — 10 05V — 30 50
FST Mode (HIRC)
.VfSYS = MHz
— 0.15 0.
m
3V — 0. 0.35V — 0.4 0.6
.VfSYS = 4MHz
— 0.3 0.53V — 0.4 0.65V — 0.8 1.
Note:Whenusingthecharacteristictabledata,thefollowingnotesshouldbetakenintoconsideration:• Anydigitalinputsaresetupinanon-floatingcondition.• Allmeasurementsaretakenunderconditionsofnoloadandwithallperipheralsinanoffstate.• TherearenoDCcurrentpaths.• AllOperatingCurrentvaluesaremeasuredusingacontinuousNOPinstructionprogramloop.
Rev. 1.00 10 st 1 01 Rev. 1.00 11 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Standby Current CharacteristicsTa= -40°C~85°C
Symbol Standby ModeTest Conditions
Min. Typ. Max.Max.
UnitVDD Conditions 85°C
ISTB
SLEEP Mode
.VWDT off
— 0. 0.6 0.μA3V — 0. 0.8 1
5V — 0.5 1 1..V
WDT on— 1. .4 .9
μA3V — 1.5 3 3.65V — 3 5 6
IDLE0 Mode – LIRC.V
fSUB on— .4 4 4.8
μA3V — 3 5 65V — 5 10 1
IDLE1 Mode – HIRC
.VfSUB on fSYS = MHz
— 60 10 140μA3V — 0 140 160
5V — 130 60 80.V
fSUB on fSYS = 4MHz— 90 00 0
μA3V — 110 0 405V — 10 40 460
Note:Whenusingthecharacteristictabledata,thefollowingnotesshouldbetakenintoconsideration:
• Anydigitalinputsaresetupinanon-floatingcondition.• Allmeasurementsaretakenunderconditionsofnoloadandwithallperipheralsinanoffstate.• TherearenoDCcurrentpaths.• AllStandbyCurrentvaluesaretakenafteraHALTinstructionexecutionthusstoppingallinstructionexecution.
Rev. 1.00 1 st 1 01 Rev. 1.00 13 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
A.C. CharacteristicsFordatainthefollowingtables,notethatfactorssuchasoscillatortype,operatingvoltage,operatingfrequencyandtemperatureetc.,canallexertaninfluenceonthemeasuredvalues.
High Speed Internal Oscillator Frequency AccuracyDuringtheprogramwritingoperationthewriterwill trimtheHIRCoscillatoratauserselectedHIRCfrequencyanduserselectedvoltageofeither3Vor5V.
Symbol ParameterTest Conditions
Min. Typ. Max. UnitVDD Temp.
fHIRC
MHz Writer Trimmed HIRC Freqency
3V/5V
5°C -1% +1%
MHz
-0°C~60°C -% +%
-40°C~85°C -3% +3%
.V~5.5V5°C -9% +9%
-40°C~85°C -10% +10%
4MHz Writer Trimmed HIRC Freqency
3V/5V5°C -1% 4 +1%
MHz-40°C~85°C -% 4 +%
.V~5.5V5°C -.5% 4 +.5%
-40°C~85°C -3% 4 +3%
Notes:1.The3V/5VvaluesforVDDareprovidedasthesearethetwoselectablefixedvoltagesatwhichtheHIRCfrequencyistrimmedbythewriter.
2.Therowbelowthe3V/5Vtrimvoltage rowisprovided toshowthevalues for the fullVDD rangeoperatingvoltage.Itisrecommendedthatthetrimvoltageisfixedat3Vforapplicationvoltagerangesfrom2.2Vto3.6Vandfixedat5Vforapplicationvoltagerangesfrom3.3Vto5.5V.
3.Theminimumandmaximumtolerancevaluesprovidedinthetableareonlyforthefrequencyatwhichthewriter trimstheHIRCoscillator.After trimmingat thischosenspecificfrequencyanychangeinHIRCoscillatorfrequencyusingtheoscillatorregistercontrolbitsbytheapplicationprogramwillgiveafrequencytolerancetowithin±20%.
Low Speed Internal Oscillator Characteristics – LIRC
Symbol ParameterTest Conditions
Min. Typ. Max. UnitVDD Temp.
fLIRC LIRC Freqency .V~5.5V5°C -10% 3 +10%
kHz-40°C~85°C -50% 3 +60%
tSTRT LIRC Start p Time — — — — 500 μs
Rev. 1.00 1 st 1 01 Rev. 1.00 13 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Operating Frequency Characteristic Curves
System Operating Frequency
Operating Voltage
2MHz
4MHz
2.2V
~ ~
5.5V
~~
~ ~
System Start Up Time CharacteristicsTa= -40°C~85°C
Symbol Parameter Test Conditions Min. Typ. Max. Unit
tSST
System Start-p Time (Wake-p from condition where fSYS is off)
fSYS = fH ~ fH/64 fH = fHIRC — 16 — tHIRC
fSYS = fSUB = fLIRC — — tLIRC
System Start-p Time (Wake-p from condition where fSYS is on)
fSYS = fH ~ fH/64 fH = fHIRC — — tHfSYS = fSUB = fLIRC — — tSUB
System Speed Switch Time (FST to SLOW Mode or SLOW to FST Mode)
fHIRC switches from off → on — 16 — tHIRC
tRSTD
System Reset Delay Time (Reset sorce from Power-on reset or LVR hardware reset)
RRPOR=5V/ms4 48 54
msSystem Reset Delay Time(RSTC/WDTC reister software reset)
System Reset Delay Time(WDT overflow reset or Reset pin reset) 14 16 18
tSRESET Minimm Software Reset Width to Reset 45 90 10 μstRES External Reset Minimm Low Plse Width 10 μs
Notes:FortheSystemStart-uptimevalues,whetherfSYSisonoroffdependsuponthemodetypeandthechosenfSYSsystemoscillator.DetailsareprovidedintheSystemOperatingModessection.• Thetimeunits,shownbythesymbolstHIRCetc.aretheinverseofthecorrespondingfrequencyvaluesasprovidedinthefrequencytables.ForexampletHIRC=1/fHIRC,tSYS=1/fSYSetc.
• IftheLIRCisusedasthesystemclockandifitisoffwhenintheSLEEPMode,thenanadditionalLIRCstartuptime,tSTART,asprovidedintheLIRCfrequencytable,mustbeaddedtothetSSTtimeinthetableabove.
• TheSystemSpeedSwitchTimeiseffectivelythetimetakenforthenewlyactivatedoscillatortostartup.
Rev. 1.00 14 st 1 01 Rev. 1.00 15 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Input/Output CharacteristicsTa=5°C nless otherwise specify
Symbol ParameterTest Conditions
Min. Typ. Max. UnitVDD Conditions
VIL
Inpt Low Voltae for I/O Ports or Inpt Pins (except RES pin)
5V — 0 — 1.5V— — 0 — 0.VDD
Inpt Low Voltae for RES pin — — 0 — 0.4VDD
VIH
Inpt Hih Voltae for I/O Ports or Inpt Pins (except RES pin)
5V — 3.5 — 5
V— — 0.8VDD — VDD
Inpt Hih Voltae for RES pin — — 0.9VDD — VDD
IOL Sink Crrent for I/O Ports 3V
VOL=0.1VDD15.5 31 —
m5V 31 6 —
IOH Sorce Crrent for I/O Ports3V
VOH = 0.9VDD-3.5 -.0 —
m5V -. -14.5 —
RPHPll-Hih Resistance for I/O Ports (Note)
3V—
0 60 100kΩ
5V 10 30 50ILEK Inpt Leakae Crrent 5V VIN = VDD or VIN = VSS — — ±1 μA
tTCKSTMn TCK Inpt Pin Minimm Plse Width — — 0.3 — — μs
tTPISTMn TPI Inpt Pin Minimm Plse Width — — 0.3 — — μs
tINTExternal Interrpt Minimm Plse Width — — 10 — — μs
Note:TheRPH internalpullhighresistancevalueiscalculatedbyconnectingtogroundandenablingtheinputpinwithapull-highresistorandthenmeasuringtheinputsinkcurrentatthespecifiedsupplyvoltagelevel.DividingthevoltagebythismeasuredcurrentprovidestheRPHvalue.
Memory CharacteristicsTa=-40°C~85°C
Symbol ParameterTest Conditions
Min. Typ. Max. UnitVDD Conditions
VRW VDD for Read/Write — — VDDmin — VDDmax VProgram Flash/Data EEPROM MemorytDEW Erase/Write Cycle Time — — — 4 msIDDPGM Prorammin/Erase Crrent on VDD — — — — 5.0 mEP Cell Endrance — — 100K — — E/WtRETD ROM Data Retention Time — Ta = 5°C — 40 — YearRAM Data MemoryVDR RM Data Retention Voltae — Device in SLEEP Mode 1 — — V
Rev. 1.00 14 st 1 01 Rev. 1.00 15 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
A/D Converter Electrical CharacteristicsTa=5°C nless otherwise specify
Symbol ParameterTest Conditions
Min. Typ. Max. UnitVDD Conditions
VDD Operatin Voltae — — . — 5.5 VVDI Inpt Voltae — — 0 — VREF VVREF Reference Voltae — — — VDD V
DNL Differential Non-linearity
3V VREF = VDDtDCK = 0.5μs
— — ±3 LSB5V3V VREF = VDD
tDCK = 8μs5V
INL Interal Non-linearity
3V VREF = VDDtDCK = 0.5μs
— — ±4 LSB5V3V VREF = VDD
tDCK = 8μs5V
IDCdditional Crrent for /D Converter Enable
3V No load tDCK = 0.5μs
— 1 m
5V — 1.5 3tDCK Clock Period — — 0.5 — 10 μstONST /D Converter On-to-Start Time — — 4 — — μstDS Samplin Time — — — 4 — tDCK
tDC
Conversion Time(Inclde /D Conversion Sample and Hold Time)
— — — 16 — tDCK
Reference Voltage CharacteristicsTa=5°C nless otherwise specify
Symbol ParameterTest Conditions
Min. Typ. Max. UnitVDD Conditions
VBG Bandap Reference Voltae — — -5% 1.04 +5% VtBGS VBG Trn On Stable Time — No load — — 150 μs
IBGdditional Crrent for Bandap Reference Enable — LVR disable LVD disable — — 180 μA
Note:TheVBGvoltageisusedastheA/Dconverterinternalsignalinput.
LVD/LVR Electrical CharacteristicsTa=5°C
Symbol ParameterTest Conditions
Min. Typ. Max. UnitVDD Conditions
VDD Operatin Voltae — — 1.9 — 5.5 VVLVR Low Voltae Reset Voltae — LVR Enable .1V option -5% .1 +5% V
VLVD Low Voltae Detector Voltae —
LVD enable voltae select .0V
-5%
.0
+5% V
LVD enable voltae select .V .LVD enable voltae select .4V .4LVD enable voltae select .V .LVD enable voltae select 3.0V 3.0LVD enable voltae select 3.3V 3.3LVD enable voltae select 3.6V 3.6LVD enable voltae select 4.0V 4.0
Rev. 1.00 16 st 1 01 Rev. 1.00 1 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Symbol ParameterTest Conditions
Min. Typ. Max. UnitVDD Conditions
ILVRLVDBG Operatin Crrent
3V LVD enable LVR enableVBGEN = 0
— — 18μA
5V — 0 53V LVD enable LVR enable
VBGEN = 1— — 150
μA5V — 180 00
tLVDS LVDO Stable Time— For LVR enable VBGEN = 0
LVD off → on — — 15μs
— For LVR disable VBGEN = 0LVD off → on — — 150
tLVRMinimm Low Voltae Width to Reset — — 10 40 480 μs
tLVDMinimm Low Voltae Width to Interrpt — — 60 10 40 μs
ILVR dditional Crrent for LVR Enable — LVD disable VBGEN = 0 — — 4 μAILVD dditional Crrent for LVD Enable — LVR disable VBGEN = 0 — — 4 μA
Power-on Reset CharacteristicsTa=5°C
Symbol ParameterTest Conditions
Min. Typ. Max. UnitVDD Conditions
VPOR VDD Start Voltae to Ensre Power-on Reset — — — — 100 mVRRPOR VDD Risin Rate to Ensre Power-on Reset — — 0.035 — — V/ms
tPORMinimm Time for VDD Stays at VPOR to Ensre Power-on Reset — — 1 — — ms
VDD
tPOR RRPOR
VPOR
Time
Rev. 1.00 16 st 1 01 Rev. 1.00 1 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
System ArchitectureAkeyfactorinthehigh-performancefeaturesoftheHoltekrangeofmicrocontrollersisattributedtotheirinternalsystemarchitecture.ThedevicetakesadvantageoftheusualfeaturesfoundwithinRISCmicrocontrollersproviding increasedspeedofoperationandPeriodicperformance.Thepipeliningschemeisimplementedinsuchawaythatinstructionfetchingandinstructionexecutionareoverlapped,henceinstructionsareeffectivelyexecutedinonecycle,withtheexceptionofbranchorcall instructions.An8-bitwideALUisusedinpracticallyall instructionsetoperations,whichcarriesoutarithmeticoperations,logicoperations,rotation,increment,decrement,branchdecisions,etc.The internaldatapath issimplifiedbymovingdata throughtheAccumulatorandtheALU.Certain internalregistersare implemented in theDataMemoryandcanbedirectlyor indirectlyaddressed.Thesimpleaddressingmethodsof theseregistersalongwithadditionalarchitecturalfeaturesensurethataminimumofexternalcomponentsisrequiredtoprovideafunctionalI/OandA/Dcontrolsystemwithmaximumreliabilityandflexibility.Thismakesthedevicesuitableforlow-cost,high-volumeproductionforcontrollerapplications
Clocking and PipeliningThemainsystemclock,derivedfromeitheraHIRCorLIRCoscillator issubdivided intofourinternallygeneratednon-overlappingclocks,T1~T4.TheProgramCounter is incrementedat thebeginningoftheT1clockduringwhichtimeanewinstructionisfetched.TheremainingT2~T4clockscarryoutthedecodingandexecutionfunctions.Inthisway,oneT1~T4clockcycleformsoneinstructioncycle.Althoughthefetchingandexecutionofinstructionstakesplaceinconsecutiveinstructioncycles, thepipeliningstructureof themicrocontrollerensures that instructionsareeffectivelyexecuted inone instructioncycle.Theexception to thisare instructionswhere thecontentsoftheProgramCounterarechanged,suchassubroutinecallsorjumps,inwhichcasetheinstructionwilltakeonemoreinstructioncycletoexecute.
Fetch Inst. (PC+)Execte Inst. (PC+1)
Oscillator Clock(System Clock)
Phase Clock T1
Phase Clock T
Phase Clock T3
Phase Clock T4
Proram Conter
Pipelinin
PC PC+1 PC+
Fetch Inst. (PC+1)Execte Inst. (PC)
Execte Inst. (PC-1)Fetch Inst. (PC)
System Clock and Pipelining
For instructions involvingbranches,suchas jumporcall instructions, twomachinecyclesarerequired tocomplete instructionexecution.Anextracycle is requiredas theprogramtakesonecycletofirstobtaintheactualjumporcalladdressandthenanothercycletoactuallyexecutethebranch.Therequirementforthisextracycleshouldbetakenintoaccountbyprogrammersintimingsensitiveapplications.
Rev. 1.00 18 st 1 01 Rev. 1.00 19 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Execte Inst. 1Fetch Inst.
1 MOV [1H] CLL DELY3 CPL [1H]4 :5 :6 DELY: NOP
Fetch Inst. 1Execte Inst. Fetch Inst. 3 Flsh Pipeline
Fetch Inst. 6 Execte Inst. 6Fetch Inst.
Instruction Fetching
Program CounterDuringprogramexecution, theProgramCounter isused tokeep trackof theaddressof thenext instruction tobeexecuted. It isautomatically incrementedbyoneeach timean instructionisexecutedexcept for instructions, suchas"JMP"or"CALL" thatdemanda jump toanon-consecutiveProgramMemoryaddress.Onlythelower8bits,knownastheProgramCounterLowRegister,aredirectlyaddressablebytheapplicationprogram.
Whenexecuting instructions requiring jumps tonon-consecutiveaddresses suchas a jumpinstruction,asubroutinecall, interruptorreset,etc., themicrocontrollermanagesprogramcontrolbyloadingtherequiredaddressintotheProgramCounter.Forconditionalskipinstructions,oncetheconditionhasbeenmet,thenextinstruction,whichhasalreadybeenfetchedduringthepresentinstructionexecution,isdiscardedandadummycycletakesitsplacewhilethecorrectinstructionisobtained.
Program CounterProgram Counter High byte PCL Register
PC10~PC8 PCL~PCL0
Thelowerbyteof theProgramCounter,knownastheProgramCounterLowregisterorPCL,isavailableforprogramcontrolandisareadableandwriteableregister.Bytransferringdatadirectlyintothisregister,ashortprogramjumpcanbeexecuteddirectly,however,asonlythis lowbyteisavailableformanipulation, the jumpsare limited to thepresentpageofmemory, that is256locations.Whensuchprogramjumpsareexecuted itshouldalsobenoted thatadummycyclewillbeinserted.ManipulatingthePCLregistermaycauseprogrambranching,soanextracycleisneededtopre-fetch.
StackThis isaspecialpartof thememorywhichisusedtosavethecontentsof theProgramCounteronly.Thestackisneitherpartofthedatanorpartoftheprogramspace,andisneitherreadablenorwriteable.TheactivatedlevelisindexedbytheStackPointer,andisneitherreadablenorwriteable.Atasubroutinecallorinterruptacknowledgesignal,thecontentsoftheProgramCounterarepushedontothestack.Attheendofasubroutineoraninterruptroutine,signaledbyareturninstruction,RETorRETI,theProgramCounterisrestoredtoitspreviousvaluefromthestack.Afteradevicereset,theStackPointerwillpointtothetopofthestack.
Ifthestackisfullandanenabledinterrupttakesplace,theinterruptrequestflagwillberecordedbuttheacknowledgesignalwillbeinhibited.WhentheStackPointer isdecremented,byRETorRETI,theinterruptwillbeserviced.Thisfeaturepreventsstackoverflowallowingtheprogrammertousethestructuremoreeasily.However,whenthestackisfull,aCALLsubroutineinstructioncanstillbeexecutedwhichwillresult inastackoverflow.Precautionsshouldbetakentoavoidsuchcaseswhichmightcauseunpredictableprogrambranching.Ifthestackisoverflow,thefirstProgramCountersaveinthestackwillbelost.
Rev. 1.00 18 st 1 01 Rev. 1.00 19 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Stack Pointer
Stack Level
Stack Level 1
Stack Level 3
:::
Stack Level 6
Proram Memory
Proram Conter
Bottom of Stack
Top of Stack
Arithmetic and Logic Unit – ALUThearithmetic-logicunitorALUisacriticalareaofthemicrocontrollerthatcarriesoutarithmeticandlogicoperationsoftheinstructionset.Connectedtothemainmicrocontrollerdatabus,theALUreceivesrelatedinstructioncodesandperformstherequiredarithmeticor logicaloperationsafterwhichtheresultwillbeplacedinthespecifiedregister.AstheseALUcalculationoroperationsmayresultincarry,borroworotherstatuschanges,thestatusregisterwillbecorrespondinglyupdatedtoreflectthesechanges.TheALUsupportsthefollowingfunctions:
• Arithmeticoperations:ADD,ADDM,ADC,ADCM,SUB,SUBM,SBC,SBCM,DAA
• Logicoperations:AND,OR,XOR,ANDM,ORM,XORM,CPL,CPLA
• Rotation:RRA,RR,RRCA,RRC,RLA,RL,RLCA,RLC
• IncrementandDecrement:INCA,INC,DECA,DEC
• Branchdecision:JMP,SZ,SZA,SNZ,SIZ,SDZ,SIZA,SDZA,CALL,RET,RETI
Flash Program MemoryTheProgramMemoryisthelocationwheretheusercodeorprogramisstored.ForthedevicetheProgramMemory isFlash type,whichmeans itcanbeprogrammedandre-programmeda largenumberof times,allowingtheuser theconvenienceofcodemodificationonthesamedevice.Byusingtheappropriateprogrammingtools,theFlashdeviceoffersuserstheflexibilitytoconvenientlydebuganddeveloptheirapplicationswhilealsoofferingameansoffieldprogrammingandupdating.
StructureTheProgramMemoryhasacapacityof2K×15bits.TheProgramMemoryisaddressedbytheProgramCounterandalsocontainsdata,tableinformationandinterruptentries.Tabledata,whichcanbesetupinanylocationwithintheProgramMemory,isaddressedbyaseparatetablepointerregister.
000H
004H
0CH
FFH
Reset
Interrpt Vector
15 bits
Program Memory Structure
Rev. 1.00 0 st 1 01 Rev. 1.00 1 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Special VectorsWithintheProgramMemory,certainlocationsarereservedfortheresetandinterrupts.Thelocation000His reservedforuseby thedevicesreset forprograminitialisation.Afteradevicereset isinitiated,theprogramwilljumptothislocationandbeginexecution.
Look-up TableAnylocationwithintheProgramMemorycanbedefinedasalook-uptablewhereprogrammerscanstorefixeddata.Tousethelook-uptable,thetablepointermustfirstbesetupbyplacingtheaddressofthelookupdatatoberetrievedinthetablepointerregisters,TBLPandTBHP.Theseregistersdefinethetotaladdressofthelook-uptable.
Aftersettingupthetablepointer,thetabledatacanberetrievedfromtheProgramMemoryusingthe"TABRD[m]"or"TABRDL[m]"instructions,respectively.Whentheinstructionisexecuted,the lowerorder tablebyte from theProgramMemorywillbe transferred to theuserdefinedDataMemoryregister[m]asspecified in the instruction.Thehigherorder tabledatabytefromtheProgramMemorywillbe transferred to theTBLHspecial register.Anyunusedbits in thistransferredhigherorderbytewillbereadas"0".
Theaccompanyingdiagramillustratestheaddressingdataflowofthelook-uptable.
PC Hih Byte
TBLP Reister
Proram Memory
TBLH Reister User Selected Reister
ddress
Data15 bits
Data Hih Byte Data Low Byte
Last pae or TBHP Reister
Table Program ExampleThefollowingexampleshowshowthetablepointerandtabledataisdefinedandretrievedfromthemicrocontroller.ThisexampleusesrawtabledatalocatedintheProgramMemorywhichisstoredthereusingtheORGstatement.ThevalueatthisORGstatementis"700H"whichreferstothestartaddressofthelastpagewithinthe2KwordsProgramMemoryofthedevice.Thetablepointerissetupheretohaveaninitialvalueof"06H".ThiswillensurethatthefirstdatareadfromthedatatablewillbeattheProgramMemoryaddress"706H"or6locationsafterthestartofthelastpage.NotethatthevalueforthetablepointerisreferencedtotheaddressspecifiedbyTBLPandTBHPif the"TABRD[m]"instructionisbeingused.Thehighbyteofthetabledatawhichinthiscaseisequal tozerowillbetransferredtotheTBLHregisterautomaticallywhenthe"TABRDL[m]"instructionisexecuted.Because theTBLHregister isaread-onlyregisterandcannotberestored,careshouldbe takentoensure itsprotection ifboth themain routineand InterruptServiceRoutineuse table readinstructions. Ifusing the tableread instructions, theInterruptServiceRoutinesmaychange thevalueoftheTBLHandsubsequentlycauseerrorsifusedagainbythemainroutine.Asaruleitisrecommendedthatsimultaneoususeofthetablereadinstructionsshouldbeavoided.However, insituationswheresimultaneoususecannotbeavoided,theinterruptsshouldbedisabledpriortotheexecutionofanymainroutinetable-readinstructions.Notethatalltablerelatedinstructionsrequiretwoinstructioncyclestocompletetheiroperation.
Rev. 1.00 0 st 1 01 Rev. 1.00 1 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Table Read Program Exampletempreg1 db ? ; temporary register #1tempreg2 db ? ; temporary register #2::mov a,06h ; initialise low table pointer - note that this address is referencedmov tblp,a ; to the last page or the page that tbhp pointed::tabrdl tempreg1 ; transfers value in table referenced by table pointer data at program ; memory address "706H" transferred to tempreg1 and TBLHdec tblp ; reduce value of table pointer by onetabrdl tempreg2 ; transfers value in table referenced by table pointer data at program ; memory address "705H" transferred to tempreg2 and TBLH in this ; example the data "1AH" is transferred to tempreg1 and data "0FH" to ; register tempreg2::org 700h ; sets initial address of program memorydc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh::
In Circuit ProgrammingTheprovisionofFlashtypeProgramMemoryprovidestheuserwithameansofconvenientandeasyupgradesandmodificationstotheirprogramsonthesamedevice.Asanadditionalconvenience,Holtekhasprovidedameansofprogrammingthemicrocontrollerin-circuitusinga4-pininterface.Thisprovidesmanufacturerswiththepossibilityofmanufacturingtheircircuitboardscompletewithaprogrammedorun-programmedmicrocontroller,andthenprogrammingorupgradingtheprogramata laterstage.Thisenablesproductmanufacturers toeasilykeep theirmanufacturedproductssuppliedwiththelatestprogramreleaseswithoutremovalandre-insertionofthedevice.
Holtek Write Pins MCU Programming Pins FunctionICPD P0 Prorammin Serial DataICPCK P Prorammin Serial ClockVDD VDD Power SpplyVSS VSS Grond
TheProgramMemoryandEEPROMdatamemorycanbothbeprogrammedseriallyin-circuitusingthis4-wireinterface.Dataisdownloadedanduploadedseriallyonasinglepinwithanadditionallinefortheclock.Twoadditionallinesarerequiredforthepowersupplyandground.Thetechnicaldetailsregardingthein-circuitprogrammingofthedevicearebeyondthescopeofthisdocumentandwillbesuppliedinsupplementaryliterature.
Rev. 1.00 st 1 01 Rev. 1.00 3 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
*
Writer_VDD
ICPD
ICPCK
Writer_VSS
To other Circit
VDD
P0
P
VSS
Writer Connector Sinals
MCU ProramminPins
*
Note:*mayberesistororcapacitor.Theresistanceof*mustbegreaterthan1kÙorthecapacitanceof*mustbelessthan1nF.
On-Chip Debug Support – OCDSThereisanEVchipwhichisusedtoemulatetherealdevice.ThisEVchipdevicealsoprovidesan"On-ChipDebug"functiontodebugthedeviceduringthedevelopmentprocess.TheEVchipandtheactualMCUdevicearealmostfunctionallycompatibleexceptfor the"On-ChipDebug"function.UserscanusetheEVchipdevicetoemulatetherealchipdevicebehaviorbyconnectingtheOCDSDAandOCDSCKpinstotheHoltekHT-IDEdevelopmenttools.TheOCDSDApinistheOCDSData/Address input/outputpinwhile theOCDSCKpin is theOCDSclockinputpin.WhenusersusetheEVchipfordebugging,otherfunctionswhicharesharedwiththeOCDSDAandOCDSCKpinsinthedevicewillhavenoeffectintheEVchip.However,thetwoOCDSpinswhicharepin-sharedwiththeICPprogrammingpinsarestillusedastheFlashMemoryprogrammingpinsforICP.FormoredetailedOCDSinformation,refertothecorrespondingdocumentnamed"Holteke-Linkfor8-bitMCUOCDSUser’sGuide".
Holtek e-Link Pins EV Chip Pins Pin DescriptionOCDSD OCDSD On-chip Deb Spport Data/ddress inpt/otptOCDSCK OCDSCK On-chip Deb Spport Clock inpt
VDD VDD Power SpplyGND VSS Grond
Rev. 1.00 st 1 01 Rev. 1.00 3 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Data MemoryTheDataMemoryisavolatileareaof8-bitwideRAMinternalmemoryandisthelocationwheretemporaryinformationisstored.
StructureDividedintotwosections,thefirstoftheseisanareaofRAM,knownastheSpecialFunctionDataMemory.Herearelocatedregisterswhicharenecessaryforcorrectoperationofthedevice.Manyoftheseregisterscanbereadfromandwrittentodirectlyunderprogramcontrol,however,someremainprotectedfromusermanipulation.ThesecondareaofDataMemoryisknownastheGeneralPurposeDataMemory,whichisreservedforgeneralpurposeuse.Alllocationswithinthisareaarereadandwriteaccessibleunderprogramcontrol.
TheoverallDataMemoryissubdividedintotwobanks.TheSpecialPurposeDataMemoryregistersarealmostlocatedinBank0,whiletheEECregisterisataddress40HinBank1.SwitchingbetweenthedifferentDataMemorybanksisachievedbysettingtheBankPointertothecorrectvalue.ThestartaddressoftheDataMemoryistheaddress00H.
MCU Special PurposeData Memory
MCU General PurposeData Memory
Located Banks Capacity Address
0 1 18×8 Bank 0: 40H~BFH
Data Memory Summary
00H
Bank 0
40H
BFH
Special Prpose Data Memory
General Prpose Data Memory
EEC Reister(40H in Bank1)
Data Memory Structure
General Purpose Data MemoryThereisa128bytegeneralpurposedatamemorywhichisarrangedinBank0.Allmicrocontrollerprogramsrequireanareaofread/writememorywheretemporarydatacanbestoredandretrievedforuselater.ItisthisareaofRAMmemorythatisknownasGeneralPurposeDataMemory.ThisareaofDataMemoryisfullyaccessiblebytheuserprogramingforbothreadingandwritingoperations.Byusingthebitoperation instructions individualbitscanbesetorresetunderprogramcontrolgivingtheuseralargerangeofflexibilityforbitmanipulationintheDataMemory.
Rev. 1.00 4 st 1 01 Rev. 1.00 5 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Special Purpose Data MemoryThis area ofDataMemory iswhere registers, necessary for the correct operation of themicrocontroller,arestored.Mostof theregistersarebothreadableandwriteablebutsomeareprotectedandarereadableonly,thedetailsofwhicharelocatedundertherelevantSpecialFunctionRegistersection.Notethatforlocationsthatareunused,anyreadinstructiontotheseaddresseswillreturnthevalue"00H".
00H01H0H03H04H05H06H0H08H09H0H0BH0CH0DH0EH0FH10H11H1H
19H18H
1BH1H
1DH1CH
1FH
13H14H15H16H1H
40H
1EH
Bank 10H1HH
9H8H
BHH
DHCH
FHEH
3H4H5H6HH
30H31H3H
38H
3CH
33H34H35H36H3H
3BH
39H3H
3DH
3FH3EH
EEC
IR0MP0IR1MP1
CCPCLTBLPTBLHTBHP
STTUS
PWU
RSTFC
WDTCTB0C
SCCHIRCC
INTCP
PCPPU
Bank 0
PSCREE
TB1C
BP
INTEGINTC0INTC1
Bank 1 Bank 0
: Unsed read as“00”
STM0C1STM0DLSTM0DHSTM0LSTM0H
PBPBC
PBPUSTM1C0STM1C1STM1DLSTM1DHSTM1L
STM1RPPS0PS1PBS0
STM1H
EED
SDOLSDOHSDC0SDC1
RSTCLVDC
STM0C0
Special Purpose Data Memory Structure
Rev. 1.00 4 st 1 01 Rev. 1.00 5 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Special Function Register DescriptionMostoftheSpecialFunctionRegisterdetailswillbedescribedintheirrelevantfunctionalsection,howeverseveralregistersrequireaseparatedescriptioninthissection.
Indirect Addressing Registers – IAR0, IAR1TheIndirectAddressingRegisters,IAR0andIAR1,althoughhavingtheirlocationsinnormalDataMemoryregisterspace,donotactuallyphysicallyexistasnormalregisters.Themethodofindirectaddressing forRAMdatamanipulationuses these IndirectAddressingRegistersandMemoryPointers, incontrast todirectmemoryaddressing,wheretheactualmemoryaddressisspecified.ActionsontheIAR0andIAR1registerswill result innoactualreadorwriteoperationto theseregistersbutrathertothememorylocationspecifiedbytheircorrespondingMemoryPointers,MP0orMP1.Actingasapair, IAR0andMP0cantogetheraccessdatafromBank0while theIAR1andMP1registerpaircanaccessdatafromanybank.AstheIndirectAddressingRegistersarenotphysicallyimplemented,readingtheIndirectAddressingRegistersindirectlywillreturnaresultof"00H"andwritingtotheregistersindirectlywillresultinnooperation.
Memory Pointers – MP0, MP1TwoMemoryPointers, knownasMP0andMP1areprovided.TheseMemoryPointers arephysicallyimplementedintheDataMemoryandcanbemanipulatedinthesamewayasnormalregistersprovidingaconvenientwaywithwhichtoaddressandtrackdata.WhenanyoperationtotherelevantIndirectAddressingRegistersiscarriedout,theactualaddressthatthemicrocontrollerisdirectedtoistheaddressspecifiedbytherelatedMemoryPointer.MP0,togetherwithIndirectAddressingRegister,IAR0,areusedtoaccessdatafromBank0,whileMP1andIAR1areusedtoaccessdatafromallbanksaccordingtoBPregister.DirectAddressingcanonlybeusedwithBank0,allotherBanksmustbeaddressedindirectlyusingMP1andIAR1.
ThefollowingexampleshowshowtoclearasectionoffourDataMemorylocationsalreadydefinedaslocationsadres1toadres4.
Indirect Addressing Program Exampledata .section ´data´adres1 db ?adres2 db ?adres3 db ?adres4 db ?block db ? code .section at 0 code´org 00hstart: mov a, 04h ; setup size of block mov block, a mova,offsetadres1;AccumulatorloadedwithfirstRAMaddress movmp0,a ;setupmemorypointerwithfirstRAMaddressloop: clrIAR0 ;clearthedataataddressdefinedbymp0 inc mp0 ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loopcontinue:
Theimportantpointtonotehereisthatintheexampleshownabove,noreferenceismadetospecificDataMemoryaddresses.
Rev. 1.00 6 st 1 01 Rev. 1.00 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Bank Pointer – BPFor thisdevice, theDataMemory isdivided into twobanks,Bank0andBank1.Selecting therequiredDataMemoryareaisachievedusingtheBankPointer.Bit0oftheBankPointerisusedtoselectDataMemoryBanks0~1.
TheDataMemoryisinitialisedtoBank0afterareset,exceptforaWDTtime-outresetintheIDLEorSLEEPMode, inwhichcase, theDataMemorybankremainsunaffected.ItshouldbenotedthattheSpecialFunctionDataMemoryisnotaffectedbythebankselection,whichmeansthattheSpecialFunctionRegisterscanbeaccessedfromwithinanybank.Directlyaddressing theDataMemorywillalwaysresultinBank0beingaccessedirrespectiveofthevalueoftheBankPointer.AccessingdatafromBank1mustbeimplementedusingIndirectAddressing.
BP Register Bit 7 6 5 4 3 2 1 0
Name — — — — — — — DMBP0R/W — — — — — — — R/WPOR — — — — — — — 0
Bit7~1 Unimplemented,readas"0"Bit0 DMBP0:SelectDataMemoryBank
0:Bank01:Bank1
Accumulator – ACCTheAccumulator iscentral to theoperationofanymicrocontrollerand isclosely relatedwithoperationscarriedoutby theALU.TheAccumulator is theplacewhereall intermediateresultsfromtheALUarestored.Without theAccumulator itwouldbenecessary towrite theresultofeachcalculationorlogicaloperationsuchasaddition,subtraction,shift,etc., totheDataMemoryresultinginhigherprogrammingandtimingoverheads.Data transferoperationsusually involvethetemporarystoragefunctionoftheAccumulator;forexample,whentransferringdatabetweenoneuser-definedregisterandanother, it isnecessary todo thisbypassing thedata throughtheAccumulatorasnodirecttransferbetweentworegistersispermitted.
Program Counter Low Register – PCLToprovideadditionalprogramcontrolfunctions, the lowbyteof theProgramCounter ismadeaccessibletoprogrammersbylocatingitwithintheSpecialPurposeareaoftheDataMemory.Bymanipulatingthisregister,directjumpstootherprogramlocationsareeasilyimplemented.LoadingavaluedirectlyintothisPCLregisterwillcauseajumptothespecifiedProgramMemorylocation,however,astheregisterisonly8-bitwide,onlyjumpswithinthecurrentProgramMemorypagearepermitted.Whensuchoperationsareused,notethatadummycyclewillbeinserted.
Look-up Table Registers – TBLP, TBHP, TBLHThesethreespecialfunctionregistersareusedtocontroloperationof thelook-uptablewhichisstoredintheProgramMemory.TBLPandTBHParethetablepointersandindicate thelocationwhere the tabledata is located.Theirvaluemustbesetupbeforeany tablereadcommandsareexecuted.Theirvaluecanbechanged,forexampleusingthe"INC"or"DEC"instructions,allowingforeasytabledatapointingandreading.TBLHisthelocationwherethehighorderbyteofthetabledataisstoredafteratablereaddatainstructionhasbeenexecuted.Notethatthelowerordertabledatabyteistransferredtoauserdefinedlocation.
Rev. 1.00 6 st 1 01 Rev. 1.00 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Status Register – STATUSThis8-bitregistercontainsthezeroflag(Z),carryflag(C),auxiliarycarryflag(AC),overflowflag(OV),powerdownflag(PDF),andwatchdogtime-outflag(TO).Thesearithmetic/logicaloperationandsystemmanagementflagsareusedtorecordthestatusandoperationofthemicrocontroller.
WiththeexceptionoftheTOandPDFflags,bitsinthestatusregistercanbealteredbyinstructionslikemostotherregisters.AnydatawrittenintothestatusregisterwillnotchangetheTOorPDFflag.Inaddition,operationsrelatedtothestatusregistermaygivedifferentresultsduetothedifferentinstructionoperations.TheTOflagcanbeaffectedonlybyasystempower-up,aWDTtime-outorbyexecutingthe"CLRWDT"or"HALT"instruction.ThePDFflagisaffectedonlybyexecutingthe"HALT"or"CLRWDT"instructionorduringasystempower-up.
TheZ,OV,ACandCflagsgenerallyreflectthestatusofthelatestoperations.
• Cissetifanoperationresultsinacarryduringanadditionoperationorifaborrowdoesnottakeplaceduringasubtractionoperation;otherwiseCiscleared.Cisalsoaffectedbyarotatethroughcarryinstruction.
• ACissetifanoperationresultsinacarryoutofthelownibblesinaddition,ornoborrowfromthehighnibbleintothelownibbleinsubtraction;otherwiseACiscleared.
• Zissetiftheresultofanarithmeticorlogicaloperationiszero;otherwiseZiscleared.
• OVissetifanoperationresultsinacarryintothehighest-orderbitbutnotacarryoutofthehighest-orderbit,orviceversa;otherwiseOViscleared.
• PDFisclearedbyasystempower-uporexecutingthe"CLRWDT"instruction.PDFissetbyexecutingthe"HALT"instruction.
• TOisclearedbyasystempower-uporexecutingthe"CLRWDT"or"HALT"instruction.TOissetbyaWDTtime-out.
Inaddition,onenteringaninterruptsequenceorexecutingasubroutinecall,thestatusregisterwillnotbepushedontothestackautomatically.Ifthecontentsofthestatusregistersareimportantandifthesubroutinecancorruptthestatusregister,precautionsmustbetakentocorrectlysaveit.
Rev. 1.00 8 st 1 01 Rev. 1.00 9 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
STATUS RegisterBit 7 6 5 4 3 2 1 0
Name — — TO PDF OV Z C CR/W — — R R R/W R/W R/W R/WPOR — — 0 0 x x x x
"x" nknownBit7~6 Unimplemented,readas"0"Bit5 TO:WatchdogTime-outflag
0:Afterpoweruporexecutingthe"CLRWDT"or"HALT"instruction1:Awatchdogtime-outoccurred.
Bit4 PDF:Powerdownflag0:Afterpoweruporexecutingthe"CLRWDT"instruction1:Byexecutingthe"HALT"instruction
Bit3 OV:Overflowflag0:Nooverflow1:Anoperationresultsinacarryintothehighest-orderbitbutnotacarryoutofthehighest-orderbitorviceversa.
Bit2 Z:Zeroflag0:Theresultofanarithmeticorlogicaloperationisnotzero1:Theresultofanarithmeticorlogicaloperationiszero
Bit1 AC:Auxiliaryflag0:Noauxiliarycarry1:Anoperationresultsinacarryoutofthelownibblesinaddition,ornoborrowfromthehighnibbleintothelownibbleinsubtraction
Bit0 C:Carryflag0:Nocarry-out1:Anoperationresultsinacarryduringanadditionoperationorifaborrowdoesnottakeplaceduringasubtractionoperation
The"C"flagisalsoaffectedbyarotatethroughcarryinstruction.
Rev. 1.00 8 st 1 01 Rev. 1.00 9 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
EEPROM Data MemoryThisdevicecontainsanareaof internalEEPROMDataMemory.EEPROM,whichstands forElectricallyErasableProgrammableReadOnlyMemory, isby itsnatureanon-volatile formof re-programmablememory,withdata retentionevenwhen itspowersupply is removed.Byincorporating thiskindofdatamemory,awholenewhostofapplicationpossibilitiesaremadeavailabletothedesigner.TheavailabilityofEEPROMstorageallowsinformationsuchasproductidentificationnumbers,calibrationvalues,specificuserdata,systemsetupdataorotherproductinformationtobestoreddirectlywithin theproductmicrocontroller.TheprocessofreadingandwritingdatatotheEEPROMmemoryhasbeenreducedtoaverytrivialaffair.
EEPROM Data Memory StructureTheEEPROMDataMemorycapacityis64×8bitsforthedevice.UnliketheProgramMemoryandRAMDataMemory, theEEPROMDataMemoryisnotdirectlymappedintomemoryspaceandisthereforenotdirectlyaddressableinthesamewayastheothertypesofmemory.ReadandWriteoperationsto theEEPROMarecarriedout insinglebyteoperationsusinganaddressandadataregisterinBank0andasinglecontrolregisterinBank1.
EEPROM RegistersThreeregisterscontroltheoveralloperationoftheinternalEEPROMDataMemory.Thesearetheaddressregisters,EEA,thedataregister,EEDandasinglecontrolregister,EEC.AsboththeEEAandEEDregistersarelocatedinBank0,theycanbedirectlyaccessedinthesamewayasanyotherSpecialFunctionRegister.TheEECregisterhowever,beinglocatedinBank1,cannotbedirectlyaddressedandcanonlybereadfromorwrittentoindirectlyusingtheMP1MemoryPointerandIndirectAddressingRegister,IAR1.BecausetheEECcontrolregisterislocatedataddress40HinBank1,theMP1MemoryPointermustfirstbesettothevalue40HandtheBankPointerregister,BP,settothevalue,01H,beforeanyoperationsontheEECregisterareexecuted.
Register Name
Bit7 6 5 4 3 2 1 0
EE — — EE5 EE4 EE3 EE EE1 EE0EED D D6 D5 D4 D3 D D1 D0EEC — — — — WREN WR RDEN RD
EEPROM Register List
EEA RegisterBit 7 6 5 4 3 2 1 0
Name — — EE5 EE4 EE3 EE EE1 EE0R/W — — R/W R/W R/W R/W R/W R/WPOR — — 0 0 0 0 0 0
Bit7~6 Unimplemented,readas"0"Bit5~0 EEA5~EEA0:DataEEPROMaddressbit5~bit0
EED RegisterBit 7 6 5 4 3 2 1 0
Name D D6 D5 D4 D3 D D1 D0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0
Bit7~0 D7~D0:DataEEPROMdatabit7~bit0
Rev. 1.00 30 st 1 01 Rev. 1.00 31 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
EEC RegisterBit 7 6 5 4 3 2 1 0
Name — — — — WREN WR RDEN RDR/W — — — — R/W R/W R/W R/WPOR — — — — 0 0 0 0
Bit7~4 Unimplemented,readas"0"Bit3 WREN:DataEEPROMWriteEnable
0:Disable1:Enable
This is theDataEEPROMWriteEnableBitwhichmustbesethighbeforeDataEEPROMwriteoperationsarecarriedout.Clearingthisbit tozerowill inhibitDataEEPROMwriteoperations.
Bit2 WR:EEPROMWriteControl0:Writecyclehasfinished1:Activateawritecycle
This is theDataEEPROMWriteControlBitandwhensethighbytheapplicationprogramwillactivateawritecycle.Thisbitwillbeautomaticallyresettozerobythehardwareafterthewritecyclehasfinished.SettingthisbithighwillhavenoeffectiftheWRENhasnotfirstbeensethigh.
Bit1 RDEN:DataEEPROMReadEnable0:Disable1:Enable
This is theDataEEPROMReadEnableBitwhichmustbesethighbeforeDataEEPROMreadoperationsarecarriedout.Clearingthisbit tozerowill inhibitDataEEPROMreadoperations.
Bit0 RD:EEPROMReadControl0:Readcyclehasfinished1:Activateareadcycle
This is theDataEEPROMReadControlBitandwhensethighbytheapplicationprogramwillactivateareadcycle.Thisbitwillbeautomaticallyresettozerobythehardwareafterthereadcyclehasfinished.SettingthisbithighwillhavenoeffectiftheRDENhasnotfirstbeensethigh.
Note:TheWREN,WR,RDENandRDcannotbesethighatthesametimeinoneinstruction.TheWRandRDcannotbesethighatthesametime.
Reading Data from the EEPROMToreaddatafromtheEEPROM,thereadenablebit,RDEN,intheEECregistermustfirstbesethightoenablethereadfunction.TheEEPROMaddressofthedatatobereadmustthenbeplacedintheEEAregister.IftheRDbitintheEECregisterisnowsethigh,areadcyclewillbeinitiated.SettingtheRDbithighwillnotinitiateareadoperationif theRDENbithasnotbeenset.Whenthereadcycleterminates,theRDbitwillbeautomaticallyclearedtozero,afterwhichthedatacanbereadfromtheEEDregister.ThedatawillremainintheEEDregisteruntilanotherreadorwriteoperationisexecuted.Theapplicationprogramcanpoll theRDbit todeterminewhenthedataisvalidforreading.
Rev. 1.00 30 st 1 01 Rev. 1.00 31 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Writing Data to the EEPROMTheEEPROMaddressofthedatatobewrittenmustfirstbeplacedintheEEAregisterandthedataplacedintheEEDregister.TowritedatatotheEEPROM,thewriteenablebit,WREN,intheEECregistermustfirstbesethightoenablethewritefunction.Afterthis,theWRbitintheEECregistermustbe immediatelysethighto initiateawritecycle.These twoinstructionsmustbeexecutedconsecutively.Theglobal interruptbitEMIshouldalsofirstbeclearedbefore implementinganywriteoperations,andthensetagainafterthewritecyclehasstarted.NotethatsettingtheWRbithighwillnotinitiateawritecycleiftheWRENbithasnotbeenset.AstheEEPROMwritecycleiscontrolledusinganinternaltimerwhoseoperationisasynchronoustomicrocontrollersystemclock,acertaintimewillelapsebeforethedatawillhavebeenwrittenintotheEEPROM.DetectingwhenthewritecyclehasfinishedcanbeimplementedeitherbypollingtheWRbitintheEECregisterorbyusingtheEEPROMinterrupt.Whenthewritecycleterminates,theWRbitwillbeautomaticallycleared tozeroby themicrocontroller, informing theuser that thedatahasbeenwritten to theEEPROM.TheapplicationprogramcanthereforepolltheWRbittodeterminewhenthewritecyclehasended.
Write ProtectionProtectionagainst inadvertentwriteoperation isprovided inseveralways.After thedevice ispowered-on theWriteEnablebit in thecontrol registerwillbeclearedpreventinganywriteoperations.Alsoatpower-ontheBankPointer,BP,willbereset tozero,whichmeansthatDataMemoryBank0willbeselected.AstheEEPROMcontrolregisterislocatedinBank1,thisaddsafurthermeasureofprotectionagainstspuriouswriteoperations.Duringnormalprogramoperation,ensuringthattheWriteEnablebitinthecontrolregisterisclearedwillsafeguardagainstincorrectwriteoperations.
EEPROM InterruptTheEEPROMwriteinterruptisgeneratedwhenanEEPROMwritecyclehasended.TheEEPROMinterruptmustfirstbeenabledbysettingtheDEEbit in therelevant interruptregister.WhenanEEPROMwritecycleends,theDEFrequestflagwillbeset.IftheglobalandEEPROMinterruptareenabledandthestackisnotfull,ajumptotheEEPROMInterruptvectorwilltakeplace.WhentheEEPROMinterruptisserviced,theEEPROMinterruptflagwillbeautomaticallyreset.MoredetailscanbeobtainedintheInterruptsection.
Rev. 1.00 3 st 1 01 Rev. 1.00 33 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Programming ConsiderationsCaremustbe taken thatdata isnot inadvertentlywritten to theEEPROM.ProtectioncanbeenhancedbyensuringthattheWriteEnablebitisnormallyclearedtozerowhennotwriting.AlsotheBankPointercouldbenormallyclearedtozeroasthiswouldinhibitaccesstoBank1wheretheEEPROMcontrolregisterexists.Althoughcertainlynotnecessary,considerationmightbegivenintheapplicationprogramtothecheckingofthevalidityofnewwritedatabyasimplereadbackprocess.
WhenwritingdatatheWRbitmustbesethighimmediatelyaftertheWRENbithasbeensethigh,toensurethewritecycleexecutescorrectly.Theglobal interruptbitEMIshouldalsobeclearedbeforeawritecycleisexecutedandthenre-enabledafterthewritecyclestarts.Notethatthedeviceshouldnotenter theIDLEorSLEEPmodeuntil theEEPROMreadorwriteoperationis totallycomplete.Otherwise,theEEPROMreadorwriteoperationwillfail.
Programming Examples• Reading data from the EEPROM – polling methodMOVA,EEPROM_ADRES ;userdefinedaddressMOVEEA,AMOVA,040H ;setupmemorypointerMP1MOVMP1,A ;MP1pointstoEECregisterMOVA,01H ;setupBankPointerMOVBP,ASETIAR1.1 ;setRDENbit,enablereadoperationsSETIAR1.0 ;startReadCycle-setRDbitBACK:SZIAR1.0 ;checkforreadcycleendJMPBACKCLRIAR1 ;disableEEPROMwriteCLRBPMOVA,EED ;movereaddatatoregisterMOVREAD_DATA,A
• Writing Data to the EEPROM – polling methodMOVA,EEPROM_ADRES ;userdefinedaddressMOVEEA,AMOVA,EEPROM_DATA ;userdefineddataMOVEED,AMOVA,040H ;setupmemorypointerMP1MOVMP1,A ;MP1pointstoEECregisterMOVA,01H ;setupBankPointerMOVBP,ACLREMISETIAR1.3 ;setWRENbit,enablewriteoperationsSETIAR1.2 ;startWriteCycle-setWRbit–executedimmediately ;aftersetWRENbitSETEMIBACK:SZIAR1.2 ;checkforwritecycleendJMPBACKCLRIAR1 ;disableEEPROMwriteCLRBP
Rev. 1.00 3 st 1 01 Rev. 1.00 33 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
OscillatorsVariousoscillatoroptionsoffer theuserawide rangeof functionsaccording to theirvariousapplication requirements.The flexible featuresof theoscillator functionsensure that thebestoptimisationcanbeachievedintermsofspeedandpowersaving.Oscillatorselectionsandoperationareselectedthroughtheapplicationprogrambyusingsomecontrolregisters.
Oscillator OverviewInadditiontobeingthesourceofthemainsystemclocktheoscillatorsalsoprovideclocksourcesfor theWatchdogTimerandTimeBaseInterrupts.Externaloscillators requiringsomeexternalcomponentsaswellasfullyintegratedinternaloscillators,requiringnoexternalcomponents,areprovidedtoformawiderangeofbothfastandslowsystemoscillators.Alloscillatoroptionsallcanbeselected throughregisterprogramming.Thehigherfrequencyoscillatorsprovidehigherperformancebutcarrywithit thedisadvantageofhigherpowerrequirements,whiletheoppositeisofcoursetrueforthelowerfrequencyoscillators.Withthecapabilityofdynamicallyswitchingbetweenfastandslowsystemclock, thedevicehavetheflexibility tooptimizetheperformance/powerratio,afeatureespeciallyimportantinpowersensitiveportableapplications.
Type Name FrequencyInternal Hih Speed RC HIRC /4MHzInternal Low Speed RC LIRC 3kHz
Oscillator Types
System Clock ConfigurationsThereare twomethodsofgeneratingthesystemclock,ahighspeedoscillatoranda lowspeedoscillator.Thehighspeedclocksissourcedfromtheinternal2/4MHzRCoscillator,HIRC.Thelowspeedoscillatoristheinternal32kHzRCoscillator,LIRC.Selectingwhethertheloworhighspeedoscillatorisusedasthesystemoscillatoris implementedusingtheCKS2~CKS0bits intheSCCregisterandasthesystemclockcanbedynamicallyselected.
Hih Speed Oscillator
PrescalerfH
fH/
fH/4
fH/8
fH/16
fH/3
fH/64
CKS~CKS0
fSYS
Low Speed Oscillator
fSUB
fSUB
WDTfLIRC
IDLESLEEP
IDLE0SLEEP
HIRC
LIRC
System Clock Configurations
Rev. 1.00 34 st 1 01 Rev. 1.00 35 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Internal High Speed RC Oscillator – HIRCTheinternalRCoscillatorisafullyintegratedsystemoscillatorrequiringnoexternalcomponents.TheinternalRCoscillatorhasthreeselectablefrequenciesof2MHzand4MHz.Devicetrimmingduringthemanufacturingprocessandtheinclusionofinternalfrequencycompensationcircuitsareusedtoensurethattheinfluenceofthepowersupplyvoltage,temperatureandprocessvariationsontheoscillationfrequencyareminimised.
Internal 32kHz Oscillator – LIRCThe Internal32kHzSystemOscillator is alsoa fully integratedRCoscillatorwitha typicalfrequencyof32kHzat5V, requiringnoexternalcomponents for its implementation.Devicetrimmingduringthemanufacturingprocessandtheinclusionofinternalfrequencycompensationcircuitsareusedtoensurethattheinfluenceofthepowersupplyvoltage,temperatureandprocessvariationsontheoscillationfrequencyareminimised.
Operating Modes and System ClocksPresentdayapplicationsrequirethat theirmicrocontrollershavehighperformancebutoftenstilldemandthattheyconsumeaslittlepoweraspossible,conflictingrequirementsthatareespeciallytrueinbatterypoweredportableapplications.Thefastclocksrequiredforhighperformancewillbytheirnatureincreasecurrentconsumptionandofcourseviceversa,lowerspeedclocksreducecurrentconsumption.AsHoltekhasprovidedthedevicewithbothhighandlowspeedclocksourcesandthemeanstoswitchbetweenthemdynamically, theusercanoptimisetheoperationof theirmicrocontrollertoachievethebestperformance/powerratio.
System ClocksThedevicehasmanydifferentclocksourcesforboththeCPUandperipheralfunctionoperation.Byprovidingtheuserwithawiderangeofclockoptionsusingregisterprogramming,aclocksystemcanbeconfiguredtoobtainmaximumapplicationperformance.
Themainsystemclock,cancomefromahighfrequency,fH,orlowfrequency,fSUB,source,andisselectedusingtheCKS2~CKS0bits intheSCCregister.ThehighspeedsystemclockissourcedfromtheHIRCoscillator,while the lowspeedsystemclocksource issourcedfromthe internalclockfSUBwhichissourcedbytheLIRCoscillator.Theotherchoice,whichisadividedversionofthehighspeedsystemoscillatorhasarangeoffH/2~fH/64.
Rev. 1.00 34 st 1 01 Rev. 1.00 35 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Hih Speed Oscillator
PrescalerfH
fH/
fH/4
fH/8
fH/16
fH/3
fH/64
CKS~CKS0
fSYS
Low Speed Oscillator
fSUB
fSUB
WDTfLIRC
IDLESLEEP
IDLE0SLEEP
HIRC
LIRC
fSUB
fSYS/4fSYS
CLKSEL[1:0]
fPSCPrescaler Time
Base 0/1
Device Clock Configurations
Note:WhenthesystemclocksourcefSYSisswitchedtofSUBfromfH,thehighspeedoscillatorcanbestoptoconservethepowerbyclearingthecorrespondinghighspeedoscillatorenablecontrolbit.ThusthereisnofH~fH/64forperipheralcircuittouse.
System Operation ModesThere are six differentmodesof operation for themicrocontroller, eachonewith its ownspecial characteristics andwhichcanbe chosenaccording to the specificperformanceandpowerrequirementsof theapplication.Thereare twomodesallowingnormaloperationof themicrocontroller,theFASTModeandSLOWMode.Theremainingfourmodes,theSLEEP,IDLE0,IDLE1andIDLE2ModeareusedwhenthemicrocontrollerCPUisswitchedofftoconservepower.
Operation Mode CPU
Related Register ValuefSYS fH fSUB fLIRC
FHIDEN FSIDEN CKS2~CKS0FST On x x 000~110 fH~fH/64 On On OnSLOW On x x 111 fSUB On/Off (1) On On
IDLE0 Off 0 1000~110 Off
Off On On111 On
IDLE1 Off 1 1 xxx On On On On
IDLE Off 1 0000~110 On
On Off On111 Off
SLEEP Off 0 0 xxx Off Off Off On ()
"x": Don’t careNote:1.ThefHclockwillbeswitchedonoroffbyconfiguringthecorrespondingoscillatorenable
bitintheSLOWmode.2.ThefLIRCclockwillbeswitchedonsincetheWDTfunctionisalwaysenabledevenintheSLEEPmode.
Rev. 1.00 36 st 1 01 Rev. 1.00 3 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
FAST ModeThis isoneof themainoperatingmodeswhere themicrocontroller has all of its functionsoperationalandwherethesystemclockisprovidedthehighspeedoscillator.Thismodeoperatesallowingthemicrocontroller tooperatenormallywithaclocksourcefromtheHIRChighspeedoscillator.Thehighspeedoscillatorwillhoweverfirstbedividedbyaratiorangingfrom1to64,theactualratiobeingselectedbytheCKS2~CKS0bitsintheSCCregister.Althoughahighspeedoscillatorisused,runningthemicrocontrolleratadividedclockratioreducestheoperatingcurrent.
SLOW ModeThisisalsoamodewherethemicrocontrolleroperatesnormallyalthoughnowwithaslowerspeedclocksource.TheclocksourceusedwillbefromfSUB.ThefSUBclockisderivedfromtheLIRCoscillator.
SLEEP ModeTheSLEEPModeisenteredwhenanHALTinstructionisexecutedandwhentheFHIDENandFSIDENbitbotharelow.IntheSLEEPmodetheCPUwillbestopped.ThefSUBclockprovidedtotheperipheralfunctionwillalsobestopped.HoweverthefLIRCclockstillcontinuestooperatesincetheWDTfunctionisenabled.
IDLE0 ModeTheIDLE0ModeisenteredwhenanHALTinstructionisexecutedandwhentheFHIDENbitintheSCCregister is lowandtheFSIDENbit intheSCCregister ishigh.IntheIDLE0ModetheCPUwillbeswitchedoffbutthelowspeedoscillatorwillbeturnedontodrivesomeperipheralfunctions.
IDLE1 ModeTheIDLE1ModeisenteredwhenanHALTinstructionisexecutedandwhentheFHIDENbitintheSCCregisterishighandtheFSIDENbitintheSCCregisterishigh.IntheIDLE1ModethesystemoscillatorwillbeinhibitedfromdrivingtheCPUbutmaycontinuetoprovideaclocktokeepsomeperipheralfunctionsoperational.IntheIDLE1Mode,thesystemoscillatorwillcontinuetorun,andthissystemoscillatormaybethehighorlowspeedoscillator.
IDLE2 ModeTheIDLE2ModeisenteredwhenanHALTinstructionisexecutedandwhentheFHIDENbitintheSCCregisterishighandtheFSIDENbitintheSCCregisterislow.IntheIDLE2ModetheCPUwillbeswitchedoffbutthehighspeedoscillatorwillbeturnedontoprovideaclocksourcetokeepsomeperipheralfunctionsoperational.
Control RegistersTheregisters,SCCandHIRCC,areused tocontrol thesystemclockand theHIRCoscillatorconfigurations.
Register Name
Bit7 6 5 4 3 2 1 0
SCC CKS CKS1 CKS0 — — — FHIDEN FSIDENHIRCC — — — — HIRC1 HIRC0 HIRCF HIRCEN
System Operating Mode Control Register List
Rev. 1.00 36 st 1 01 Rev. 1.00 3 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
SCC RegisterBit 7 6 5 4 3 2 1 0
Name CKS CKS1 CKS0 — — — FHIDEN FSIDENR/W R/W R/W R/W — — — R/W R/WPOR 0 0 0 — — — 0 0
Bit7~5 CKS2~CKS0:Systemclockselection000:fH
001:fH/2010:fH/4011:fH/8100:fH/16101:fH/32110:fH/64111:fSUB
Thesethreebitsareusedtoselectwhichclockisusedasthesystemclocksource.InadditiontothesystemclocksourcedirectlyderivedfromfHorfSUB,adividedversionofthehighspeedsystemoscillatorcanalsobechosenasthesystemclocksource.
Bit4~2 Unimplemented,readas0.Bit1 FHIDEN:HighFrequencyoscillatorcontrolwhenCPUisswitchedoff
0:Disable1:Enable
Thisbit isusedtocontrolwhether thehighspeedoscillator isactivatedorstoppedwhentheCPUisswitchedoffbyexecutingan"HALT"instruction.
Bit0 FSIDEN:LowFrequencyoscillatorcontrolwhenCPUisswitchedoff0:Disable1:Enable
Thisbit isusedtocontrolwhether the lowspeedoscillator isactivatedorstoppedwhen theCPU is switchedoffbyexecutingan "HALT" instruction.TheLIRCoscillatoriscontrolledbythisbit togetherwiththeWDTfunctionenablecontrol.Ifthisbitisclearedto0buttheWDTfunctionisenabled,theLIRCwillalsobeenabled.
HIRCC RegisterBit 7 6 5 4 3 2 1 0
Name — — — — HIRC1 HIRC0 HIRCF HIRCENR/W — — — — R/W R/W R R/WPOR — — — — 0 0 0 1
Bit7~4 Unimplemented,readas0.Bit3~2 HIRC1~HIRC0:HIRCfrequencyselection
00:2MHz01:4MHz11:2MHz
WhentheHIRCoscillator isenabled, theHIRCfrequencyischangedbychangingthesetwobits,theclockfrequencywillautomaticallybechangedaftertheHIRCFflagissetto1.
Bit1 HIRCF:HIRCoscillatorstableflag0:HIRCunstable1:HIRCstable
Thisbit isusedto indicatewhether theHIRCoscillator isstableornot.WhentheHIRCENbitissetto1toenabletheHIRCoscillatorortheHIRCfrequencyselectionischangedbyapplicationprogram,theHIRCFbitwillfirstbeclearedto0andthensetto1aftertheHIRCoscillatorisstable.
Bit0 HIRCEN:HIRCoscillatorenablecontrol0:Disable1:Enable
Rev. 1.00 38 st 1 01 Rev. 1.00 39 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Operating Mode SwitchingThedevicecanswitchbetweenoperatingmodesdynamicallyallowingtheusertoselect thebestperformance/powerratiofor thepresent taskinhand.Inthiswaymicrocontrolleroperationsthatdonotrequirehighperformancecanbeexecutedusingslowerclocksthusrequiringlessoperatingcurrentandprolongingbatterylifeinportableapplications.
Insimpleterms,ModeSwitchingbetweentheFASTModeandSLOWModeisexecutedusingtheCKS2~CKS0bitsintheSCCregisterwhileModeSwitchingfromtheFAST/SLOWModestotheSLEEP/IDLEModesisexecutedviatheHALTinstruction.WhenanHALTinstructionisexecuted,whetherthedeviceentertheIDLEModeortheSLEEPModeisdeterminedbytheconditionoftheFHIDENandFSIDENbitsintheSCCregister.
FASTfSYS=fH~fH/64
fH onCPU rnfSYS onfSUB on
SLOWfSYS=fSUBfSUB on
CPU rnfSYS onfH on/off
IDLE0HLT instrction exected
CPU stopFHIDEN=0FSIDEN=1
fH offfSUB on
IDLE1HLT instrction exected
CPU stopFHIDEN=1FSIDEN=1
fH onfSUB on
IDLE2HLT instrction exected
CPU stopFHIDEN=1FSIDEN=0
fH onfSUB off
SLEEPHLT instrction exected
CPU stopFHIDEN=0FSIDEN=0
fH offfSUB off
Rev. 1.00 38 st 1 01 Rev. 1.00 39 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
FAST Mode to SLOW Mode SwitchingWhenrunning in theFASTMode,whichuses thehighspeedsystemoscillator,and thereforeconsumesmorepower, the systemclock can switch to run in theSLOWModeby set theCKS2~CKS0bitsto"111"intheSCCregister.Thiswill thenusethelowspeedsystemoscillatorwhichwillconsumelesspower.Usersmaydecidetodothisforcertainoperationswhichdonotrequirehighperformanceandcansubsequentlyreducepowerconsumption.
TheSLOWModeissourcedfromtheLIRCoscillatorandthereforerequires thisoscillator tobestablebeforefullmodeswitchingoccurs.
FAST Mode
SLOW Mode
CKS~CKS0 = 111
SLEEP Mode
FHIDEN=0 FSIDEN=0HLT instrction is exected
IDLE0 Mode
FHIDEN=0 FSIDEN=1HLT instrction is exected
IDLE1 Mode
FHIDEN=1 FSIDEN=1HLT instrction is exected
IDLE2 Mode
FHIDEN=1 FSIDEN=0HLT instrction is exected
Rev. 1.00 40 st 1 01 Rev. 1.00 41 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
SLOW Mode to FAST Mode SwitchingInSLOWmodethesystemclockisderivedfromfSUB.WhensystemclockisswitchedbacktotheFASTmodefromfSUB,theCKS2~CKS0bitsshouldbesetto"000"~"110"andthenthesystemclockwillrespectivelybeswitchedtofH~fH/64.
However, if fH isnotused inSLOWmodeand thusswitchedoff, itwill takesometime tore-oscillateandstabilisewhenswitchingtotheFASTmodefromtheSLOWMode.ThisismonitoredusingtheHIRCFbit intheHIRCCregister.ThetimedurationrequiredforthehighspeedsystemoscillatorstabilizationisspecifiedintheSystemStartUpTimeCharacteristics.
FAST Mode
SLOW Mode
CKS~CKS0 = 000~110
SLEEP Mode
FHIDEN=0 FSIDEN=0HLT instrction is exected
IDLE0 Mode
FHIDEN=0 FSIDEN=1HLT instrction is exected
IDLE1 Mode
FHIDEN=1 FSIDEN=1HLT instrction is exected
IDLE2 Mode
FHIDEN=1 FSIDEN=0HLT instrction is exected
Entering the SLEEP ModeThereisonlyonewayforthedevicetoentertheSLEEPModeandthatistoexecutethe"HALT"instructionintheapplicationprogramwithboththeFHIDENandFSIDENbitsintheSCCregisterequalto"0".InthismodealltheclocksandfunctionswillbeswitchedoffexcepttheWDTfunction.Whenthisinstructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:
• Thesystemclockwillbestoppedandtheapplicationprogramwillstopatthe"HALT"instruction.
• TheDataMemorycontentsandregisterswillmaintaintheirpresentcondition.
• TheI/Oportswillmaintaintheirpresentconditions.
• Inthestatusregister,thePowerDownflag,PDF,willbesetandtheWatchdogtime-outflag,TO,willbecleared.
• TheWDTwillbeclearedandresumecountingastheWDTfunctionisalwaysenabled.
Rev. 1.00 40 st 1 01 Rev. 1.00 41 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Entering the IDLE0 ModeThereisonlyonewayforthedevicetoentertheIDLE0Modeandthatistoexecutethe"HALT"instructionintheapplicationprogramwiththeFHIDENbitintheSCCregisterequalto"0"andtheFSIDENbitintheSCCregisterequalto"1".Whenthisinstructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:
• ThefHclockwillbestoppedandtheapplicationprogramwillstopatthe"HALT"instruction,butthefSUBclockwillbeon.
• TheDataMemorycontentsandregisterswillmaintaintheirpresentcondition.
• TheI/Oportswillmaintaintheirpresentconditions.
• Inthestatusregister,thePowerDownflag,PDF,willbesetandtheWatchdogtime-outflag,TO,willbecleared.
• TheWDTwillbeclearedandresumecountingastheWDTfunctionisalwaysenabled.
Entering the IDLE1 ModeThereisonlyonewayforthedevicetoentertheIDLE1Modeandthatistoexecutethe"HALT"instructionintheapplicationprogramwithboththeFHIDENandFSIDENbitsintheSCCregisterequalto"1".Whenthisinstructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:
• ThefHandfSUBclockswillbeonbuttheapplicationprogramwillstopatthe"HALT"instruction.
• TheDataMemorycontentsandregisterswillmaintaintheirpresentcondition.
• TheI/Oportswillmaintaintheirpresentconditions.
• Inthestatusregister,thePowerDownflag,PDF,willbesetandtheWatchdogtime-outflag,TO,willbecleared.
• TheWDTwillbeclearedandresumecountingastheWDTfunctionisalwaysenabled.
Entering the IDLE2 ModeThereisonlyonewayforthedevicetoentertheIDLE2Modeandthatistoexecutethe"HALT"instructionintheapplicationprogramwiththeFHIDENbitintheSCCregisterequalto"1"andtheFSIDENbitintheSCCregisterequalto"0".Whenthisinstructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:
• ThefHclockwillbeonbutthefSUBclockwillbeoffandtheapplicationprogramwillstopatthe"HALT"instruction.
• TheDataMemorycontentsandregisterswillmaintaintheirpresentcondition.
• TheI/Oportswillmaintaintheirpresentconditions.
• Inthestatusregister,thePowerDownflag,PDF,willbesetandtheWatchdogtime-outflag,TO,willbecleared.
• TheWDTwillbeclearedandresumecountingastheWDTfunctionisalwaysenabled.
Rev. 1.00 4 st 1 01 Rev. 1.00 43 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Standby Current ConsiderationsAsthemainreasonforenteringtheSLEEPorIDLEModeistokeepthecurrentconsumptionofthedevicetoaslowavalueaspossible,perhapsonlyintheorderofseveralmicro-ampsintheIDLE0andSLEEPMode,thereareotherconsiderationswhichmustalsobetakenintoaccountbythecircuitdesignerifthepowerconsumptionistobeminimised.SpecialattentionmustbemadetotheI/Opinsonthedevice.Allhigh-impedanceinputpinsmustbeconnectedtoeitherafixedhighorlowlevelasanyfloatinginputpinscouldcreateinternaloscillationsandresultinincreasedcurrentconsumption.Thisalsoappliestothedevicewhichhasdifferentpackagetypes,astheremaybeunbondedpins.Thesemusteitherbesetupasoutputsorifsetupasinputsmusthavepull-highresistorsconnected.
Caremustalsobetakenwiththeloads,whichareconnectedtoI/Opins,whicharesetupasoutputs.Theseshouldbeplacedinaconditioninwhichminimumcurrent isdrawnorconnectedonlytoexternalcircuitsthatdonotdrawcurrent,suchasotherCMOSinputs.
In theIDLE1andIDLE2Modethehighspeedoscillator ison, if theperipheral functionclocksourceisderivedfromthehighspeedoscillator,theadditionalstandbycurrentwillalsobeperhapsintheorderofseveralhundredmicro-amps.
Wake-upTominimisepowerconsumptionthedevicecanenter theSLEEPoranyIDLEMode,wherethesystemclocksourcetotheCPUwillbestopped.However,whenthedeviceiswokenupagain,itwilltakeaconsiderabletimefortheoriginalsystemoscillatortorestart,stabiliseandallownormaloperationtoresume.
AfterthesystementerstheSLEEPorIDLEMode,itcanbewokenupfromoneofvarioussourceslistedasfollows:
• Anexternalpinreset
• AnexternalfallingedgeonPortA
• Asysteminterrupt
• AWDToverflow
IfthesystemWhenthedeviceexecutesthe"HALT"instruction,itwillenterthePowerdownmodeandthePDFflagwillbesethigh.ThePDFflagisclearedto0ifthedeviceexperiencesasystempower-uporexecutestheclearWatchdogTimerinstruction.
Ifthesystemiswokenupbyanexternalpinreset, thedevicewillexperienceafullsystemreset,however,ifthedeviceiswokenupbyaWDToverflow,aWatchdogTimerTime-outresetwillbeinitiatedandtheTOflagwillbeset to1.TheTOflagissethighifaWDTtime-outoccurs,andcausesawake-upthatonlyresetstheProgramCounterandStackPointer,theotherflagsremainintheiroriginalstatus.
EachpinonPortAcanbesetupusingthePAWUregister topermitanegativetransitiononthepintowake-upthesystem.Whenapinwake-upoccurs,theprogramwillresumeexecutionattheinstructionfollowingthe"HALT"instruction.
Ifthesystemiswokenupbyaninterrupt,thentwopossiblesituationsmayoccur.Thefirstiswheretherelatedinterrupt isdisabledor theinterrupt isenabledbut thestackisfull, inwhichcasetheprogramwillresumeexecutionattheinstructionfollowingthe"HALT"instruction.Inthissituation,theinterruptwhichwoke-upthedevicewillnotbeimmediatelyserviced,butwillratherbeservicedlaterwhentherelated interrupt isfinallyenabledorwhenastacklevelbecomesfree.Theothersituationiswheretherelatedinterruptisenabledandthestackisnotfull,inwhichcasetheregularinterruptresponsetakesplace.IfaninterruptrequestflagissethighbeforeenteringtheSLEEPorIDLEMode,thewake-upfunctionoftherelatedinterruptwillbedisabled.
Rev. 1.00 4 st 1 01 Rev. 1.00 43 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Watchdog TimerTheWatchdogTimerisprovidedtopreventprogrammalfunctionsorsequencesfromjumpingtounknownlocations,duetocertainuncontrollableexternaleventssuchaselectricalnoise.
Watchdog Timer Clock SourceTheWatchdogTimerclocksourceisprovidedbytheinternalclock,fLIRCwhichissourcedfromtheLIRCoscillator.TheLIRCinternaloscillatorhasanapproximatefrequencyof32kHzandthisspecifiedinternalclockperiodcanvarywithVDD,temperatureandprocessvariations.TheWatchdogTimersourceclockisthensubdividedbyaratioof28to218togivelongertimeouts,theactualvaluebeingchosenusingtheWS2~WS0bitsintheWDTCregister.
Watchdog Timer Control RegisterAsingleregister,WDTC,controlstherequiredtimeoutperiodaswellastheenableandresetMCUoperation.
WDTC RegisterBit 7 6 5 4 3 2 1 0
Name WE4 WE3 WE WE1 WE0 WS WS1 WS0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 1 0 1 0 0 1 1
Bit7~3 WE4~WE0:WDTfunctionsoftwarecontrol01010/10101:EnableOthers:ResetMCU
Whenthesebitsarechangedbytheenvironmentalnoiseorsoftwaresettingtoresetthemicrocontroller,theresetoperationwillbeactivatedafteradelaytime,tSRESETandtheWRFbitintheRSTFCregisterwillbesethigh.
Bit2~0 WS2~WS0:WDTtime-outperiodselection000:28/fLIRC001:210/fLIRC010:212/fLIRC011:214/fLIRC100:215/fLIRC101:216/fLIRC110:217/fLIRC111:218/fLIRC
These threebitsdetermine thedivisionratioof thewatchdog timersourceclock,whichinturndeterminesthetime-outperiod.
RSTFC RegisterBit 7 6 5 4 3 2 1 0
Name — — — — RSTF LVRF — WRFR/W — — — — R/W R/W — R/WPOR — — — — 0 x — 0
"x"nknownBit7~4 Unimplemented,readas"0"Bit3 RSTF:RSTCregistersoftwareresetflag
DescribedelsewhereBit2 LVRF:LVRfunctionresetflag
DescribedelsewhereBit1 Unimplemented,readas"0"
Rev. 1.00 44 st 1 01 Rev. 1.00 45 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Bit0 WRF:WDTCregistersoftwareresetflag0:Notoccurred1:Occurred
Thisbitissetto1bytheWDTCregistersoftwareresetandclearedbytheapplicationprogram.Notethatthisbitcanbeclearedto0onlybytheapplicationprogram.
Watchdog Timer OperationTheWatchdogTimeroperatesbyprovidingadeviceresetwhenits timeroverflows.ThismeansthatintheapplicationprogramandduringnormaloperationtheuserhastostrategicallycleartheWatchdogTimerbeforeitoverflowstopreventtheWatchdogTimerfromexecutingareset.Thisisdoneusingtheclearwatchdoginstruction.Iftheprogrammalfunctionsforwhateverreason,jumpstoanunknownlocation,orentersanendlessloop,theclearinstructionwillnotbeexecutedinthecorrectmanner,inwhichcasetheWatchdogTimerwilloverflowandresetthedevice.Therearefivebits,WE4~WE0,intheWDTCregistertooffertheenablecontrolandresetcontroloftheWatchdogTimer.TheWDTfunctionwillbeenablediftheWE4~WE0bitsareequalto01010Bor10101B.IftheWE4~WE0bitsaresettoanyothervalues,otherthan01010Band10101B,itwillresetthedeviceafteradelaytime,tSRESET.Afterpoweronthesebitswillhaveavalueof01010B.
WE4~WE0 Bits WDT Function01010B or 10101B Enableny other vales Reset MCU
Watchdog Timer Enable/Reset Control
Undernormalprogramoperation,aWatchdogTimertime-outwill initialiseadeviceresetandsetthestatusbitTOhigh.However,ifthesystemisintheSLEEPorIDLEMode,whenaWatchdogTimer time-outoccurs, theTObit in thestatus registerwillbesethighandonly theProgramCounterandStackPointerwillbereset.FourmethodscanbeadoptedtoclearthecontentsoftheWatchdogTimer.ThefirstisaWDTreset,whichmeansacertainvalueexcept01010Band10101BwrittenintotheWE4~WE0bits,thesecondisanexternalhardwarereset,whichmeansalowlevelontheexternalresetpin,thethirdisusingtheWatchdogTimersoftwareclearinstructionandthefourthisviaaHALTinstruction.
ThereisonlyonemethodofusingsoftwareinstructiontocleartheWatchdogTimer.Thatistousethesingle"CLRWDT"instructiontocleartheWDT.
Themaximumtimeoutperiod iswhenthe218divisionratio isselected.Asanexample,witha32kHzLIRCoscillatorasitssourceclock,thiswillgiveamaximumwatchdogperiodofaround8secondsforthe218divisionratio,andaminimumtimeoutof8msforthe28divisionration.
“CLR WDT”Instrction
8-stae Divider WDT Prescaler
WE4~WE0 bitsWDTC Reister Reset MCU
fLIRC fLIRC/8
8-to-1 MUX
CLR
WS~WS0 WDT Time-ot(8/fLIRC ~ 18/fLIRC)
“HLT”Instrction
LIRC
RES Pin Reset
Watchdog Timer
Rev. 1.00 44 st 1 01 Rev. 1.00 45 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Reset and InitialisationAresetfunctionisafundamentalpartofanymicrocontrollerensuringthat thedevicecanbesettosomepredeterminedcondition irrespectiveofoutsideparameters.Themost important resetconditionisafterpowerisfirstappliedtothemicrocontroller.Inthiscase, internalcircuitrywillensure that themicrocontroller,afterashortdelay,willbe inawelldefinedstateandready toexecutethefirstprograminstruction.Afterthispower-onreset,certainimportantinternalregisterswillbesettodefinedstatesbeforetheprogramcommences.OneoftheseregistersistheProgramCounter,whichwillberesettozeroforcingthemicrocontrollertobeginprogramexecutionfromthelowestProgramMemoryaddress.
Inaddition to thepower-onreset,situationsmayarisewhere it isnecessary toforcefullyapplyaresetconditionwhenthemicrocontroller isrunning.Oneexampleof this iswhereafterpowerhasbeenappliedandthemicrocontrollerisalreadyrunning,theRESlineisforcefullypulledlow.Insuchacase,knownasanormaloperationreset,someof themicrocontrollerregistersremainunchangedallowing themicrocontroller toproceedwithnormaloperationafter thereset line isallowedtoreturnhigh.
Another typeofreset iswhentheWatchdogTimeroverflowsandresets themicrocontroller.Alltypesofresetoperationsresultindifferentregisterconditionsbeingsetup.AnotherresetexistsintheformofaLowVoltageReset,LVR,whereafullresetisimplementedinsituationswherethepowersupplyvoltagefallsbelowacertainthreshold.
Reset FunctionsThereareseveralwaysinwhichamicrocontrollerresetcanoccur, througheventsoccurringbothinternallyandexternally:
Power-on ResetThemostfundamentalandunavoidablereset is theonethatoccursafterpowerisfirstappliedtothemicrocontroller.AswellasensuringthattheProgramMemorybeginsexecutionfromthefirstmemoryaddress,apower-onresetalsoensures thatcertainother registersarepreset toknownconditions.AlltheI/Oportandportcontrolregisterswillpowerupinahighconditionensuringthatallpinswillbefirstsettoinputs.
VDD
tRSTD+tSSTRES
Internal Reset
0.9VDD
Note:tRSTDispower-ondelay,typicaltime=48msPower-On Reset Timing Chart
RES Pin ResetAlthoughthemicrocontrollerhasaninternalRCresetfunction,if theVDDpowersupplyrisetimeisnot fastenoughordoesnotstabilisequicklyatpower-on, the internal reset functionmaybeincapableofprovidingproperresetoperation.Forthisreasonit isrecommendedthatanexternalRCnetworkisconnectedtotheRESpin,whoseadditionaltimedelaywillensurethattheRESpinremainslowforanextendedperiodtoallowthepowersupplytostabilise.Duringthistimedelay,normaloperationof themicrocontrollerwillbe inhibited.After theRES line reachesacertainvoltagevalue,theresetdelaytimetRSTDisinvokedtoprovideanextradelaytimeafterwhichthemicrocontrollerwillbeginnormaloperation.TheabbreviationSSTinthefiguresstandsforSystemStart-upTimer.
Rev. 1.00 46 st 1 01 Rev. 1.00 4 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
FormostapplicationsaresistorconnectedbetweenVDDandtheRESpinandacapacitorconnectedbetweenVSSandtheRESpinwillprovideasuitableexternalresetcircuit.Anywiringconnectedto theRESpinshouldbekeptasshortaspossible tominimizeanystraynoise interference.Forapplicationsthatoperatewithinanenvironmentwheremorenoiseispresent theEnhancedResetCircuitshownisrecommended.
VDD
VDD
RES
10kΩ~100kΩ
0.01µF**
1N4148*
VSS
0.1µF~1µF300Ω*
Note:"*"ItisrecommendedthatthiscomponentisaddedforaddedESDprotection"**"Itisrecommendedthatthiscomponentisaddedinenvironmentswherepowerlinenoiseissignificant
External RES Circuit
PullingtheRESPinlowusingexternalhardwarewillalsoexecuteadevicereset.Inthiscase,asinthecaseofotherresets,theProgramCounterwillresettozeroandprogramexecutioninitiatedfromthispoint.
Internal Reset
tRSTD+tSST
RES
0.9VDD0.4VDD
Note:tRSTDispower-ondelay,typicaltime=16msRES Reset Timing Chart
• RSTC External Reset Register
Bit 7 6 5 4 3 2 1 0Name RSTC RSTC6 RSTC5 RSTC4 RSTC3 RSTC RSTC1 RSTC0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 1 0 1 0 1 0 1
Bit7~0 RSTC7 ~ RSTC0:PB4/RESselection01010101:Configuredasinput/outputPB4pinfunction10101010:ConfiguredasexternalresetRESpinOtherValues:MCUreset(resetwillbeactiveaftertSRESETtimefordebouncetime)
AllresetwillresetthisregisterasPORvalueexceptWDTtimeoutHardwarewarmreset.
Rev. 1.00 46 st 1 01 Rev. 1.00 4 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Low Voltage Reset – LVRThemicrocontrollercontainsalowvoltageresetcircuit inordertomonitorthesupplyvoltageofthedeviceandprovideanMCUresetshouldthevaluefallbelowacertainpredefinedlevel.TheLVRfunctionisalwaysenabledduringtheFASTandSLOWmodeswithaspecificLVRvoltageVLVR.Ifthesupplyvoltageofthedevicedropstowithinarangeof0.9V~VLVRsuchasmightoccurwhenchangingthebattery,theLVRwillautomaticallyresetthedeviceinternallyandtheLVRFbitintheSMOD1registerwillalsobesetto1.ForavalidLVRsignal,alowvoltage,i.e.,avoltageintherangebetween0.9V~VLVRmustexistforgreaterthanthevaluetLVRspecifiedintheLVD/LVRElectricalCharacteristics.Ifthelowvoltagestatedoesnotexceedthisvalue,theLVRwillignorethelowsupplyvoltageandwillnotperformaresetfunction.TheactualVLVRis2.1V,theLVRwillresetthedeviceafteradelaytime,tSRESET.NotethattheLVRfunctionwillbeautomaticallydisabledwhenthedeviceenterstheSLEEP/IDLEmode.
LVR
Internal Reset
tRSTD + tSST
Note:tRSTDispower-ondelay,typicaltime=48msLow Voltage Reset Timing Chart
• RSTFC Register
Bit 7 6 5 4 3 2 1 0
Name — — — — RSTF LVRF — WRF
R/W — — — — R/W R/W — R/W
POR — — — — 0 x — 0
"x" nknownBit7~4 Unimplemented,readas"0"Bit3 RSTF:RSTCregistersoftwareresetflag
0:Notactive1:Active
Thisbit isset to1bytheRSTCregistersettingandclearedto0bytheapplicationprogram.Notethatthisbitcanonlybeclearedto0bytheapplicationprogramorPORreset.
Bit2 LVRF:LVRfunctionresetflag0:Notactive1:Active
Thisbitcanbeclearedto"0",butcannotbesetto"1"Bit1 Unimplemented,readas"0"Bit0 WRF:WDTCregistersoftwareresetflag
Describedelsewhere
Watchdog Time-out Reset during Normal OperationTheWatchdogtime-outflagTOwillbeset to"1"whenWatchdogtime-outResetduringnormaloperations.
WDT Time-ot
Internal ResettRSTD + tSST
Note:tRSTDispower-ondelay,typicaltime=16msWDT Time-out Reset during Normal Operation Timing Chart
Rev. 1.00 48 st 1 01 Rev. 1.00 49 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Watchdog Time-out Reset during SLEEP or IDLE ModeTheWatchdogtime-outResetduringSLEEPorIDLEModeisa littledifferentfromotherkindsofreset.MostoftheconditionsremainunchangedexceptthattheProgramCounterandtheStackPointerwillbeclearedto"0"andtheTOflagwillbesetto"1".RefertotheA.C.CharacteristicsfortSSTdetails.
WDT Time-ot
Internal ResettSST
WDT Time-out Reset during SLEEP or IDLE Timing Chart
Reset Initial ConditionsThedifferent typesofresetdescribedaffect theresetflagsindifferentways.Theseflags,knownasPDFandTOare located in thestatus registerandarecontrolledbyvariousmicrocontrolleroperations,suchas theSLEEPorIDLEModefunctionorWatchdogTimer.Thereset flagsareshowninthetable:
TO PDF RESET Conditions0 0 Power-on reset LVR reset 1 WDT time-ot reset drin FST or SLOW Mode 1 1 WDT time-ot reset drin IDLE or SLEEP Mode
Note:"u"standsforunchanged
Thefollowingtableindicatesthewayinwhichthevariouscomponentsofthemicrocontrollerareaffectedafterapower-onresetoccurs.
Item Condition After RESETProram Conter Reset to zeroInterrpts ll interrpts will be disabledWDT Clear after reset WDT beins continTimer Modles Timer Modles will be trned offInpt/Otpt Ports I/O ports will be setp as inpts Stack Pointer Stack Pointer will point to the top of the stack
Thedifferentkindsofresetsallaffecttheinternalregistersofthemicrocontrollerindifferentways.Toensurereliablecontinuationofnormalprogramexecutionafteraresetoccurs,itisimportanttoknowwhatconditionthemicrocontrolleris inafteraparticularresetoccurs.Thefollowingtabledescribeshoweachtypeofresetaffectseachof themicrocontroller internalregisters.Note thatwheremorethanonepackagetypeexiststhetablewillreflectthesituationforthelargerpackagetype.
Rev. 1.00 48 st 1 01 Rev. 1.00 49 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Register Reset (Power On) RES Reset LVR Reset WDT Time-out
(Normal Operation)WDT Time-out (SLEEP/IDLE)*
IR0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MP0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IR1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MP1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BP - - - - - - - 0 - - - - - - - 0 - - - - - - - 0 - - - - - - - 0 - - - - - - - CC x x x x x x x x x x x x x x x x PCL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TBLP x x x x x x x x x x x x x x x x TBLH - x x x x x x x - x x x x x x x - - - TBHP - - - - - x x x - - - - - x x x - - - - - - - - - - - - - - - STTUS - - 0 0 x x x x - - - - - - 1 - - 1 1 RSTFC - - - - 0 x - 0 - - - - - - - - - 1 - - - - - - - - - - - INTEG - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - INTC0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - INTC1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 PC 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 PPU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWU 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCC 0 0 0 - - - 0 0 0 0 0 - - - 0 0 0 0 0 - - - 0 0 0 0 0 - - - 0 0 - - - HIRCC - - - - 0 0 0 1 - - - - 0 0 0 1 - - - - 0 0 0 1 - - - - 0 0 0 1 - - - - WDTC 0 1 0 1 0 0 11 0 1 0 1 0 0 11 0 1 0 1 0 0 11 0 1 0 1 0 0 11 TB0C 0 - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - 0 0 0 - - - - TB1C 0 - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - 0 0 0 - - - - PSCR - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - EE - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - EED 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDOL (DRFS=0) x x x x - - - - x x x x - - - - x x x x - - - - x x x x - - - - - - - -SDOL (DRFS=1) x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x SDOH (DRFS=0) x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x SDOH (DRFS=1) - - - - x x x x - - - - x x x x - - - - x x x x - - - - x x x x - - - - SDC0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDC1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LVDC - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - RSTC 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 STM0C0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STM0C1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STM0DL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STM0DH - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - STM0L 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STM0H - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - 0 0 - - - - - - PB - 1 1 1 1 1 1 1 - 1 1 1 1 1 1 1 - 1 1 1 1 1 1 1 - 1 1 1 1 1 1 1 - PBC - 1 1 1 1 1 1 1 - 1 1 1 1 1 1 1 - 1 1 1 1 1 1 1 - 1 1 1 1 1 1 1 - PBPU - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 - STM1C0 0 0 0 0 0 - - - 0 0 0 0 0 - - - 0 0 0 0 0 - - - 0 0 0 0 0 - - - - - -STM1C1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Rev. 1.00 50 st 1 01 Rev. 1.00 51 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Register Reset (Power On) RES Reset LVR Reset WDT Time-out
(Normal Operation)WDT Time-out (SLEEP/IDLE)*
STM1DL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STM1DH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STM1L 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STM1H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STM1RP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PS0 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - 0 0 - - - - - -PS1 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - 0 0 0 0 0 0 - - - -PBS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EEC - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - 0 0 0 0 - - - - 0 0 0 0 - - - -
Note:"*"standsforwarmreset"-"standsfor"unimplemented""u"standsfor"unchanged""x"standsfor"unknown"
Rev. 1.00 50 st 1 01 Rev. 1.00 51 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Input/Output PortsHoltekmicrocontrollersofferconsiderableflexibilityontheirI/Oports.Withtheinputoroutputdesignationofeverypinfullyunderuserprogramcontrol,pull-highselectionsforallportsandwake-upselectionsoncertainpins,theuserisprovidedwithanI/Ostructuretomeettheneedsofawiderangeofapplicationpossibilities.
Thedeviceprovidebidirectionalinput/outputlineslabeledwithportnamesPA~PB.TheseI/Oportsaremappedto theRAMDataMemorywithspecificaddressesasshownin theSpecialPurposeDataMemorytable.Allof theseI/Oportscanbeusedforinputandoutputoperations.Forinputoperation,theseportsarenon-latching,whichmeanstheinputsmustbereadyattheT2risingedgeofinstruction"MOVA,[m]",wheremdenotestheportaddress.Foroutputoperation,allthedataislatchedandremainsunchangeduntiltheoutputlatchisrewritten.
Register Name
Bit
7 6 5 4 3 2 1 0
P P P6 P5 P4 P3 P P1 P0
PC PC PC6 PC5 PC4 PC3 PC PC1 PC0
PPU PPU PPU6 PPU5 PPU4 PPU3 PPU PPU1 PPU0
PWU PWU PWU6 PWU5 PWU4 PWU3 PWU PWU1 PWU0
PB — PB6 — PB4 PB3 PB PB1 PB0
PBC — PBC6 PBC5 PBC4 PBC3 PBC PBC1 PBC0
PBPU — PBPU6 PBPU5 PBPU4 PBPU3 PBPU PBPU1 PBPU0
I/O Logic Function Register List
Pull-high ResistorsManyproductapplicationsrequirepull-highresistorsfortheirswitchinputsusuallyrequiringtheuseofanexternal resistor.Toeliminate theneedfor theseexternal resistors,all I/Opins,whenconfiguredasaninputhavethecapabilityofbeingconnectedtoaninternalpull-highresistor.Thesepull-highresistorsareselectedusingregistersPAPU~PBPU,andare implementedusingweakPMOStransistors.
Notethatthepull-highresistorcanbecontrolledbytherelevantpull-highcontrolregisteronlywhenthepin-sharedfunctionalpinisselectedasalogicinputorNMOSoutput.Otherwise,thepull-highresistorscannotbeenabled.
PxPU RegisterBit 7 6 5 4 3 2 1 0
Name PxPU PxPU6 PxPU5 PxPU4 PxPU3 PxPU PxPU1 PxPU0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0
PxPUn:I/OPortxPinpull-highfunctioncontrol0:Disable1:EnableThePxPUnbitisusedtocontrolthepinpull-highfunction.Herethe"x"canbeAorB.However,theactualavailablebitsforeachI/OPortmaybedifferent.
Rev. 1.00 5 st 1 01 Rev. 1.00 53 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Port A Wake-upTheHALTinstructionforcesthemicrocontrollerintotheSLEEPorIDLEModewhichpreservespower,afeature that is importantforbatteryandother low-powerapplications.Variousmethodsexisttowake-upthemicrocontroller,oneofwhichistochangethelogicconditionononeofthePortApinsfromhightolow.Thisfunctionisespeciallysuitableforapplicationsthatcanbewokenupviaexternalswitches.EachpinonPortAcanbeselectedindividuallytohavethiswake-upfeatureusingthePAWUregister.
Notethat thewake-upfunctioncanbecontrolledbythewake-upcontrolregistersonlywhenthepin-sharedfunctionalpinisselectedasgeneralpurposeinput/outputandtheMCUenterstheIDLEorSLEEPmode.
PAWU RegisterBit 7 6 5 4 3 2 1 0
Name PWU PWU6 PWU5 PWU4 PWU3 PWU PWU1 PWU0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0
Bit7~0 PAWU7~PAWU0:PA7~PA0wake-upfunctioncontrol0:Disable1:Enable
I/O Port Control RegistersEach I/Oporthas itsowncontrol registerknownasPAC~PBC, to control the input/outputconfiguration.With this control register, eachCMOSoutput or input canbe reconfigureddynamicallyundersoftwarecontrol.Eachpinof theI/Oports isdirectlymappedtoabit in itsassociatedportcontrolregister.FortheI/Opintofunctionasaninput,thecorrespondingbitofthecontrolregistermustbewrittenasa"1".Thiswillthenallowthelogicstateoftheinputpintobedirectlyreadbyinstructions.Whenthecorrespondingbitofthecontrolregisteriswrittenasa"0",theI/OpinwillbesetupasaCMOSoutput.Ifthepiniscurrentlysetupasanoutput,instructionscanstillbeusedtoreadtheoutputregister.However,itshouldbenotedthattheprogramwillinfactonlyreadthestatusoftheoutputdatalatchandnottheactuallogicstatusoftheoutputpin.
PxC RegisterBit 7 6 5 4 3 2 1 0
Name PxC PxC6 PxC5 PxC4 PxC3 PxC PxC1 PxC0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 1 1 1 1 1 1 1 1
PxCn:I/OPortxPintypeselection0:Output1:InputThePxCnbitisusedtocontrolthepintypeselection.Herethe"x"canbeAorB.However,theactualavailablebitsforeachI/OPortmaybedifferent.
Rev. 1.00 5 st 1 01 Rev. 1.00 53 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Pin-shared FunctionsTheflexibilityofthemicrocontrollerrangeisgreatlyenhancedbytheuseofpinsthathavemorethanonefunction.Limitednumbersofpinscanforceseriousdesignconstraintsondesignersbutbysupplyingpinswithmulti-functions,manyofthesedifficultiescanbeovercome.Forthesepins,thedesiredfunctionofthemulti-functionI/Opinsisselectedbyaseriesofregistersviatheapplicationprogramcontrol.
Pin-shared Function Selection RegistersThelimitednumberofsuppliedpinsinapackagecanimposerestrictionsontheamountoffunctionsacertaindevicecancontain.Howeverbyallowingthesamepinstoshareseveraldifferentfunctionsandprovidingameansoffunctionselection,awiderangeofdifferentfunctionscanbeincorporatedintoevenrelativelysmallpackagesizes.ThedeviceincludesPort"x"pinsharedfunctionselectionregister, labeledasPxSn,whichcanselect thedesiredfunctionsof themulti-functionpin-sharedpins.
Whenthepin-sharedfunctionisselectedtobeused,thecorrespondinginputandoutputfunctionsselectionshouldbeproperlymanaged.Forexample, if theSTM0functionSTP0pinisused, thecorrespondingpin-shared functionshouldbeconfiguredas theSTP0functionbyconfiguringthePxSnregister.If theexternal interruptfunctionisselectedtobeused, therelevantpin-sharedfunctionshouldbeselectedasanI/Ofunctionwith thepin in input typeandthe interrupt inputsignalactiveedgeshouldbeselected.
Themostimportantpoint tonoteis tomakesurethat thedesiredpin-sharedfunctionisproperlyselectedandalsodeselected.Formostpin-sharedfunctions,toselectthedesiredpin-sharedfunction,thepin-sharedfunctionshouldfirstbecorrectlyselectedusingthecorrespondingpin-sharedcontrolregister.Afterthatthecorrespondingperipheralfunctionalsettingshouldbeconfiguredandthentheperipheralfunctioncanbeenabled.However,aspecialpointmustbenotedforsomedigitalinputpins,suchasINTn,STCKn,STPnI,etc,whichsharethesamepin-sharedcontrolconfigurationwiththeircorrespondinggeneralpurposeI/Ofunctionswhensettingtherelevantpin-sharedcontrolbitfields.Toselectthesepinfunctions,inadditiontothenecessarypin-sharedcontrolandperipheralfunctionalsetupaforementioned,theymustalsobesetupasaninputbysettingthecorrespondingbitintheI/Oportcontrolregister.Tocorrectlydeselectthepin-sharedfunction,theperipheralfunctionshouldfirstbedisabledand then thecorrespondingpin-sharedfunctioncontrol registercanbemodifiedtoselectotherpin-sharedfunctions.
RegisterName
Bit7 6 5 4 3 2 1 0
PS0 PS0 PS06 — — PS03 PS0 — —PS1 PS1 PS16 PS15 PS14 PS13 PS1 — —PBS0 PBS0 PBS06 PBS05 PBS04 PBS03 PBS0 PBS01 PBS00
Pin-shared Function Selection Register List
• PAS0 Register
Bit 7 6 5 4 3 2 1 0Name PS0 PS06 — — PS03 PS0 — —R/W R/W R/W — — R/W R/W — —POR 0 0 — — 0 0 — —
Bit7~6 PAS07~PAS06:PA3pinfunctionselectionbits00:PA3/STCK001:AN410:PA3/STCK011:PA3/STCK0
Rev. 1.00 54 st 1 01 Rev. 1.00 55 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Bit5~4 Unimplemented,readas"0"Bit3~2 PAS03~PAS02:PA1pinfunctionselectionbits
00:PA101:STP010:VREF11:PA1
Bit1~0 Unimplemented,readas"0"
• PAS1 Register
Bit 7 6 5 4 3 2 1 0Name PS1 PS16 PS15 PS14 PS13 PS1 — —R/W R/W R/W R/W R/W R/W R/W — —POR 0 0 0 0 0 0 — —
Bit7~6 PAS17~PAS16:PA7pinfunctionselectionbits00:PA701:AN710:PA711:PA7
Bit5~4 PAS15~PAS14:PA6pinfunctionselectionbits00:PA601:AN610:PA611:PA6
Bit3~2 PAS13~PAS12:PA5pinfunctionselectionbits00:PA5/STP0I01:AN510:PA5/STP0I11:PA5/STP0I
Bit1~0 Unimplemented,readas"0"
• PBS0 Register
Bit 7 6 5 4 3 2 1 0Name PBS0 PBS06 PBS05 PBS04 PBS03 PBS0 PBS01 PBS00R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0
Bit7~6 PBS07~PBS06:PB3pinfunctionselectionbits00:PB301:AN310:PB311:PB3
Bit5~4 PBS05~PBS04:PB2pinfunctionselectionbits00:PB2/STP1I01:AN210:PB2/STP1I11:PB2/STP1I
Bit3~2 PBS03~PBS02:PB1pinfunctionselectionbits00:PB1/STCK101:AN110:PB1/STCK111:PB1/STCK1
Bit1~0 PBS01~PBS00:PB0pinfunctionselectionbits00:PB001:STP110:AN011:PB0
Rev. 1.00 54 st 1 01 Rev. 1.00 55 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
I/O Pin StructuresTheaccompanyingdiagrams illustrate the internalstructuresofsomegeneric I/Opin types.AstheexactlogicalconstructionoftheI/Opinwilldifferfromthesedrawings,theyaresuppliedasaguideonlytoassistwiththefunctionalunderstandingoftheI/Opins.Thewiderangeofpin-sharedstructuresdoesnotpermitalltypestobeshown.
MUX
VDD
Control Bit
Data Bit
Data Bs
Write Control Reister
Chip Reset
Read Control Reister
Read Data Reister
Write Data Reister
System Wake-p wake-p Select
I/O pin
WeakPll-p
Pll-hihReisterSelect
Q
D
CK
Q
D
CK
Q
QS
S
P only
Generic Input/Output Structure
Programming ConsiderationsWithintheuserprogram,oneof thefirst thingstoconsider isport initialisation.Afterareset,alloftheI/Odataandportcontrolregisterswillbesethigh.ThismeansthatallI/Opinswilldefaulttoan inputstate, the levelofwhichdependsontheotherconnectedcircuitryandwhetherpull-highselectionshavebeenchosen.Iftheportcontrolregistersarethenprogrammedtosetupsomepinsasoutputs, theseoutputpinswillhaveaninitialhighoutputvalueunlesstheassociatedportdataregistersarefirstprogrammed.Selectingwhichpinsareinputsandwhichareoutputscanbeachievedbyte-widebyloadingthecorrectvalues into theappropriateportcontrolregisterorbyprogrammingindividualbits in theportcontrolregisterusing the"SET[m].i"and"CLR[m].i"instructions.Notethatwhenusingthesebitcontrolinstructions,aread-modify-writeoperationtakesplace.Themicrocontrollermustfirstreadinthedataontheentireport,modifyittotherequirednewbitvaluesandthenrewritethisdatabacktotheoutputports.
PortAhas theadditionalcapabilityofprovidingwake-upfunctions.When thedevice is in theSLEEPorIDLEMode,variousmethodsareavailabletowakethedeviceup.OneoftheseisahightolowtransitionofanyofthePortApins.SingleormultiplepinsonPortAcanbesetuptohavethisfunction.
Rev. 1.00 56 st 1 01 Rev. 1.00 5 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Timer Modules – TMOneofthemostfundamentalfunctionsinanymicrocontrollerdeviceistheabilitytocontrolandmeasure time.To implement timerelatedfunctions thedevice includesseveralTimerModules,abbreviated to thenameTM.TheTMsaremulti-purpose timingunits and serve toprovideoperationssuchasTimer/Counter,InputCapture,CompareMatchOutputandSinglePulseOutputaswellasbeingthefunctionalunitforthegenerationofPWMsignals.EachoftheTMshastwoindividual interrupts.Theadditionof inputandoutputpins foreachTMensures thatusersareprovidedwithtimingunitswithawideandflexiblerangeoffeatures.
Thegeneralfeaturesof thestandardtypeTMaredescribedherewithmoredetailedinformationprovidedintheStandardTypeTMsection.
IntroductionThedevicecontainstwoStandardTypeTMs,oneofwhichis10-bitandtheotheris16-bitwide,witheachTMhavingareferencenameofSTM0andSTM1.ThecommonfeaturestotheStandardTMswillbedescribedinthissectionandthedetailedoperationwillbedescribedincorrespondingsection.ThemainfeaturesoftheSTMaresummarisedintheaccompanyingtable.
Function STMTimer/Conter √Inpt Captre √Compare Match Otpt √PWM Channels 1Sinle Plse Otpt 1PWM linment EdePWM djstment Period & Dty Dty or Period
TM Function Summary
TM OperationTheStandard typeTMsofferadiverse rangeof functions, fromsimple timingoperations toPWMsignalgeneration.ThekeytounderstandinghowtheTMoperates is tosee it in termsofafreerunningcounterwhosevalueis thencomparedwiththevalueofpre-programmedinternalcomparators.Whenthefreerunningcounterhasthesamevalueasthepre-programmedcomparator,knownasacomparematchsituation,aTMinterruptsignalwillbegeneratedwhichcanclearthecounterandperhapsalsochangetheconditionoftheTMoutputpin.TheinternalTMcounter isdrivenbyauserselectableclocksource,whichcanbeaninternalclockoranexternalpin.
TM Clock SourcesTheclocksourcewhichdrives themaincounter ineachTMcanoriginatefromvarioussources.TheselectionoftherequiredclocksourceisimplementedusingtheSTnCK2~STnCK0bitsintheSTMnC0controlregisters.Theclocksourcecanbearatioofeither thesystemclockfSYSor theinternalhighclockfH,thefSUBclocksourceortheexternalSTCKnpin.TheSTCKnpinclocksourceisusedtoallowanexternalsignaltodrivetheTMasanexternalclocksourceorforeventcounting.
TM InterruptsTheStandardtypeTMseachhastwointernalinterrupts, theinternalcomparatorAorcomparatorP,whichgenerateaTMinterruptwhenacomparematchconditionoccurs.WhenaTMinterruptisgenerated,itcanbeusedtoclearthecounterandalsotochangethestateoftheTMoutputpin.
Rev. 1.00 56 st 1 01 Rev. 1.00 5 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
TM External PinsEachoftheSTMshastwoTMinputpins,withthelabelSTCKnandSTPnI.TheSTMninputpinSTCKn,isessentiallyaclocksourcefortheSTMnandisselectedusingtheSTnCK2~STnCK0bitsintheSTMnC0register.ThisexternalSTMninputpinallowsanexternalclocksourcetodrivetheinternalTM.TheSTCKninputpincanbechosentohaveeitherarisingorfallingactiveedge.
TheotherSTMninputpin,STPnI, is thecaptureinputwhoseactiveedgecanbearisingedge,afallingedgeorbothrisingandfallingedgesandtheactiveedgetransitiontypeisselectedusingtheSTnIO1andSTnIO0bitsintheSTMnC1register.
TheTMseachhasoneoutputpinwith the labelSTPn.WhentheTMis in theCompareMatchOutputMode, thepincanbecontrolledbytheTMtoswitchtoahighor lowlevelor to togglewhenacomparematchsituationoccurs.TheexternalSTPnoutputpinisalsothepinwheretheTMgeneratesthePWMoutputwaveform.AstheTMoutputpinsarepin-sharedwithotherfunction,theTMoutputfunctionmustfirstbesetupusingregisters.AsinglebitinoneoftheregistersdeterminesifitsassociatedpinistobeusedasanexternalTMoutputpinorifitistohaveanotherfunction.ThenumberofoutputpinsforeachTMtypeisdifferent,thedetailsareprovidedintheaccompanyingtable.
10-bit STM0 16-bit STM1Input Output Input Output
STCK0 STP0I STP0 STCK1 STP1I STP1
TM External Pins
TM Input/Output Pin ControlSelectingtohaveaTMinput/outputorwhethertoretainitsothersharedfunctionisimplementedusingtherelevantpin-sharedfunctionselectionregisters,withthecorrespondingselectionbits ineachpin-sharedfunctionregistercorrespondingtoaTMinput/outputpin.ConfiguringtheselectionbitscorrectlywillsetupthecorrespondingpinasaTMinput/output.Thedetailsofthepin-sharedfunctionselectionaredescribedinthepin-sharedfunctionsection.
STMn
STPn
STCKn
Captre Inpt
TCK Inpt
Otpt
STPnI
STMn Function Pin Control Block Diagram – n=0~1
Rev. 1.00 58 st 1 01 Rev. 1.00 59 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Programming ConsiderationsTheTMCounterRegistersandtheCapture/CompareCCRAregisters,allhavealowandhighbytestructure.Thehighbytescanbedirectlyaccessed,butasthelowbytescanonlybeaccessedviaaninternal8-bitbuffer,readingorwritingtotheseregisterpairsmustbecarriedoutinaspecificway.Theimportantpointtonoteisthatdatatransfertoandfromthe8-bitbufferanditsrelatedlowbyteonlytakesplacewhenawriteorreadoperationtoitscorrespondinghighbyteisexecuted.
AstheCCRAregistersareimplementedinthewayshowninthefollowingdiagramandaccessingtheregisteriscarriedoutinaspecificwaydescribedabove,itisrecommendedtousethe"MOV"instruction toaccess theCCRAlowbyteregister,namedSTMnAL,using thefollowingaccessprocedures.AccessingtheCCRAlowbyteregisterwithoutfollowingtheseaccessprocedureswillresultinunpredictablevalues.
Thefollowingstepsshowthereadandwriteprocedures:
• WritingDatatoCCRA♦ Step1.WritedatatoLowByteSTMnAL
– notethatheredataisonlywrittentothe8-bitbuffer.♦ Step2.WritedatatoHighByteSTMnAH
– heredata iswrittendirectly to thehighbyteregistersandsimultaneouslydata is latchedfromthe8-bitbuffertotheLowByteregisters.
• ReadingDatafromtheCounterRegistersandCCRA♦ Step1.ReaddatafromtheHighByteSTMnDHorSTMnAH
– heredataisreaddirectlyfromtheHighByteregistersandsimultaneouslydataislatchedfromtheLowByteregisterintothe8-bitbuffer.
♦ Step2.ReaddatafromtheLowByteSTMnDLorSTMnAL– thisstepreadsdatafromthe8-bitbuffer.
Rev. 1.00 58 st 1 01 Rev. 1.00 59 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Standard Type TM – STMTheStandardTypeTMcontainsfiveoperatingmodes,whichareCompareMatchOutput,Timer/EventCounter,CaptureInput,SinglePulseOutputandPWMOutputmodes.TheStandardTMcanbecontrolledwithtwoexternalinputpinsandcandriveoneexternaloutputpins.
TM Type TM Name TM Input Pin TM Output Pin10-bit STM STM0 STCK0 STP0I STP016-bit STM STM1 STCK1 STP1I STP1
fSYS
fSYS/4
fH/64fH/16
fSUB
STCK0
000001010011100101110111
ST0CK~ST0CK0
10-bit Cont-p Conter
3-bit Comparator P
CCRP
b~b9
b0~b9
10-bit Comparator
ST0ONST0PU
Comparator Match
Comparator P Match
Conter Clear 01
OtptControl
Polarity Control STP0
ST1OC
ST0M1 ST0M0ST0IO1 ST0IO0
STM0F Interrpt
STM0PF Interrpt
ST0POL
CCR
ST0CCLR
EdeDetector
ST0IO1 ST0IO0
fSUB
STP0I
10-bit Standard Type TM Block Diagram
fSYS
fSYS/4
fH/64fH/16
fSUB
STCK1
000001010011100101110111
ST1CK~ST1CK0
16-bit Cont-p Conter
8-bit Comparator P
CCRP
b8~b15
b0~b15
16-bit Comparator
ST1ONST1PU
Comparator Match
Comparator P Match
Conter Clear 01
OtptControl
Polarity Control STP1
ST1OC
ST1M1 ST1M0ST1IO1 ST1IO0
STM1F Interrpt
STM1PF Interrpt
ST1POL
CCR
ST1CCLR
EdeDetector
ST1IO1 ST1IO0
fSUB
STP1I
16-bit Standard Type TM Block DiagramNote:TheSTMnexternalpinsarepin-sharedwithI/Oorotherfunctions,sobeforeusingtheSTMnfunctions,the
pin-sharedfunctionregistersmustbesetproperlytoenabletheSTMnpinfunction.
Rev. 1.00 60 st 1 01 Rev. 1.00 61 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Standard TM OperationTherearetwosizesofStandardTMs,oneis10-bitwideandtheotheris16-bitwide.Itscoreisa10-bitor16-bitcount-upcounterwhichisdrivenbyauserselectableinternalclocksource.Therearealsotwointernalcomparatorswiththenames,ComparatorAandComparatorP.ThesecomparatorswillcomparethevalueinthecounterwithCCRPandCCRAregisters.TheCCRPis3-bitor8-bitwidewhosevalueiscomparedwiththehighest3bitsor8bitsinthecounterwhiletheCCRAisthe10bitsor16bitsandthereforecompareswithallcounterbits.
Theonlywayofchangingthevalueofthe10-bitor16-bitcounterusingtheapplicationprogram,istoclearthecounterbychangingtheSTnONbitfromlowtohigh.Thecounterwillalsobeclearedautomaticallybyacounteroverfloworacomparematchwithoneof itsassociatedcomparators.Whentheseconditionsoccur,aTMinterruptsignalwillalsousuallybegenerated.TheStandardTypeTMcanoperateinanumberofdifferentoperationalmodes,canbedrivenbydifferentclocksourcesandcanalsocontrolanoutputpin.Alloperatingsetupconditionsareselectedusingrelevantinternalregisters.
Standard Type TM Register DescriptionOveralloperationoftheStandardTMiscontrolledusingaseriesofregisters.Areadonlyregisterpairexiststostoretheinternalcounter10-bitor16-bitvalue,whilearead/writeregisterpairexiststostoretheinternal10-bitor16-bitCCRAvalue.Theremainingtworegistersarecontrolregisterswhichsetupthedifferentoperatingandcontrolmodes.For16-bitSTM,thereisanotherread/writeregisterexiststostoretheinternal8-bitCCRPvaluewhilefor10-bitSTM,the3-bitCCRPvaluearestoredintheSTMnC0register.
RegisterName
Bit7 6 5 4 3 2 1 0
STM0C0 ST0PU ST0CK ST0CK1 ST0CK0 ST0ON ST0RP ST0RP1 ST0RP0STM0C1 ST0M1 ST0M0 ST0IO1 ST0IO0 ST0OC ST0POL ST0DPX ST0CCLRSTM0DL D D6 D5 D4 D3 D D1 D0STM0DH — — — — — — D9 D8STM0L D D6 D5 D4 D3 D D1 D0STM0H — — — — — — D9 D8
10-bit Standard TM0 Register List
RegisterName
Bit7 6 5 4 3 2 1 0
STM1C0 ST1PU ST1CK ST1CK1 ST1CK0 ST1ON — — —STM1C1 ST1M1 ST1M0 ST1IO1 ST1IO0 ST1OC ST1POL ST1DPX ST1CCLRSTM1DL D D6 D5 D4 D3 D D1 D0STM1DH D15 D14 D13 D1 D11 D10 D9 D8STM1L D D6 D5 D4 D3 D D1 D0STM1H D15 D14 D13 D1 D11 D10 D9 D8STM1RP D D6 D5 D4 D3 D D1 D0
16-bit Standard TM1 Register List
Rev. 1.00 60 st 1 01 Rev. 1.00 61 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
STMnC0 Register – n=0Bit 7 6 5 4 3 2 1 0
Name STnPU STnCK STnCK1 STnCK0 STnON STnRP STnRP1 STnRP0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0
Bit7 STnPAU:STMCounterPauseControl0:Run1:Pause
Thecountercanbepausedbysettingthisbithigh.Clearingthebit tozerorestoresnormalcounteroperation.WheninaPauseconditiontheSTMwillremainpoweredupandcontinuetoconsumepower.Thecounterwillretainitsresidualvaluewhenthisbitchangesfromlowtohighandresumecountingfromthisvaluewhenthebitchangestoalowvalueagain.
Bit6~4 STnCK2~STnCK0:SelectSTMnCounterclock000:fSYS/4001:fSYS
010:fH/16011:fH/64100:fSUB
101:fSUB
110:STCKnrisingedgeclock111:STCKnfallingedgeclock
ThesethreebitsareusedtoselecttheclocksourcefortheSTM.Theexternalpinclocksourcecanbechosentobeactiveontherisingorfallingedge.TheclocksourcefSYSisthesystemclock,whilefHandfSUBareotherinternalclocks,thedetailsofwhichcanbefoundintheoscillatorsection.
Bit3 STnON:STMCounterOn/OffControl0:Off1:On
Thisbitcontrolstheoverallon/offfunctionoftheSTM.Settingthebithighenablesthecounter torun,clearingthebitdisables theSTM.Clearingthisbit tozerowillstop thecounterfromcountingand turnoff theSTMwhichwill reduce itspowerconsumption.Whenthebitchangesstatefromlowtohightheinternalcountervaluewillbereset tozero,howeverwhenthebitchangesfromhighto low, the internalcounterwillretainitsresidualvalueuntilthebitreturnshighagain.IftheSTMisintheCompareMatchOutputModeorthePWMoutputModeorSinglePulseOutputModethentheSTMoutputpinwillberesettoitsinitialcondition,asspecifiedbytheSTnOCbit,whentheSTnONbitchangesfromlowtohigh.
Bit2~0 STnRP2~STnRP0:STMnCCRP3-bitregister,comparedwiththeSTMnCounterbit9~bit7ComparatorPMatchPeriod000:1024STMnclocks001:128STMnclocks010:256STMnclocks011:384STMnclocks100:512STMnclocks101:640STMnclocks110:768STMnclocks111:896STMnclocks
ThesethreebitsareusedtosetupthevalueontheinternalCCRP3-bitregister,whichare thencomparedwith the internalcounter’shighest threebits.Theresultof thiscomparisoncanbeselectedtocleartheinternalcounteriftheSTnCCLRbitissettozero.SettingtheSTnCCLRbittozeroensuresthatacomparematchwiththeCCRPvalueswillreset theinternalcounter.AstheCCRPbitsareonlycomparedwiththehighest threecounterbits, thecomparevaluesexist in128clockcyclemultiples.Clearingall threebits tozero is ineffectallowing thecounter tooverflowat itsmaximumvalue.
Rev. 1.00 6 st 1 01 Rev. 1.00 63 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
STMnC0 Register – n=1Bit 7 6 5 4 3 2 1 0
Name STnPU STnCK STnCK1 STnCK0 STnON — — —R/W R/W R/W R/W R/W R/W — — —POR 0 0 0 0 0 — — —
Bit7 STnPAU:STMCounterPauseControl0:Run1:Pause
Thecountercanbepausedbysettingthisbithigh.Clearingthebit tozerorestoresnormalcounteroperation.WheninaPauseconditiontheSTMwillremainpoweredupandcontinuetoconsumepower.Thecounterwillretainitsresidualvaluewhenthisbitchangesfromlowtohighandresumecountingfromthisvaluewhenthebitchangestoalowvalueagain.
Bit6~4 STnCK2~STnCK0:SelectSTMnCounterclock000:fSYS/4001:fSYS
010:fH/16011:fH/64100:fSUB
101:fSUB
110:STCKnrisingedgeclock111:STCKnfallingedgeclock
ThesethreebitsareusedtoselecttheclocksourcefortheSTM.Theexternalpinclocksourcecanbechosentobeactiveontherisingorfallingedge.TheclocksourcefSYSisthesystemclock,whilefHandfSUBareotherinternalclocks,thedetailsofwhichcanbefoundintheoscillatorsection.
Bit3 STnON:STMCounterOn/OffControl0:Off1:On
Thisbitcontrolstheoverallon/offfunctionoftheSTM.Settingthebithighenablesthecounter torun,clearingthebitdisables theSTM.Clearingthisbit tozerowillstop thecounterfromcountingand turnoff theSTMwhichwill reduce itspowerconsumption.Whenthebitchangesstatefromlowtohightheinternalcountervaluewillbereset tozero,howeverwhenthebitchangesfromhighto low, the internalcounterwillretainitsresidualvalueuntilthebitreturnshighagain.IftheSTMisintheCompareMatchOutputModeorthePWMoutputModeorSinglePulseOutputModethentheSTMoutputpinwillberesettoitsinitialcondition,asspecifiedbytheSTnOCbit,whentheSTnONbitchangesfromlowtohigh.
Bit2~0 Unimplemented,readas"0"
STMnC1 Register – n=0~1Bit 7 6 5 4 3 2 1 0
Name STnM1 STnM0 STnIO1 STnIO0 STnOC STnPOL STnDPX STnCCLRR/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0
Bit7~6 STnM1~STnM0:SelectSTMnOperatingMode00:CompareMatchOutputMode01:CaptureInputMode10:PWMoutputModeorSinglePulseOutputMode11:Timer/CounterMode
ThesebitssetuptherequiredoperatingmodefortheSTM.ToensurereliableoperationtheSTMshouldbeswitchedoffbeforeanychangesaremade to theSTnM1andSTnM0bits.IntheTimer/CounterMode,theSTMoutputpinstateisundefined.
Rev. 1.00 6 st 1 01 Rev. 1.00 63 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Bit5~4 STnIO1~ STnIO0:SelectSTMnfunctionCompareMatchOutputMode00:Nochange01:Outputlow10:Outputhigh11:Toggleoutput
PWMoutputMode/SinglePulseOutputMode00:PWMOutputinactivestate01:PWMOutputactivestate10:PWMoutput11:Singlepulseoutput
CaptureInputMode00:InputcaptureatrisingedgeofSTPnI01:InputcaptureatfallingedgeofSTPnI10:Inputcaptureatfalling/risingedgeofSTPnI11:Inputcapturedisabled
Timer/counterMode:Unused
ThesetwobitsareusedtodeterminehowtheTMoutputpinchangesstatewhenacertainconditionisreached.ThefunctionthatthesebitsselectdependsuponinwhichmodetheTMisrunning.In theCompareMatchOutputMode, theSTnIO1~STnIO0bitsdeterminehowtheSTMnoutputpinchangesstatewhenacomparematchoccursfromtheComparatorA.TheTMoutputpincanbesetuptoswitchhigh,switchlowortotoggleitspresentstatewhenacomparematchoccursfromtheComparatorA.WhentheSTnIO1~STnIO0bitsarebothzero,thennochangewill takeplaceontheoutput.TheinitialvalueoftheTMoutputpinshouldbesetupusingtheSTnOCbit.Notethat theoutput levelrequestedbytheSTnIO1~STnIO0bitsmustbedifferentfromtheinitialvaluesetupusingtheSTnOCbitotherwisenochangewilloccurontheTMoutputpinwhenacomparematchoccurs.After theTMoutputpinchangesstate, itcanbereset toitsinitiallevelbychangingtheleveloftheSTnONbitfromlowtohigh.InthePWMOutputMode,theSTnIO1andSTnIO0bitsdeterminehowtheTMoutputpinchangesstatewhenacertaincomparematchconditionoccurs.ThePWMoutputfunctionismodifiedbychangingthesetwobits.ItisnecessarytochangethevaluesoftheSTnIO1andSTnIO0bitsonlyaftertheTMhasbeenswitchedoff.UnpredictablePWMoutputswilloccuriftheSTnIO1andSTnIO0bitsarechangedwhentheTMisrunning.
Bit3 STnOC:STMnOutputcontrolbitCompareMatchOutputMode0:Initiallow1:Initialhigh
PWMOutputMode/SinglePulseOutputMode0:Activelow1:Activehigh
This is theoutputcontrolbit for theSTMoutputpin. ItsoperationdependsuponwhetherSTMisbeingused in theCompareMatchOutputModeor in thePWMOutputMode/SinglePulseOutputMode.IthasnoeffectiftheSTMisintheTimer/CounterMode. In theCompareMatchOutputMode itdetermines the logic leveloftheSTMoutputpinbeforeacomparematchoccurs.InthePWMoutputModeitdeterminesifthePWMsignalisactivehighoractivelow.IntheSinglePulseOutputMode itdetermines the logic levelof theSTMoutputpinwhen theSTnONbitchangesfromlowtohigh.
Rev. 1.00 64 st 1 01 Rev. 1.00 65 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Bit2 STnPOL:STMnSTPnOutputpolarityControl0:Non-inverted1:Inverted
ThisbitcontrolsthepolarityoftheSTPnoutputpin.WhenthebitissethightheSTMoutputpinwillbeinvertedandnotinvertedwhenthebitiszero.IthasnoeffectiftheTMisintheTimer/CounterMode.
Bit1 STnDPX:STMnPWMperiod/dutyControl0:CCRP–period;CCRA–duty1:CCRP–duty;CCRA–period
Thisbit,determineswhichoftheCCRAandCCRPregistersareusedforperiodanddutycontrolofthePWMwaveform.
Bit0 STnCCLR:SelectSTMnCounterclearcondition0:STMnComparatorPmatch1:STMnComparatorAmatch
Thisbit isused toselect themethodwhichclears thecounter.Remember that theStandardTMcontainstwocomparators,ComparatorAandComparatorP,eitherofwhichcanbeselectedtocleartheinternalcounter.WiththeSTnCCLRbitsethigh,thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorA.Whenthebitislow,thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorPorwithacounteroverflow.AcounteroverflowclearingmethodcanonlybeimplementediftheCCRPbitsareallclearedtozero.TheSTnCCLRbitisnotusedinthePWMoutputmode,SinglePulseorInputCaptureMode.
STMnDL Register – n=0~1 Bit 7 6 5 4 3 2 1 0
Name D D6 D5 D4 D3 D D1 D0R/W R R R R R R R RPOR 0 0 0 0 0 0 0 0
Bit7~0 D7~D0:STMnCounterLowByteRegisterbit7~bit0STMn10-bit/16-bitCounterbit7~bit0
STMnDH Register – n=0 Bit 7 6 5 4 3 2 1 0
Name — — — — — — D9 D8R/W — — — — — — R RPOR — — — — — — 0 0
Bit7~2 Unimplemented,readas"0"Bit1~0 D9~D8:STMnCounterHighByteRegisterbit1~bit0
STMn10-bitCounterbit9~bit8
STMnDH Register – n=1 Bit 7 6 5 4 3 2 1 0
Name D15 D14 D13 D1 D11 D10 D9 D8R/W R R R R R R R RPOR 0 0 0 0 0 0 0 0
Bit7~0 D15~D8:STMnCounterHighByteRegisterbit7~bit0STMn16-bitCounterbit15~bit8
Rev. 1.00 64 st 1 01 Rev. 1.00 65 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
STMnAL Register – n=0~1Bit 7 6 5 4 3 2 1 0
Name D D6 D5 D4 D3 D D1 D0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0
Bit7~0 D7~D0:STMnCCRALowByteRegisterbit7~bit0STMn10-bit/16-bitCCRAbit7~bit0
STMnAH Register – n=0Bit 7 6 5 4 3 2 1 0
Name — — — — — — D9 D8R/W — — — — — — R/W R/WPOR — — — — — — 0 0
Bit7~2 Unimplemented,readas"0"Bit1~0 D9~D8:STMnCCRAHighByteRegisterbit1~bit0
STMn10-bitCCRAbit9~bit8
STMnAH Register – n=1Bit 7 6 5 4 3 2 1 0
Name D15 D14 D13 D1 D11 D10 D9 D8R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0
Bit1~0 D15~D8:STMnCCRAHighByteRegisterbit7~bit0STMn16-bitCCRAbit15~bit8
STMnRP Register – n=1Bit 7 6 5 4 3 2 1 0
Name D D6 D5 D4 D3 D D1 D0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0
Bit7~0 D7~D0:STMnCCRPRegisterbit7~bit0STMnCCRP8-bitregister,comparedwiththeSTMnCounterbit15~bit8.ComparatorPMatchPeriod:0:65536STMnclocks1~255:256×(1~255)STMnclocks
TheseeightbitsareusedtosetupthevalueontheinternalCCRP8-bitregister,whichare thencomparedwith the internalcounter’shighesteightbits.Theresultof thiscomparisoncanbeselectedtocleartheinternalcounteriftheSTnCCLRbitissettozero.SettingtheSTnCCLRbittozeroensuresthatacomparematchwiththeCCRPvalueswillreset theinternalcounter.AstheCCRPbitsareonlycomparedwiththehighesteightcounterbits, thecomparevaluesexist in256clockcyclemultiples.Clearingalleightbits tozero is ineffectallowing thecounter tooverflowat itsmaximumvalue.
Rev. 1.00 66 st 1 01 Rev. 1.00 6 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Standard Type TM Operating ModesTheStandardTypeTMcanoperateinoneoffiveoperatingmodes,CompareMatchOutputMode,PWMOutputMode,SinglePulseOutputMode,CaptureInputModeorTimer/CounterMode.TheoperatingmodeisselectedusingtheSTnM1andSTnM0bitsintheSTMnC1register.
Compare Match Output ModeTo select thismode, bitsSTnM1andSTnM0 in theSTMnC1 register, shouldbe set to00respectively. In thismodeonce thecounter isenabledand running itcanbeclearedby threemethods.Theseareacounteroverflow,acomparematchfromComparatorAandacomparematchfromComparatorP.WhentheSTnCCLRbitislow,therearetwowaysinwhichthecountercanbecleared.OneiswhenacomparematchfromComparatorP,theotheriswhentheCCRPbitsareallzerowhichallowsthecountertooverflow.HerebothSTMnAFandSTMnPFinterruptrequestflagsforComparatorAandComparatorPrespectively,willbothbegenerated.
IftheSTnCCLRbitintheSTMnC1registerishighthenthecounterwillbeclearedwhenacomparematchoccursfromComparatorA.However,hereonly theSTMnAFinterrupt request flagwillbegeneratedevenifthevalueoftheCCRPbitsislessthanthatoftheCCRAregisters.ThereforewhenSTnCCLRishighnoSTMnPF interrupt request flagwillbegenerated. In theCompareMatchOutputMode,theCCRAcannotbesetto"0".IftheCCRAbitsareallzero,thecounterwilloverflowwhenitsreachesitsmaximum10-bit,3FFHex,valueor16-bit,FFFFHex,value,howeverheretheSTMnAFinterruptrequestflagwillnotbegenerated.
Asthenameofthemodesuggests,afteracomparisonismade,theSTMoutputpin,willchangestate.TheSTMoutputpinconditionhoweveronlychangesstatewhenanSTMnAFinterruptrequestflagisgeneratedafteracomparematchoccursfromComparatorA.TheSTMnPFinterruptrequestflag,generatedfromacomparematchoccursfromComparatorP,willhavenoeffectontheSTMoutputpin.ThewayinwhichtheSTMoutputpinchangesstatearedeterminedbytheconditionoftheSTnIO1andSTnIO0bitsintheSTMnC1register.TheSTMoutputpincanbeselectedusingtheSTnIO1andSTnIO0bitstogohigh,togolowortotogglefromitspresentconditionwhenacomparematchoccursfromComparatorA.TheinitialconditionoftheSTMoutputpin,whichissetupaftertheSTnONbitchangesfromlowtohigh,issetupusingtheSTnOCbit.NotethatiftheSTnIO1andSTnIO0bitsarezerothennopinchangewilltakeplace.
Rev. 1.00 66 st 1 01 Rev. 1.00 6 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Conter Vale
0x3FF/0xFFFF
CCRP
CCR
STnON
STnPU
STnPOL
CCRP Int. fla STMnPF
CCR Int. fla STMnF
STMnO/P Pin
Time
CCRP=0
CCRP > 0
Conter overflowCCRP > 0
Conter cleared by CCRP vale
Pase
Resme
Stop
Conter Restart
STnCCLR = 0; STnM [1:0] = 00
Otpt pin set to initial Level Low if STnOC=0
Otpt Tole with STMnF fla
Note STnIO [1:0] = 10 ctive Hih Otpt selectHere STnIO [1:0] = 11
Tole Otpt select
Otpt not affected by STMnF fla. Remains Hih ntil reset by STnON bit
Otpt PinReset to Initial vale
Otpt controlled by other pin-shared fnction
Otpt Invertswhen STnPOL is hih
Compare Match Output Mode – STnCCLR=0 (n=0~1)Note:1.WithSTnCCLR=0aComparatorPmatchwillclearthecounter
2.TheTMoutputpincontrolledonlybytheSTMnAFflag3.TheoutputpinresettoinitialstatebyaSTnONbitrisingedge
Rev. 1.00 68 st 1 01 Rev. 1.00 69 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Conter Vale
0x3FF/0xFFFF
CCRP
CCR
STnON
STnPU
STnPOL
CCRP Int. fla STMnPF
CCR Int. fla STMnF
STMn O/P Pin
Time
CCR=0
CCR = 0Conter overflowCCR > 0 Conter cleared by CCR vale
Pase
Resme
Stop Conter Restart
STnCCLR = 1; STnM [1:0] = 00
Otpt pin set to initial Level Low if STnOC=0
Otpt Tole with STMnF fla
Note STnIO [1:0] = 10 ctive Hih Otpt selectHere STnIO [1:0] = 11
Tole Otpt select
Otpt not affected by STMnF fla. Remains Hih ntil reset by STnON bit Otpt Pin
Reset to Initial valeOtpt controlled by other pin-shared fnction
Otpt Invertswhen STnPOL is hih
STMnPF not enerated
No STMnF fla enerated on CCR overflow
Otpt does not chane
Compare Match Output Mode – STnCCLR=1 (n=0~1)Note:1.WithSTnCCLR=1aComparatorAmatchwillclearthecounter
2.TheTMoutputpincontrolledonlybytheSTMnAFflag3.TheoutputpinresettoinitialstatebyaSTnONrisingedge4.TheSTMnPFflagisnotgeneratedwhenSTnCCLR=1
Timer/Counter ModeTo select thismode, bitsSTnM1andSTnM0 in theSTMnC1 register shouldbe set to 11respectively.TheTimer/CounterModeoperatesinanidenticalwaytotheCompareMatchOutputModegenerating thesameinterruptflags.Theexception is that in theTimer/CounterModetheSTMoutputpinisnotused.ThereforetheabovedescriptionandTimingDiagramsfortheCompareMatchOutputModecanbeusedtounderstanditsfunction.AstheSTMoutputpinisnotusedinthismode,thepincanbeusedasanormalI/Opinorotherpin-sharedfunctionbysettingpin-sharefunctionregister.
PWM Output ModeTo select thismode, bitsSTnM1andSTnM0 in theSTMnC1 register shouldbe set to 10respectivelyandalso theSTnIO1andSTnIO0bitsshouldbeset to10respectively.ThePWMgenerationfunctionwithin theSTMnisuseful forapplicationswhichrequirefunctionssuchasmotorcontrol,heatingcontrol,illuminationcontroletc.ByprovidingasignaloffixedfrequencybutofvaryingdutycycleontheSTMoutputpin,asquarewaveACwaveformcanbegeneratedwithvaryingequivalentDCRMSvalues.
Rev. 1.00 68 st 1 01 Rev. 1.00 69 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
AsboththeperiodanddutycycleofthePWMwaveformcanbecontrolled,thechoiceofgeneratedwaveformisextremelyflexible.InthePWMoutputmode,theSTnCCLRbithasnoeffectasthePWMperiod.BothoftheCCRAandCCRPregistersareusedtogeneratethePWMwaveform,oneregisterisusedtocleartheinternalcounterandthuscontrolthePWMwaveformfrequency,whiletheotheroneisusedtocontrol thedutycycle.Whichregister isusedtocontroleitherfrequencyordutycycleisdeterminedusingtheSTnDPXbit intheSTMnC1register.ThePWMwaveformfrequencyanddutycyclecanthereforebecontrolledbythevaluesintheCCRAandCCRPregisters.
Aninterruptflag,oneforeachoftheCCRAandCCRP,willbegeneratedwhenacomparematchoccursfromeitherComparatorAorComparatorP.TheSTnOCbitintheSTMnC1registerisusedtoselecttherequiredpolarityofthePWMwaveformwhilethetwoSTnIO1andSTnIO0bitsareusedtoenablethePWMoutputortoforcetheSTMoutputpintoafixedhighorlowlevel.TheSTnPOLbitisusedtoreversethepolarityofthePWMoutputwaveform.
• 10-bit STMn, PWM Output Mode, Edge-aligned Mode, STnDPX=0
CCRP 001b 010b 011b 100b 101b 110b 111b 000bPeriod 18 56 384 51 640 68 896 104Dty CCR
IffSYS=4MHz,TMclocksourceisfSYS/4,CCRP=100bandCCRA=128,
TheSTMPWMoutputfrequency=(fSYS/4)/512=fSYS/2048=2kHz,duty=128/512=25%.
IftheDutyvaluedefinedbytheCCRAregisterisequaltoorgreaterthanthePeriodvalue,thenthePWMoutputdutyis100%.
• 10-bit STMn, PWM Output Mode, Edge-aligned Mode, STnDPX=1
CCRP 001b 010b 011b 100b 101b 110b 111b 000bPeriod CCR
Dty 18 56 384 51 640 68 896 104
ThePWMoutputperiodisdeterminedbytheCCRAregistervaluetogetherwiththeSTMclockwhilethePWMdutycycleisdefinedbytheCCRPregistervalue.
• 16-bit STMn, PWM Output Mode, Edge-aligned Mode, STnDPX=0
CCRP 1~255 00HPeriod CCRP×56 65536Dty CCR
IffSYS=4MHz,TMclocksourceisfSYS/4,CCRP=2andCCRA=128,
TheSTMPWMoutputfrequency=(fSYS/4)/(2×256)=fSYS/2048=2kHz,duty=128/512=25%.
IftheDutyvaluedefinedbytheCCRAregisterisequaltoorgreaterthanthePeriodvalue,thenthePWMoutputdutyis100%.
• 16-bit STMn, PWM Output Mode, Edge-aligned Mode, STnDPX=1
CCRP 1~255 00HPeriod CCRDty CCRP×56 65536
ThePWMoutputperiodisdeterminedbytheCCRAregistervaluetogetherwiththeSTMclockwhilethePWMdutycycleisdefinedbytheCCRPregistervalue.
Rev. 1.00 0 st 1 01 Rev. 1.00 1 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Conter Vale
CCRP
CCR
STnON
STnPU
STnPOL
CCRP Int. fla STMnPF
CCR Int. fla STMnF
STM O/P Pin(STnOC=1)
Time
Conter cleared by CCRP
Pase Resme Conter Stop if STnON bit low
Conter Reset when STnON retrns hih
STnDPX = 0; STnM [1:0] = 10
PWM Dty Cycle set by CCR
PWM resmes operation
Otpt controlled by other pin-shared fnction Otpt Inverts
when STnPOL = 1PWM Period set by CCRP
STM O/P Pin(STnOC=0)
PWM Output Mode – STnDPX = 0 (n=0~1)Note:1.HereSTnDPX=0–CounterclearedbyCCRP
2.AcounterclearsetsPWMPeriod3.TheinternalPWMfunctioncontinuesrunningevenwhenSTnIO[1:0]=00or014.TheSTnCCLRbithasnoinfluenceonPWMoperation
Rev. 1.00 0 st 1 01 Rev. 1.00 1 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Conter Vale
CCRP
CCR
STnON
STnPU
STnPOL
CCRP Int. fla STMnPF
CCR Int. fla STMnF
STMn O/P Pin (STnOC=1)
Time
Conter cleared by CCR
Pase Resme Conter Stop if STnON bit low
STnDPX = 1; STnM [1:0] = 10
PWM Dty Cycle set by CCRP
PWM resmes operation
Otpt controlled by other pin-shared fnction Otpt Inverts
when STnPOL = 1PWM Period set by CCR
STMn O/P Pin (STnOC=0)
Conter Reset when STnON retrns hih
PWM Output Mode – STnDPX = 1Note:1.HereSTnDPX=1–CounterclearedbyCCRA
2.AcounterclearsetsPWMPeriod3.TheinternalPWMfunctioncontinuesevenwhenSTnIO[1:0]=00or014.TheSTnCCLRbithasnoinfluenceonPWMoperation
Rev. 1.00 st 1 01 Rev. 1.00 3 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Single Pulse ModeTo select thismode, bitsSTnM1andSTnM0 in theSTMnC1 register shouldbe set to 10respectivelyandalsotheSTnIO1andSTnIO0bitsshouldbesetto11respectively.TheSinglePulseOutputMode,asthenamesuggests,willgenerateasingleshotpulseontheSTMoutputpin.
ThetriggerforthepulseoutputleadingedgeisalowtohightransitionoftheSTnONbit,whichcanbeimplementedusingtheapplicationprogram.HoweverintheSinglePulseMode,theSTnONbitcanalsobemade toautomaticallychangefromlowtohighusing theexternalSTCKnpin,whichwillinturninitiatetheSinglePulseoutput.WhentheSTnONbittransitionstoahighlevel,thecounterwillstartrunningandthepulseleadingedgewillbegenerated.TheSTnONbitshouldremainhighwhenthepulseisinitsactivestate.ThegeneratedpulsetrailingedgewillbegeneratedwhentheSTnONbitisclearedtozero,whichcanbeimplementedusingtheapplicationprogramorwhenacomparematchoccursfromComparatorA.
HoweveracomparematchfromComparatorAwillalsoautomaticallycleartheSTnONbitandthusgeneratetheSinglePulseoutputtrailingedge.InthiswaytheCCRAvaluecanbeusedtocontrolthepulsewidth.AcomparematchfromComparatorAwillalsogenerateaSTMinterrupt.ThecountercanonlyberesetbacktozerowhentheSTnONbitchangesfromlowtohighwhenthecounterrestarts.IntheSinglePulseModeCCRPisnotused.TheSTnCCLRandSTnDPXbitsarenotusedinthisMode.
STnON bit0 1
S/W Command SET“STnON”
orSTCKn Pin
Transition
STnON bit1 0
CCR Trailin Ede
S/W Command CLR“STnON”
orCCR Compare Match
STPn Otpt Pin
Plse Width = CCR Vale
CCR Leadin Ede
Single Pulse Generation
Rev. 1.00 st 1 01 Rev. 1.00 3 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Conter Vale
CCRP
CCR
STnON
STnPU
STnPOL
CCRP Int. Fla STMnPF
CCR Int. Fla STMnF
STMn O/P Pin(STnOC=1)
Time
Conter stopped by CCR
PaseResme Conter Stops
by software
Conter Reset when STnON retrns hih
STnM [1:0] = 10 ; STnIO [1:0] = 11
Plse Width set by CCR
Otpt Invertswhen STnPOL = 1
No CCRP Interrpts enerated
STMn O/P Pin(STnOC=0)
STCKn pin
Software Trier
Cleared by CCR match
STCKn pin Trier
to. set by STCKn pin
Software Trier
Software Clear
Software TrierSoftware
Trier
Single Pulse Mode (n=0~1)Note:1.CounterstoppedbyCCRAmatch
2.CCRPisnotused3.ThepulseistriggeredbysettingtheSTnONbithigh4.IntheSinglePulseMode,STnIO[1:0]mustbesetto"11"andcannotbechanged.
Rev. 1.00 4 st 1 01 Rev. 1.00 5 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Capture Input ModeToselectthismodebitsSTnM1andSTnM0intheSTMnC1registershouldbesetto01respectively.Thismodeenablesexternalsignals tocaptureandstore thepresentvalueof theinternalcounterandcanthereforebeusedforapplicationssuchaspulsewidthmeasurements.TheexternalsignalissuppliedontheSTPnI,whoseactiveedgecanbeeitherarisingedge,afallingedgeorbothrisingandfallingedges;theactiveedgetransitiontypeisselectedusingtheSTnIO1andSTnIO0bitsintheSTMnC1register.ThecounterisstartedwhentheSTnONbitchangesfromlowtohighwhichisinitiatedusingtheapplicationprogram.
WhentherequirededgetransitionappearsontheSTPnIthepresentvalueinthecounterwillbelatchedintotheCCRAregistersandaSTMinterruptgenerated.IrrespectiveofwhateventsoccurontheSTPnIthecounterwillcontinuetofreerununtiltheSTnONbitchangesfromhightolow.WhenaCCRPcomparematchoccurs thecounterwill resetbacktozero; in thiswaytheCCRPvaluecanbeused tocontrol themaximumcountervalue.WhenaCCRPcomparematchoccursfromComparatorP,aSTMinterruptwillalsobegenerated.CountingthenumberofoverflowinterruptsignalsfromtheCCRPcanbeausefulmethodinmeasuringlongpulsewidths.TheSTnIO1andSTnIO0bitscanselecttheactivetriggeredgeontheSTPnItobearisingedge,fallingedgeorbothedgetypes.If theSTnIO1andSTnIO0bitsarebothsethigh,thennocaptureoperationwill takeplaceirrespectiveofwhathappensontheSTPnI,howeveritmustbenotedthat thecounterwillcontinuetorun.
TheSTnCCLRandSTnDPXbitsarenotusedinthisMode.
Rev. 1.00 4 st 1 01 Rev. 1.00 5 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Conter Vale
YY
CCRP
STnON
STnPU
CCRP Int. Fla STMnPF
CCR Int. Fla STMnF
CCR Vale
Time
Conter cleared by CCRP
PaseResme
Conter Reset
STnM [1:0] = 01
STMn captre pin STPnI
XX
Conter Stop
STnIO [1:0] Vale
XX YY XX YY
ctiveede ctive
edective ede
00 – Risin ede 01 – Fallin ede 10 – Both edes 11 – Disable Captre
Capture Input Mode (n=0~1)Note:1.STnM[1:0]=01andactiveedgesetbytheSTnIO[1:0]bits
2.ATMCaptureinputpinactiveedgetransfersthecountervaluetoCCRA3.TheSTnCCLRandSTnDPXbitsarenotused4.Nooutputfunction–STnOCandSTnPOLbitsarenotused5.CCRPdeterminesthecountervalueandthecounterhasamaximumcountvaluewhenCCRPisequaltozero.
Rev. 1.00 6 st 1 01 Rev. 1.00 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Analog to Digital Converter Theneedtointerfacetorealworldanalogsignals isacommonrequirementformanyelectronicsystems.However, toproperlyprocess these signalsbyamicrocontroller, theymust firstbeconverted intodigitalsignalsbyA/Dconverters.By integrating theA/Dconversionelectroniccircuitryintothemicrocontroller,theneedforexternalcomponentsisreducedsignificantlywiththecorrespondingfollow-onbenefitsoflowercostsandreducedcomponentspacerequirements.
A/D Converter OverviewThedevicecontainsamulti-channelanalog todigitalconverterwhichcandirectly interface toexternalanalogsignals,suchasthatfromsensorsorothercontrolsignalsandconvertthesesignalsdirectlyintoa12-bitdigitalvalue.Italsocanconverttheinternalsignalintoa12-bitdigitalvalue.TheexternalorinternalanalogsignaltobeconvertedisdeterminedbytheSAINS2~SAINS0bitstogetherwith theSACS3~SACS0bits.Moredetailed informationabout theA/Dinputsignal isdescribedin the"A/DConverterControlRegisters"and"A/DConverterInputSignals"sectionsrespectively.
External Input Channels Internal Signals Channel Select Bits
8: N0~N VBGSINS~SINS0SCS3~SCS0
TheaccompanyingblockdiagramshowstheoverallinternalstructureoftheA/Dconverter,togetherwithitsassociatedregisters.
Pin-sharedSelection
SCS3~SCS0
SINS~SINS0
/D Converter
STRT DBZ DCEN
VSS
÷ N
(N=0~)
fSYS
SCKS~SCKS0
VDD
VDD
SVRS1~SVRS0
DCEN
/D Reference Voltae
/D DataReisters
DRFS
VBG
GND
SDOLSDOH
/D Clock
VREF
Pin-shared Selection
N0N1
N
A/D Converter Structure
Rev. 1.00 6 st 1 01 Rev. 1.00 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
A/D Converter Register DescriptionOveralloperationoftheA/Dconverteriscontrolledusingseveralregisters.AreadonlyregisterpairexiststostoretheA/Dconverterdata12-bitvalue.TheremainingtworegistersarecontrolregisterswhichsetuptheoperatingandcontrolfunctionoftheA/Dconverter.
Register Name
Bit7 6 5 4 3 2 1 0
SDOH (DRFS=0) D11 D10 D9 D8 D D6 D5 D4
SDOL (DRFS=0) D3 D D1 D0 — — — —
SDOH (DRFS=1) — — — — D11 D10 D9 D8
SDOL (DRFS=1) D D6 D5 D4 D3 D D1 D0
SDC0 STRT DBZ DCEN DRFS SCS3 SCS SCS1 SCS0SDC1 SINS SINS1 SINS0 SVRS1 SVRS0 SCKS SCKS1 SCKS0
A/D Converter Register List
A/D Converter Data Registers – SADOL, SADOHAsthedevicecontainsaninternal12-bitA/Dconverter, itrequirestwodataregisterstostoretheconvertedvalue.Theseareahighbyteregister,knownasSADOH,andalowbyteregister,knownasSADOL.After theconversionprocess takesplace, theseregisterscanbedirectlyreadbythemicrocontrollertoobtainthedigitisedconversionvalue.Asonly12bitsofthe16-bitregisterspaceisutilised, theformat inwhichthedata isstorediscontrolledbytheADRFSbit in theSADC0registerasshownintheaccompanyingtable.D0~D11aretheA/Dconversionresultdatabits.Anyunusedbitswillbereadaszero.NotethatA/DConverterdataregistercontentswillbeunchangediftheA/Dconverterisdisabled.
ADRFSSADOH SADOL
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 00 D11 D10 D9 D8 D D6 D5 D4 D3 D D1 D0 0 0 0 01 0 0 0 0 D11 D10 D9 D8 D D6 D5 D4 D3 D D1 D0
A/D Data Register Pair
A/D Converter Control Registers – SADC0, SADC1TocontrolthefunctionandoperationoftheA/Dconverter,twocontrolregistersknownasSADC0andSADC1areprovided.These8-bit registersdefinefunctionssuchas theselectionofwhichanalogchannelisconnectedtotheinternalA/Dconverter,thedigitiseddataformat,theA/DclocksourceaswellascontrollingthestartfunctionandmonitoringtheA/Dconverterbusystatus.Asthedevicecontainsonlyoneactualanalogtodigitalconverterhardwarecircuit,eachof theexternalor internalanalogsignal inputsmustberoutedto theconverter.TheSACS3~SACS0bits in theSADC0registerareusedtodeterminewhichexternalchannel input isselectedtobeconverted.TheSAINS2~SAINS0bitsintheSADC1registerareusedtodeterminethattheanalogsignaltobeconvertedcomesfromtheinternalanalogsignalorexternalanalogchannelinput.
Therelevantpin-sharedfunctionselectionbitsdeterminewhichpinsonI/OPortsareusedasanaloginputsfortheA/Dconverterinputandwhichpinsarenot tobeusedastheA/Dconverterinput.WhenthepinisselectedtobeanA/Dinput,itsoriginalfunctionwhetheritisanI/Oorotherpin-sharedfunctionwillberemoved.Inaddition,anyinternalpull-highresistorconnectedtothepinwillbeautomaticallyremovedifthepinisselectedtobeanA/Dconverterinput.
Rev. 1.00 8 st 1 01 Rev. 1.00 9 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
• SADC0 Register
Bit 7 6 5 4 3 2 1 0Name STRT DBZ DCEN DRFS SCS3 SCS SCS1 SCS0R/W R/W R R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0
Bit7 START:StarttheA/Dconversion0→1→0:StartA/Dconversion
ThisbitisusedtoinitiateanA/Dconversionprocess.Thebitisnormallylowbutifsethighandthenclearedlowagain,theA/Dconverterwillinitiateaconversionprocess.
Bit6 ADBZ:A/Dconverterbusyflag0:NoA/Dconversionisinprogress1:A/Dconversionisinprogress
ThisreadonlyflagisusedtoindicatewhethertheA/Dconversionis inprogressornot.WhentheSTARTbitissetfromlowtohighandthentolowagain,theADBZflagwillbesetto1toindicatethattheA/Dconversionisinitiated.TheADBZflagwillbeclearedto0aftertheA/Dconversioniscomplete.
Bit5 ADCEN:A/Dconverterfunctionenablecontrol0:Disable1:Enable
Thisbitcontrols theA/Dinternal function.Thisbitshouldbeset toone toenabletheA/Dconverter.If thebit isset low,thentheA/Dconverterwillbeswitchedoffreducingthedevicepowerconsumption.WhentheA/Dconverterfunctionisdisabled,thecontentsof theA/Ddata registerpairknownasSADOHandSADOLwillbeunchanged.
Bit4 ADRFS:A/Dconverterdataformatselect0:A/Dconverterdataformat→SADOH=D[11:4];SADOL=D[3:0]1:A/Dconverterdataformat→SADOH=D[11:8];SADOL=D[7:0]
Thisbitcontrols theformatof the12-bitconvertedA/Dvaluein thetwoA/Ddataregisters.DetailsareprovidedintheA/Ddataregistersection.
Bit3~0 SACS3~SACS0:A/Dconverterexternalanalogchannelinputselect0000:AN00001:AN10010:AN20011:AN30100:AN40101:AN50110:AN60111:AN71000~1111:Un-existedchannel,theexternalinputisfloating
Rev. 1.00 8 st 1 01 Rev. 1.00 9 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
• SADC1 Register
Bit 7 6 5 4 3 2 1 0Name SINS SINS1 SINS0 SVRS1 SVRS0 SCKS SCKS1 SCKS0R/W R/W R/W R/W R/W R/W R/W R/W R/WPOR 0 0 0 0 0 0 0 0
Bit7~5 SAINS2~SAINS0:A/Dconverterinputsignalselect000:Externalinput–Externalanalogchannelinput001:Internalinput–Internalbandgapreferencevoltage,VBG
010:Internalinput–Unused,connectedtoground011:Internalinput–Unused,connectedtoground100:Internalinput–Unused,connectedtoground101~111:Externalinput–Externalanalogchannelinput
CaremustbetakeniftheSAINS2~SAINS0bitsaresetfrom"001"to"100"toselecttheinternalanalogsignaltobeconverted.Whentheinternalanalogsignalisselectedtobeconverted,theexternalinputpinmustneverbeselectedastheA/DinputsignalbyproperlysettingtheSACS3~SACS0bits.Otherwise,theexternalchannelinputwillbeconnectedtogetherwiththeinternalanalogsignal.Thiswillresultinunpredictablesituationssuchasanirreversibledamage.
Bit4~3 SAVRS1~SAVRS0:A/Dconverterreferencevoltageselect00:FromexternalVREFpin01:InternalA/Dconverterpower,AVDD
1x:FromexternalVREFpinThesebitsareusedtoselecttheA/Dconverterreferencevoltage.CaremustbetakeniftheSAVRS1~SAVRS0bitsaresetto"01"toselecttheinternalA/Dconverterpoweras thereferencevoltagesource.WhentheinternalA/Dconverterpowerisselectedasthereferencevoltage,theVREFpincannotbeconfiguredasthereferencevoltageinputbyproperlyconfiguring thecorrespondingpin-sharedfunctioncontrolbits.Otherwise,theexternalinputvoltageonVREFpinwillbeconnectedtotheinternalA/Dconverterpower.
Bit2~0 SACKS2~SACKS0:A/Dconversionclocksourceselect000:fSYS
001:fSYS/2010:fSYS/4011:fSYS/8100:fSYS/16101:fSYS/32110:fSYS/64111:fSYS/128
ThesethreebitsareusedtoselecttheclocksourcefortheA/Dconverter.
A/D Converter OperationTheSTARTbitintheSADC0registerisusedtostarttheADconversion.Whenthemicrocontrollersetsthisbitfromlowtohighandthenlowagain,ananalogtodigitalconversioncyclewillbeinitiated.
TheADBZbit intheSADC0registerisusedtoindicatewhethertheanalogtodigitalconversionprocessisinprogressornot.Thisbitwillbeautomaticallysetto1bythemicrocontrollerafteranA/Dconversionissuccessfullyinitiated.WhentheA/Dconversioniscomplete,theADBZwillbeclearedto0.Inaddition, thecorrespondingA/Dinterruptrequestflagwillbeset in theinterruptcontrolregister,andif the interruptsareenabled,anappropriate internal interruptsignalwillbegenerated.ThisA/Dinternal interruptsignalwilldirect theprogramflowto theassociatedA/Dinternalinterruptaddressforprocessing.IftheA/Dinternalinterruptisdisabled,themicrocontrollercanpolltheADBZbitintheSADC0registertocheckwhetherithasbeenclearedasanalternativemethodofdetectingtheendofanA/Dconversioncycle.
Rev. 1.00 80 st 1 01 Rev. 1.00 81 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
TheclocksourcefortheA/Dconverter,whichoriginatesfromthesystemclockfSYS,canbechosentobeeither fSYSorasubdividedversionof fSYS.Thedivisionratiovalue isdeterminedby theSACKS2~SACKS0bits intheSADC1register.AlthoughtheA/DclocksourceisdeterminedbythesystemclockfSYSandbybitsSACKS2~SACKS0,therearesomelimitationsonthemaximumA/Dclocksourcespeedthatcanbeselected.AstherecommendedrangeofpermissibleA/Dclockperiod,tADCK,isfrom0.5μsto10μs,caremustbetakenforsystemclockfrequencies.Forexample,asthesystemclockoperatesatafrequencyof4MHz,theSACKS2~SACKS0bitsshouldnotbesetto000,110or111.DoingsowillgiveA/DclockperiodsthatarelessthantheminimumorlargerthanthemaximumA/DclockperiodwhichmayresultininaccurateA/Dconversionvalues.Refertothefollowingtableforexamples,wherevaluesmarkedwithanasterisk*showwhere,dependinguponthedevice,specialcaremustbetaken,asthevaluesmaybelessorlargerthanthespecifiedA/DClockPeriodrange.
fSYS
A/D Clock Period (tADCK)SACKS
[2:0]=000(fSYS)
SACKS[2:0]=001
(fSYS/2)
SACKS[2:0]=010
(fSYS/4)
SACKS[2:0]=011
(fSYS/8)
SACKS[2:0]=100(fSYS/16)
SACKS[2:0]=101(fSYS/32)
SACKS[2:0]=110(fSYS/64)
SACKS[2:0]=111(fSYS/128)
1MHz 1μs 2μs 4μs 8μs 16μs * 32μs * 64μs * 128μs *MHz 500ns 1μs 2μs 4μs 8μs 16μs * 32μs * 64μs *4MHz 50ns * 500ns 1μs 2μs 4μs 8μs 16μs * 32μs *
A/D Clock Period Examples
Controlling thepoweron/off functionof theA/Dconvertercircuitry is implementedusing theADCENbitintheSADC0register.ThisbitmustbesethightopowerontheA/Dconverter.WhentheADCENbit issethigh topoweron theA/Dconverter internalcircuitryacertaindelay,asindicatedin the timingdiagram,mustbeallowedbeforeanA/Dconversionis initiated.EvenifnopinsareselectedforuseasA/Dinputs,iftheADCENbitishigh,thensomepowerwillstillbeconsumed.InpowerconsciousapplicationsitisthereforerecommendedthattheADCENissetlowtoreducepowerconsumptionwhentheA/Dconverterfunctionisnotbeingused.
A/D Converter Reference VoltageThereferencevoltagesupplytotheA/DconvertercanbesuppliedfromthepowersupplyAVDD,orfromanexternalreferencesourcesuppliedonpinVREF.ThedesiredselectionismadeusingtheSAVRS1andSAVRS0bits.WhentheSAVRSbitfieldissetto"01",theA/DconverterreferencevoltagewillcomefromtheAVDD.Otherwise,iftheSAVRSbitfieldissettoanyothervalueexcept"01",theA/DconverterreferencevoltagewillcomefromtheVREFpin.AstheVREFpinispin-sharedwithotherfunctions,whentheVREFpinisselectedasthereferencevoltagesupplypin,theVREFpincontrolbitVREFSshouldfirstbesethightoenabletheVREFpinfunctionthentheotherpinfunctionswillbedisabledautomatically.However, if theinternalA/DconverterpowerAVDDisselectedasthereferencevoltage,theVREFpinmustnotbeconfiguredasthereferencevoltageinputfunctiontoavoidtheinternalconnectionbetweentheVREFpintoA/DconverterpowerAVDD.Theanaloginputvaluesmustnotbeallowedtoexceedthevalueof theselectedA/Dreferencevoltage.
Rev. 1.00 80 st 1 01 Rev. 1.00 81 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
A/D Converter Input SignalsAll theexternalA/Danalogchannel inputpinsarepin-sharedwiththeI/Opinsaswellasotherfunctions.ThecorrespondingcontrolbitsforeachA/Dexternal inputpinin thePxS0andPxS1registersdeterminewhether the inputpinsaresetupasA/Dconverteranalog inputchannelorwhether theyhaveotherfunctions.If thepin issetuptobeasanA/Danalogchannel input, theoriginalpinfunctionswillbedisabled.Inthisway,pinscanbechangedunderprogramcontroltochangetheirfunctionbetweenA/Dinputsandotherfunctions.Allpullhighresistors,whicharesetupthroughregisterprogramming,willbeautomaticallydisconnectedifthepinsaresetupasA/Dinputs.NotethatitisnotnecessarytofirstsetuptheA/DpinasaninputintheportcontrolregistertoenabletheA/Dinputaswhenthepin-sharedfunctioncontrolbitsenableanA/Dinput,thestatusoftheportcontrolregisterwillbeoverridden.TheinternalbandgapvoltagecanbeconnectedtotheA/DconverterastheanaloginputsignalbyconfiguringtheSAINS2~SAINS0bits. If theexternalchannel input isselected tobeconverted,theSAINS2~SAINS0bits shouldbe set to "000"or "101~111"and theSACS3~SACS0bitscandeterminewhichexternalchannel isselected. If the internalanalogsignal isselected tobeconverted,theSACS3~SACS0bitsmustbeconfiguredwithanappropriatevaluetoswitchofftheexternalanalogchannelinput.Otherwise,theinternalanalogsignalwillbeconnectedtogetherwiththeexternalchannelinput.Thiswillresultinunpredictablesituations.
SAINS[2:0] SACS[3:0] Input Signals Description
000 101~1110000~0111 N0~N External pin analo inpt
1000~1111 — Un-existed channel, input is floating.
001 1000~1111 VBG Internal Bandap reference voltae
010~100 1000~1111 GND Unsed connected to rond
A/D Converter Input Signal Selection
Conversion Rate and Timing DiagramAcompleteA/Dconversioncontains twoparts,data samplinganddataconversion.ThedatasamplingwhichisdefinedastADStakes4A/Dclockcyclesandthedataconversiontakes12A/Dclockcycles.Thereforeatotalof16A/DclockcyclesforanexternalinputA/DconversionwhichisdefinedastADCarenecessary.
MaximumsingleA/Dconversionrate=A/Dclockperiod÷16Theaccompanyingdiagramshowsgraphicallythevariousstagesinvolvedinananalogtodigitalconversionprocessanditsassociatedtiming.AfteranA/Dconversionprocesshasbeeninitiatedby theapplicationprogram, themicrocontroller internalhardwarewillbegin tocarryout theconversion,duringwhichtimetheprogramcancontinuewithotherfunctions.ThetimetakenfortheA/Dconversionis16tADCKclockcycleswheretADCKisequaltotheA/Dclockperiod.
DCEN
STRT
DBZ
SCS[3:0](SINS[:0]=000)
off on off on
tONST
tDS
/D samplin timetDS
/D samplin time
Start of /D conversion Start of /D conversion Start of /D conversion
End of /D conversion
End of /D conversion
tDC
/D conversion timetDC
/D conversion timetDC
/D conversion time
0011B 0010B 0000B 0001B
/D channel switch
A/D Conversion Timing
Rev. 1.00 8 st 1 01 Rev. 1.00 83 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Summary of A/D Conversion Steps ThefollowingsummarisestheindividualstepsthatshouldbeexecutedinordertoimplementanA/Dconversionprocess.
• Step1SelecttherequiredA/DconversionclockbycorrectlyprogrammingbitsSACKS2~SACKS0intheSADC1register.
• Step2EnabletheA/DbysettingtheADCENbitintheSADC0registerto1.
• Step3SelectwhichsignalistobeconnectedtotheinternalA/DconverterbycorrectlyconfiguringtheSAINS2~SAINS0bitsSelecttheexternalchannelinputtobeconverted,gotoStep4.Selecttheinternalanalogsignaltobeconverted,gotoStep5.
• Step4IftheA/DinputsignalcomesfromtheexternalchannelinputselectedbyconfiguringtheSAINSbitfield,thecorrespondingpinsshouldbeconfiguredasA/Dinputfunctionbyconfiguringtherelevantpin-sharedfunctioncontrolbits.ThedesiredanalogchannelthenshouldbeselectedbyconfiguringtheSACSbitfield.Afterthisstep,gotoStep6.
• Step5BeforetheA/DinputsignalisselectedtocomefromtheinternalanalogsignalbyconfiguringtheSAINSbitfield,thecorrespondingexternalinputpinmustbeswitchedtoanon-existedchannelinputbyproperlyconfiguredtheSACS3~SACS0bits.ThedesiredinternalanalogsignalthencanbeselectedbyconfiguringtheSAINSbitfield.Afterthisstep,gotoStep6.
• Step6Select thereferencevoltagesourcebyconfiguring theSAVRS1~SAVRS0bits in theSADC1register.
• Step7SelectA/DconverteroutputdataformatbysettingtheADRFSbitintheSADC0register.
• Step8IfA/Dconversioninterruptisused,theinterruptcontrolregistersmustbecorrectlyconfiguredtoensuretheA/Dinterruptfunctionisactive.Themasterinterruptcontrolbit,EMI,andtheA/Dconversioninterruptcontrolbit,ADE,mustbothbesethighinadvance.
• Step9TheA/DconversionprocedurecannowbeinitializedbysettingtheSTARTbitfromlowtohighandthenlowagain.
• Step10IfA/Dconversion is inprogress, theADBZflagwillbesethigh.After theA/Dconversionprocess iscomplete, theADBZflagwillgo lowand then theoutputdatacanbe readfromSADOHandSADOLregisters.
Note:Whencheckingfortheendoftheconversionprocess,ifthemethodofpollingtheADBZbitintheSADC0registerisused,theinterruptenablestepabovecanbeomitted.
Rev. 1.00 8 st 1 01 Rev. 1.00 83 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Programming ConsiderationsDuringmicrocontrolleroperationswhere theA/Dconverter isnotbeingused, theA/Dinternalcircuitrycanbeswitchedoff toreducepowerconsumption,byclearingbitADCENto0 in theSADC0register.Whenthishappens, theinternalA/Dconvertercircuitswillnotconsumepowerirrespectiveofwhatanalogvoltageisappliedtotheirinputlines.IftheA/DconverterinputlinesareusedasnormalI/Opins,thencaremustbetakenasiftheinputvoltageisnotatavalidlogiclevel,thenthismayleadtosomeincreaseinpowerconsumption.
A/D Conversion FunctionAsthedevicecontainsa12-bitA/Dconverter, itsfull-scaleconverteddigitisedvalueisequal toFFFH.Sincethefull-scaleanaloginputvalueisequaltotheactualA/Dconverterreferencevoltage,VREF,thisgivesasinglebitanaloginputvalueofVREFdividedby4096.
1LSB=VREF÷4096
TheA/DConverterinputvoltagevaluecanbecalculatedusingthefollowingequation:
A/Dinputvoltage=A/Doutputdigitalvalue×(VREF÷4096)
Thediagramshowsthe ideal transferfunctionbetweentheanaloginputvalueandthedigitisedoutputvaluefor theA/Dconverter.Exceptfor thedigitisedzerovalue, thesubsequentdigitisedvalueswillchangeatapoint0.5LSBbelowwheretheywouldchangewithouttheoffset,andthelastfullscaledigitisedvaluewillchangeatapoint1.5LSBbelowtheVREFlevel.NotethatheretheVREFvoltageistheactualA/DconverterreferencevoltagedeterminedbytheSAVRSfield.
FFFH
FFEH
FFDH
03H
0H
01H
0 1 3 4093 4094 4095
VREF4096
Analog Input Voltage
A/D Conversion Result
1.5 LSB
0.5 LSB
4096
Ideal A/D Transfer Function
Rev. 1.00 84 st 1 01 Rev. 1.00 85 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
A/D Conversion Programming ExamplesThefollowingtwoprogrammingexamplesillustratehowtosetupandimplementanA/Dconversion.Inthefirstexample, themethodofpollingtheADBZbit intheSADC0registerisusedtodetectwhentheconversioncycleiscomplete,whereasinthesecondexample,theA/Dinterruptisusedtodeterminewhentheconversioniscomplete.
Example: using an ADBZ polling method to detect the end of conversionclr ADE ; disable ADC interruptmov a,03Hmov SADC1,a ;selectfSYS/8 as A/D clock set ADCENmov a,02h ;setupPBS0registertoconfigurepinAN0mov PBS0,amov a,20hmov SADC0,a ;enableandconnectAN0channeltoA/Dconverter:start_conversion:clr START ;highpulseonstartbittoinitiateconversionset START ;resetA/Dclr START ;startA/Dpolling_EOC:sz ADBZ ;polltheSADC0registerADBZbittodetectendofA/Dconversionjmp polling_EOC ;continuepollingmov a,SADOL ;readlowbyteconversionresultvaluemov SADOL_buffer,a ;saveresulttouserdefinedregistermov a,SADOH ;readhighbyteconversionresultvaluemov SADOH_buffer,a ;saveresulttouserdefinedregister::jmp start_conversion ;startnextA/Dconversion
Rev. 1.00 84 st 1 01 Rev. 1.00 85 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Example: using the interrupt method to detect the end of conversionclr ADE ; disable ADC interruptmov a,03Hmov SADC1,a ;selectfSYS/8 as A/D clock set ADCENmov a,02h ;setupPBS0registertoconfigurepinAN0mov PBS0,amov a,20hmov SADC0,a ;enableandconnectAN0channeltoA/DconverterStart_conversion:clr START ;highpulseonSTARTbittoinitiateconversionset START ;resetA/Dclr START ;startA/Dclr ADF ;clearADCinterruptrequestflagset ADE ; enable ADC interruptset EMI ;enableglobalinterrupt:: ; ADC interrupt service routineADC_ISR:mov acc_stack,a ;saveACCtouserdefinedmemorymov a,STATUSmov status_stack,a ;saveSTATUStouserdefinedmemory::mov a,SADOL ;readlowbyteconversionresultvaluemov SADOL_buffer,a ;saveresulttouserdefinedregistermov a,SADOH ;readhighbyteconversionresultvaluemov SADOH_buffer,a ;saveresulttouserdefinedregister::EXIT_INT_ISR:mov a,status_stackmov STATUS,a ;restoreSTATUSfromuserdefinedmemorymov a,acc_stack ;restoreACCfromuserdefinedmemoryreti
Rev. 1.00 86 st 1 01 Rev. 1.00 8 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
InterruptsInterruptsarean importantpartofanymicrocontroller system.WhenanexternaleventoraninternalfunctionsuchasaTimerModulerequiresmicrocontrollerattention, theircorrespondinginterruptwillenforceatemporarysuspensionofthemainprogramallowingthemicrocontrollertodirectattentiontotheirrespectiveneeds.Thedevicecontainsseveralexternalinterruptandinternalinterruptfunctions.TheexternalinterruptisgeneratedbytheactionoftheexternalINTnpin,whiletheinternalinterruptsaregeneratedbyvariousinternalfunctionssuchastheTMs,EEPROMwriteandTimeBases,etc.
Interrupt RegistersOverall interrupt control,whichbasicallymeans the settingof request flagswhen certainmicrocontrollerconditionsoccurandthesettingofinterruptenablebitsbytheapplicationprogram,iscontrolledbya seriesof registers, located in theSpecialPurposeDataMemory,as shownin theaccompanying table.Thenumberof registers falls into threecategories.Thefirst is theINTC0~INTC1registerswhichsetuptheprimaryinterrupts,thesecondistheMFI0~MFI1registerswhichsetuptheMulti-functioninterrupts.FinallythereisanINTEGregistertosetuptheexternalinterrupttriggeredgetype.
Eachregistercontainsanumberofenablebitstoenableordisableindividualregistersaswellasinterrupt flags to indicate thepresenceofan interrupt request.Thenamingconventionof thesefollowsaspecificpattern.Firstislistedanabbreviatedinterrupttype,thenthe(optional)numberofthatinterruptfollowedbyeitheran"E"forenable/disablebitor"F"forrequestflag.
Function Enable Bit Request Flag Notes
Global EMI — —
External Interrpt INTnE INTnF n=0 or 1
Time Base TBnE TBnF n=0 or 1
EEPROM DEE DEF —
/D Converter DE DF —
Low Voltae Detector LVE LVF —
STMSTMnPE STMnPF
n=0 or 1STMnE STMnF
Interrupt Register Bit Naming Conventions
Register Name
Bit
7 6 5 4 3 2 1 0INTEG — — — — INT1S1 INT1S0 INT0S1 INT0S0
INTC0 — LVF INT1F INT0F LVE INT1E INT0E EMI
INTC1 STM0F STM0PF DEF DF STM0E STM0PE DEE DE
INTC STM1F STM1PF TB1F TB0F STM1E STM1PE TB1E TB0E
Interrupt Register List
Rev. 1.00 86 st 1 01 Rev. 1.00 8 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
INTEG Register
Bit 7 6 5 4 3 2 1 0
Name — — — — INT1S1 INT1S0 INT0S1 INT0S0
R/W — — — — R/W R/W R/W R/W
POR — — — — 0 0 0 0
Bit7~4 Unimplemented,readas"0"Bit3~2 INT1S1~INT1S0:DefinesINT1pinexternalinterruptactiveedge
00:DisableINT1Interrupt01:Risingedge10:Fallingedge11:Risingandfallingedges
Bit1~0 INT0S1~INT0S0:DefinesINT0pinexternalinterruptactiveedge00:DisableINT0Interrupt01:Risingedge10:Fallingedge11:Risingandfallingedges
INTC0 Register
Bit 7 6 5 4 3 2 1 0
Name — LVF INT1F INT0F LVE INT1E INT0E EMI
R/W — R/W R/W R/W R/W R/W R/W R/W
POR — 0 0 0 0 0 0 0
Bit7 Unimplemented,readas"0"Bit6 LVF:LVDinterruptrequestflag
0:Norequest1:Interruptrequest
Bit5 INT1F:INT1interruptrequestflag0:Norequest1:Interruptrequest
Bit4 INT0F:INT0interruptrequestflag0:Norequest1:Interruptrequest
Bit3 LVE:LVDinterruptcontrol0:Disable1:Enable
Bit2 INT1E:INT1interruptcontrol0:Disable1:Enable
Bit1 INT0E:INT0interruptcontrol0:Disable1:Enable
Bit0 EMI:Globalinterruptcontrol0:Disable1:Enable
Rev. 1.00 88 st 1 01 Rev. 1.00 89 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
INTC1 Register
Bit 7 6 5 4 3 2 1 0
Name STM0F STM0PF DEF DF STM0E STM0PE DEE DE
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0 0 0
Bit7 STM0AF:STM0ComparatorAmatchinterruptrequestflag0:Norequest1:Interruptrequest
Bit6 STM0PF:STM0ComparatorPmatchinterruptrequestflag0:Norequest1:Interruptrequest
Bit5 DEF:DataEEPROMinterruptrequestflag0:Norequest1:Interruptrequest
Bit4 ADF:A/DConverterinterruptrequestflag0:Norequest1:Interruptrequest
Bit3 STM0AE:STM0ComparatorAmatchinterruptcontrol0:Disable1:Enable
Bit2 STM0PE:STM0ComparatorPmatchinterruptcontrol0:Disable1:Enable
Bit1 DEE:DataEEPROMinterruptcontrol0:Disable1:Enable
Bit0 ADE:A/DConverterinterruptcontrol0:Disable1:Enable
INTC2 Register
Bit 7 6 5 4 3 2 1 0
Name STM1F STM1PF TB1F TB0F STM1E STM1PE TB1E TB0E
R/W R/W R/W R/W R/W R/W R/W R/W R/W
POR 0 0 0 0 0 0 0 0
Bit7 STM1AF:STM1ComparatorAmatchinterruptrequestflag0:Norequest1:Interruptrequest
Bit6 STM1PF:STM1ComparatorPmatchinterruptrequestflag0:Norequest1:Interruptrequest
Bit5 TB1F:TimeBase1interruptrequestflag0:Norequest1:Interruptrequest
Bit4 TB0F:TimeBase0interruptrequestflag0:Norequest1:Interruptrequest
Bit3 STM1AE:STM1ComparatorAmatchinterruptcontrol0:Disable1:Enable
Rev. 1.00 88 st 1 01 Rev. 1.00 89 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Bit2 STM1PE:STM1ComparatorPmatchinterruptcontrol0:Disable1:Enable
Bit1 TB1E:TimeBase1interruptcontrol0:Disable1:Enable
Bit0 TB0E:TimeBase0interruptcontrol0:Disable1:Enable
Interrupt OperationWhentheconditionsforaninterrupteventoccur,suchasaTMComparatorPorComparatorAmatchetc.,therelevantinterruptrequestflagwillbeset.Whethertherequestflagactuallygeneratesaprogramjumptotherelevantinterruptvectorisdeterminedbytheconditionoftheinterruptenablebit.Iftheenablebitissethighthentheprogramwilljumptoitsrelevantvector;iftheenablebitiszerothenalthoughtheinterruptrequestflagissetanactualinterruptwillnotbegeneratedandtheprogramwillnotjumptotherelevantinterruptvector.Theglobalinterruptenablebit,ifclearedtozero,willdisableallinterrupts.
Whenaninterruptisgenerated,theProgramCounter,whichstorestheaddressofthenextinstructiontobeexecuted,willbetransferredontothestack.TheProgramCounterwillthenbeloadedwithanewaddresswhichwillbethevalueofthecorrespondinginterruptvector.Themicrocontrollerwillthenfetchitsnextinstructionfromthisinterruptvector.Theinstructionatthisvectorwillusuallybea"JMP"whichwilljumptoanothersectionofprogramwhichisknownastheinterruptserviceroutine.Hereislocatedthecodetocontroltheappropriateinterrupt.Theinterruptserviceroutinemustbe terminatedwitha"RETI",whichretrieves theoriginalProgramCounteraddress fromthestackandallowsthemicrocontrollertocontinuewithnormalexecutionatthepointwheretheinterruptoccurred.
Thevarious interruptenablebits, togetherwith theirassociatedrequest flags,areshownin theaccompanyingdiagramswith theirorderofpriority.Some interrupt sourceshave theirownindividualvectorwhileothersshare thesamemulti-function interruptvector.Oncean interruptsubroutineisserviced,all theother interruptswillbeblocked,as theglobal interruptenablebit,EMIbitwillbeclearedautomatically.Thiswillpreventanyfurtherinterruptnestingfromoccurring.However, ifother interruptrequestsoccurduringthis interval,althoughtheinterruptwillnotbeimmediatelyserviced,therequestflagwillstillberecorded.
Ifaninterruptrequiresimmediateservicingwhiletheprogramisalreadyinanotherinterruptserviceroutine,theEMIbitshouldbesetafterenteringtheroutine,toallowinterruptnesting.Ifthestackisfull,theinterruptrequestwillnotbeacknowledged,eveniftherelatedinterruptisenabled,untiltheStackPointerisdecremented.Ifimmediateserviceisdesired,thestackmustbepreventedfrombecomingfull.Incaseofsimultaneousrequests,theaccompanyingdiagramshowstheprioritythatisapplied.Alloftheinterruptrequestflagswhensetwillwake-upthedeviceifit isinSLEEPorIDLEMode,however topreventawake-upfromoccurringthecorrespondingflagshouldbesetbeforethedeviceisinSLEEPorIDLEMode.
Rev. 1.00 90 st 1 01 Rev. 1.00 91 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
InterrptName
Reqest Flas
Enable Bits
Master Enable Vector
EMI ato disabled in ISR
PriorityHih
Low
04HEMI
0H
INT1 Pin
EMI
CHEMI
STM0 Comp. STM0F STM0E
08HEMI
8H
STM0 Comp.P STM0PF STM0PE
EMI
14HEMI
LVD LVF LVE
18H
/D Converter DF DE
EMI
1CH
EEPROM DEF DEE
EMI
Time Base 1 TB1F TB1E
0CH
INT1F INT1E
EMI
10HEMI
4HEMI
Time Base 0 TB0F TB0E
INT0 Pin INT0F INT0E
Reqest Fla ato reset in ISR
STM1 Comp. STM1F STM1E
STM1 Comp.P STM1PF STM1PE
Interrupt Structure
External InterruptsTheexternal interruptsarecontrolledbysignal transitionsonthepinsINT0~INT1.Anexternalinterruptrequestwill takeplacewhentheexternalinterruptrequestflags,INT0F~INT1F,areset,whichwilloccurwhenatransition,whosetypeischosenbytheedgeselectbits,appearsontheexternal interruptpins.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,theglobal interruptenablebit,EMI,andrespectiveexternal interruptenablebit, INT0E~INT1E,mustfirstbeset.Additionally thecorrect interruptedgetypemustbeselectedusingtheINTEGregistertoenabletheexternalinterruptfunctionandtochoosethetriggeredgetype.Astheexternalinterruptpinsarepin-sharedwithI/Opins,theycanonlybeconfiguredasexternalinterruptpinsiftheirexternalinterruptenablebitinthecorrespondinginterruptregisterhasbeensetandtheexternalinterruptpinisselectedbythecorrespondingpin-sharedfunctionselectionbits.Thepinmustalsobesetupasaninputbysettingthecorrespondingbitintheportcontrolregister.Whentheinterruptisenabled,thestackisnotfullandthecorrecttransitiontypeappearsontheexternalinterruptpin,asubroutinecalltotheexternalinterruptvector,willtakeplace.Whentheinterruptisserviced,theexternalinterruptrequestflags,INT0F~INT1F,willbeautomaticallyresetandtheEMIbitwillbeautomaticallyclearedtodisableotherinterrupts.Notethatanypull-highresistorselectionsontheexternalinterruptpinswillremainvalidevenifthepinisusedasanexternalinterruptinput.TheINTEGregister isusedtoselect thetypeofactiveedgethatwill triggertheexternal interrupt.Achoiceofeitherrisingorfallingorbothedgetypescanbechosentotriggeranexternalinterrupt.NotethattheINTEGregistercanalsobeusedtodisabletheexternalinterruptfunction.
Rev. 1.00 90 st 1 01 Rev. 1.00 91 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
LVD InterruptAnLVDInterruptrequestwill takeplacewhentheLVDInterruptrequestflag,LVF,isset,whichoccurswhentheLowVoltageDetectorfunctiondetectsalowpowersupplyvoltage.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress, theglobal interruptenablebit,EMI,andLowVoltageInterruptenablebit,LVE,mustfirstbeset.Whenthe interrupt isenabled, thestackisnotfullandalowvoltageconditionoccurs,asubroutinecalltotheLVDInterruptvector,will takeplace.WhentheLowVoltageInterruptisserviced,theLVDInterruptflag,LVF,willbeautomaticallycleared.TheEMIbitwillalsobeautomaticallyclearedtodisableotherinterrupts.
A/D Converter InterruptTheA/DConverterInterruptiscontrolledbytheterminationofanA/Dconversionprocess.AnA/DConverterInterruptrequestwilltakeplacewhentheA/DConverterInterruptrequestflag,ADF,isset,whichoccurswhentheA/Dconversionprocessfinishes.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,andA/DInterruptenablebit,ADE,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandtheA/Dconversionprocesshasended,asubroutinecalltotheA/DConverterInterruptvector,willtakeplace.Whentheinterruptisserviced,theA/DConverterInterruptflag,ADF,willbeautomaticallycleared.TheEMIbitwillalsobeautomaticallyclearedtodisableotherinterrupts.
Time Base InterruptsThefunctionoftheTimeBaseInterruptsistoprovideregulartimesignalintheformofaninternalinterrupt.Theyarecontrolledbytheoverflowsignalsfromtheirrespectivetimerfunctions.Whenthesehappenstheirrespective interruptrequestflags,TBnFwillbeset.Toallowtheprogramtobranchtotheirrespectiveinterruptvectoraddresses,theglobalinterruptenablebit,EMIandTimeBaseenablebits,TBnE,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandtheTimeBaseoverflows,asubroutinecalltotheirrespectivevectorlocationswilltakeplace.Whentheinterruptisserviced,therespectiveinterruptrequestflag,TBnF,willbeautomaticallyresetandtheEMIbitwillbeclearedtodisableotherinterrupts.
ThepurposeoftheTimeBaseInterruptistoprovideaninterruptsignalatfixedtimeperiods.Itsclocksource, fPSC,originates fromthe internalclocksourcefSYS, fSYS/4or fSUBand thenpassesthroughadivider,thedivisionratioofwhichisselectedbyprogrammingtheappropriatebitsintheTBnCregistertoobtainlongerinterruptperiodswhosevalueranges.TheclocksourcewhichinturncontrolstheTimeBaseinterruptperiodisselectedusingtheCLKSEL1~CLKSEL0bitsinthePSCRregister.
MUX
fSYS/4fSYS
fSUB
Prescaler
CLKSEL[1:0]
fPSC MUX
TBn[:0]
Time Base n Interrpt
TBnON
fPSC/8 ~ fPSC/15
Time Base Interrupt (n=0 or 1)
Rev. 1.00 9 st 1 01 Rev. 1.00 93 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
PSCR RegisterBit 7 6 5 4 3 2 1 0
Name — — — — — — CLKSEL1 CLKSEL0R/W — — — — — — R/W R/WPOR — — — — — — 0 0
Bit7~2 Unimplemented,readas"0"Bit1~0 CLKSEL1~CLKSEL0:Prescalerclocksourceselection
00:fSYS
01:fSYS/41x:fSUB
TBnC Register (n=0 or 1)Bit 7 6 5 4 3 2 1 0
Name TBnON — — — — TBn TBn1 TBn0R/W R/W — — — — R/W R/W R/WPOR 0 — — — — 0 0 0
Bit7 TBnON:TimeBasenControl0:Disable1:Enable
Bit6~3 Unimplemented,readas"0"Bit2~0 TBn2~TBn0:SelectTimeBasenTime-outPeriod
000:28/fPSC001:29/fPSC010:210/fPSC011:211/fPSC100:212/fPSC101:213/fPSC110:214/fPSC111:215/fPSC
EEPROM Write InterruptAnEEPROMInterruptrequestwilltakeplacewhentheEEPROMInterruptrequestflag,DEF,isset,whichoccurswhenanEEPROMWritecycleends.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress, theglobal interruptenablebit,EMI,andEEPROMInterruptenablebit,DEE,mustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandanEEPROMWritecycleends,asubroutinecalltotherespectiveEEPROMInterruptvectorwilltakeplace.WhentheEEPROMInterruptisserviced,theEMIbitwillbeautomaticallyclearedtodisableotherinterruptsandtheEEPROMinterruptrequestflagalsowillbeautomaticallycleared.
STM InterruptsThetwoStandardTypeTMseachhavetwointerrupts,onecomesfromthecomparatorAmatchsituationandtheothercomesfromthecomparatorPmatchsituation.ForalloftheTMtypestherearetwointerruptrequestflagsandtwoenablecontrolbits.ATMinterruptrequestwill takeplacewhenanyoftheTMrequestflagsareset,asituationwhichoccurswhenaTMcomparatorPorAmatchsituationhappens.
Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,andrespectiveTMInterruptenablebitmustfirstbeset.Whentheinterruptisenabled,thestackisnotfullandaTMcomparatormatchsituationoccurs,asubroutinecalltotherespectiveSTMCCRAorCCRPInterruptvectorlocation,willtakeplace.WhentheTMinterruptisserviced,theEMIbitwillbeautomaticallyclearedtodisableotherinterruptsandtheTMinterruptrequestflagwillalsobeautomaticallycleared.
Rev. 1.00 9 st 1 01 Rev. 1.00 93 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Interrupt Wake-up FunctionEachof the interruptfunctionshas thecapabilityofwakingupthemicrocontrollerwhenin theSLEEPorIDLEMode.Awake-upisgeneratedwhenaninterruptrequestflagchangesfromlowtohighandisindependentofwhethertheinterruptisenabledornot.Therefore,eventhoughthedeviceisintheSLEEPorIDLEModeanditssystemoscillatorstopped,situationssuchasexternaledgetransitionsontheexternalinterruptpinmaycausetheirrespectiveinterruptflagtobesethighandconsequentlygenerateaninterrupt.
Caremustthereforebetakenifspuriouswake-upsituationsaretobeavoided.Ifaninterruptwake-upfunctionistobedisabledthenthecorrespondinginterruptrequestflagshouldbesethighbeforethedeviceenterstheSLEEPorIDLEMode.Theinterruptenablebitshavenoeffectontheinterruptwake-upfunction.
Programming ConsiderationsBydisablingtherelevantinterruptenablebits,arequestedinterruptcanbepreventedfrombeingserviced,however,oncean interrupt request flag is set, itwill remain in thiscondition in theinterruptregisteruntilthecorrespondinginterruptisservicedoruntiltherequestflagisclearedbytheapplicationprogram.
It isrecommendedthatprogramsdonotusethe"CALL"instructionwithintheinterruptservicesubroutine.Interruptsoftenoccurinanunpredictablemannerorneedtobeservicedimmediately.Ifonlyonestackisleftandtheinterruptisnotwellcontrolled,theoriginalcontrolsequencewillbedamagedonceaCALLsubroutineisexecutedintheinterruptsubroutine.
EveryinterrupthasthecapabilityofwakingupthemicrocontrollerwhenitisintheSLEEPorIDLEMode,thewakeupbeinggeneratedwhentheinterruptrequestflagchangesfromlowtohigh.IfitisrequiredtopreventacertaininterruptfromwakingupthemicrocontrollerthenitsrespectiverequestflagshouldbefirstsethighbeforeentertheSLEEPorIDLEMode.
AsonlytheProgramCounter ispushedontothestack, thenwhentheinterrupt isserviced, if thecontentsof theaccumulator,statusregisterorotherregistersarealteredbythe interruptserviceprogram,theircontentsshouldbesavedto thememoryat thebeginningof the interruptserviceroutine.
Toreturnfromaninterruptsubroutine,eitheraRETorRETIinstructionmaybeexecuted.TheRETIinstructioninadditiontoexecutingareturntothemainprogramalsoautomaticallysetstheEMIbithightoallowfurtherinterrupts.TheRETinstructionhoweveronlyexecutesareturntothemainprogramleavingtheEMIbitinitspresentzerostateandthereforedisablingtheexecutionoffurtherinterrupts.
Rev. 1.00 94 st 1 01 Rev. 1.00 95 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Low Voltage Detector – LVDThedevicehasaLowVoltageDetectorfunction,alsoknownasLVD.Thisenabledthedevicetomonitorthepowersupplyvoltage,VDD,andprovideawarningsignalshoulditfallbelowacertainlevel.Thisfunctionmaybeespeciallyusefulinbatteryapplicationswherethesupplyvoltagewillgraduallyreduceasthebatteryages,asitallowsanearlywarningbatterylowsignaltobegenerated.TheLowVoltageDetectoralsohasthecapabilityofgeneratinganinterruptsignal.
LVD RegisterTheLowVoltageDetectorfunctioniscontrolledusingasingleregisterwiththenameLVDC.Threebits inthisregister,VLVD2~VLVD0,areusedtoselectoneofeightfixedvoltagesbelowwhichalowvoltageconditionwillbedetermined.AlowvoltageconditionisindicatedwhentheLVDObitisset.IftheLVDObitislow,thisindicatesthattheVDDvoltageisabovethepresetlowvoltagevalue.TheLVDENbit isusedtocontrol theoverallon/offfunctionof thelowvoltagedetector.Settingthebithighwillenablethelowvoltagedetector.Clearingthebittozerowillswitchofftheinternallowvoltagedetectorcircuits.Asthelowvoltagedetectorwillconsumeacertainamountofpower,itmaybedesirabletoswitchoffthecircuitwhennotinuse,animportantconsiderationinpowersensitivebatterypoweredapplications.
LVDC RegisterBit 7 6 5 4 3 2 1 0
Name — — LVDO LVDEN VBGEN VLVD VLVD1 VLVD0R/W — — R R/W R/W R/W R/W R/WPOR — — 0 0 0 0 0 0
Bit7~6 Unimplemented,readas"0"Bit5 LVDO:LVDOutputFlag
0:NoLowVoltageDetected1:LowVoltageDetected
Bit4 LVDEN:LowVoltageDetectorControl0:Disable1:Enable
Bit3 VBGEN:BandgapBufferControl0:Disable1:Enable
NotethattheBandgapcircuitisenabledwhentheLVDortheLVRfunctionisenabledorwhentheVBGENbitissethigh.
Bit2~0 VLVD2~VLVD0:SelectLVDVoltage000:2.0V001:2.2V010:2.4V011:2.7V100:3.0V101:3.3V110:3.6V111:4.0V
Rev. 1.00 94 st 1 01 Rev. 1.00 95 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
LVD OperationTheLowVoltageDetectorfunctionoperatesbycomparingthepowersupplyvoltage,VDD,withapre-specifiedvoltagelevelstoredintheLVDCregister.Thishasarangeofbetween2.0Vand4.0V.Whenthepowersupplyvoltage,VDD, fallsbelowthispre-determinedvalue, theLVDObitwillbesethighindicatingalowpowersupplyvoltagecondition.TheLowVoltageDetectorfunctionissuppliedbya referencevoltagewhichwillbeautomaticallyenabled.When thedevice is intheSLEEPmode, thelowvoltagedetectorwillbedisabledevenif theLVDENbit ishigh.AfterenablingtheLowVoltageDetector,atimedelaytLVDSshouldbeallowedforthecircuitrytostabilisebeforereadingtheLVDObit.NotealsothatastheVDDvoltagemayriseandfallratherslowly,atthevoltagenearsthatofVLVD,theremaybemultiplebitLVDOtransitions.
VDD
LVDEN
LVDO
VLVD
tLVDS
LVD Operation
TheLowVoltageDetectoralsohasitsowninterrupt,providinganalternativemeansoflowvoltagedetection,inadditiontopollingtheLVDObit.TheinterruptwillonlybegeneratedafteradelayoftLVDaftertheLVDObithasbeensethighbyalowvoltagecondition.Inthiscase,theLVFinterruptrequest flagwillbeset,causingan interrupt tobegenerated ifVDD fallsbelowthepresetLVDvoltage.Thiswillcausethedevicetowake-upfromtheIDLEMode,howeveriftheLowVoltageDetectorwakeupfunctionisnotrequiredthentheLVFflagshouldbefirstsethighbeforethedeviceentertheIDLEMode.TheLVDfunctionisalwaysdisabledintheSLEEPmode.
Rev. 1.00 96 st 1 01 Rev. 1.00 9 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Instruction Set
IntroductionCentral to thesuccessfuloperationofanymicrocontroller is its instructionset,whichisasetofprograminstructioncodesthatdirectsthemicrocontrollertoperformcertainoperations.InthecaseofHoltekmicrocontroller,acomprehensiveandflexiblesetofover60instructionsisprovidedtoenableprogrammerstoimplementtheirapplicationwiththeminimumofprogrammingoverheads.
Foreasierunderstandingofthevariousinstructioncodes, theyhavebeensubdividedintoseveralfunctionalgroupings.
Instruction TimingMostinstructionsareimplementedwithinoneinstructioncycle.Theexceptionstothisarebranch,call,or tablereadinstructionswheretwoinstructioncyclesarerequired.Oneinstructioncycleisequalto4systemclockcycles,thereforeinthecaseofan4MHzsystemoscillator,mostinstructionswouldbeimplementedwithin0.5μsandbranchorcall instructionswouldbeimplementedwithin1μs.Although instructionswhichrequireonemorecycle to implementaregenerally limited totheJMP,CALL,RET,RETIandtablereadinstructions, it is important torealize thatanyotherinstructionswhichinvolvemanipulationoftheProgramCounterLowregisterorPCLwillalsotakeonemorecycletoimplement.AsinstructionswhichchangethecontentsofthePCLwill implyadirect jumptothatnewaddress,onemorecyclewillberequired.Examplesofsuchinstructionswouldbe"CLRPCL"or"MOVPCL,A".Forthecaseofskipinstructions,itmustbenotedthatiftheresultofthecomparisoninvolvesaskipoperationthenthiswillalsotakeonemorecycle,ifnoskipisinvolvedthenonlyonecycleisrequired.
Moving and Transferring DataThe transferofdatawithin themicrocontrollerprogram isoneof themost frequentlyusedoperations.MakinguseofthreekindsofMOVinstructions,datacanbetransferredfromregisterstotheAccumulatorandvice-versaaswellasbeingabletomovespecificimmediatedatadirectlyintotheAccumulator.Oneofthemostimportantdatatransferapplicationsis toreceivedatafromtheinputportsandtransferdatatotheoutputports.
Arithmetic OperationsTheabilitytoperformcertainarithmeticoperationsanddatamanipulationisanecessaryfeatureofmostmicrocontrollerapplications.WithintheHoltekmicrocontrollerinstructionsetarearangeofaddandsubtract instructionmnemonicstoenablethenecessaryarithmetictobecarriedout.Caremustbe taken toensurecorrecthandlingofcarryandborrowdatawhenresultsexceed255foradditionandlessthan0forsubtraction.TheincrementanddecrementinstructionsINC,INCA,DECandDECAprovideasimplemeansofincreasingordecreasingbyavalueofoneofthevaluesinthedestinationspecified.
Rev. 1.00 96 st 1 01 Rev. 1.00 9 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Logical and Rotate OperationThestandardlogicaloperationssuchasAND,OR,XORandCPLallhavetheirowninstructionwithintheHoltekmicrocontroller instructionset.Aswiththecaseofmost instructionsinvolvingdatamanipulation, datamust pass through theAccumulatorwhichmay involve additionalprogrammingsteps. Inall logicaldataoperations, thezero flagmaybeset if the resultof theoperationiszero.AnotherformoflogicaldatamanipulationcomesfromtherotateinstructionssuchasRR,RL,RRCandRLCwhichprovideasimplemeansofrotatingonebitrightorleft.Differentrotateinstructionsexistdependingonprogramrequirements.Rotateinstructionsareusefulforserialportprogrammingapplicationswheredatacanberotatedfromaninternalregister intotheCarrybitfromwhereitcanbeexaminedandthenecessaryserialbitsethighorlow.Anotherapplicationwhichrotatedataoperationsareusedistoimplementmultiplicationanddivisioncalculations.
Branches and Control TransferProgrambranchingtakestheformofeitherjumpstospecifiedlocationsusingtheJMPinstructionor toa subroutineusing theCALL instruction.Theydiffer in the sense that in thecaseofasubroutinecall, theprogrammustreturn to the instruction immediatelywhenthesubroutinehasbeencarriedout.Thisisdonebyplacingareturninstruction"RET"inthesubroutinewhichwillcausetheprogramtojumpbacktotheaddressrightaftertheCALLinstruction.InthecaseofaJMPinstruction,theprogramsimplyjumpstothedesiredlocation.ThereisnorequirementtojumpbacktotheoriginaljumpingoffpointasinthecaseoftheCALLinstruction.Onespecialandextremelyusefulsetofbranchinstructionsaretheconditionalbranches.Hereadecisionisfirstmaderegardingtheconditionofacertaindatamemoryor individualbits.Dependingupon theconditions, theprogramwillcontinuewiththenextinstructionorskipoveritandjumptothefollowinginstruction.These instructionsare thekey todecisionmakingandbranchingwithin theprogramperhapsdeterminedbytheconditionofcertaininputswitchesorbytheconditionofinternaldatabits.
Bit OperationsTheabilitytoprovidesinglebitoperationsonDataMemoryisanextremelyflexiblefeatureofallHoltekmicrocontrollers.Thisfeature isespeciallyusefulforoutputportbitprogrammingwhereindividualbitsorportpinscanbedirectlysethighorlowusingeitherthe"SET[m].i"or"CLR[m].i" instructionsrespectively.Thefeatureremovestheneedforprogrammers tofirstreadthe8-bitoutputport,manipulatetheinputdatatoensurethatotherbitsarenotchangedandthenoutputtheportwiththecorrectnewdata.Thisread-modify-writeprocessistakencareofautomaticallywhenthesebitoperationinstructionsareused.
Table Read OperationsDatastorage isnormally implementedbyusing registers.However,whenworkingwith largeamountsoffixeddata, thevolumeinvolvedoftenmakesit inconvenienttostorethefixeddataintheDataMemory.Toovercomethisproblem,HoltekmicrocontrollersallowanareaofProgramMemory tobesetasa tablewheredatacanbedirectlystored.Asetofeasy touse instructionsprovides themeansbywhich this fixeddatacanbereferencedandretrievedfromtheProgramMemory.
Other OperationsInaddition to theabovefunctional instructions,a rangeofother instructionsalsoexistsuchasthe"HALT"instructionforPower-downoperationsand instructions tocontrol theoperationoftheWatchdogTimerfor reliableprogramoperationsunderextremeelectricorelectromagneticenvironments.Fortheirrelevantoperations,refertothefunctionalrelatedsections.
Rev. 1.00 98 st 1 01 Rev. 1.00 99 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Instruction Set SummaryThefollowingtabledepictsasummaryoftheinstructionsetcategorisedaccordingtofunctionandcanbeconsultedasabasicinstructionreferenceusingthefollowinglistedconventions.
Table Conventionsx:Bitsimmediatedatam:DataMemoryaddressA:Accumulatori:0~7numberofbitsaddr:Programmemoryaddress
Mnemonic Description Cycles Flag AffectedArithmeticDD [m] dd Data Memory to CC 1 Z C C OVDDM [m] dd CC to Data Memory 1Note Z C C OVDD x dd immediate data to CC 1 Z C C OVDC [m] dd Data Memory to CC with Carry 1 Z C C OVDCM [m] dd CC to Data memory with Carry 1Note Z C C OVSUB x Sbtract immediate data from the CC 1 Z C C OVSUB [m] Sbtract Data Memory from CC 1 Z C C OVSUBM [m] Sbtract Data Memory from CC with reslt in Data Memory 1Note Z C C OVSBC [m] Sbtract Data Memory from CC with Carry 1 Z C C OVSBCM [m] Sbtract Data Memory from CC with Carry reslt in Data Memory 1Note Z C C OVD [m] Decimal adjst CC for ddition with reslt in Data Memory 1Note CLogic OperationND [m] Loical ND Data Memory to CC 1 ZOR [m] Loical OR Data Memory to CC 1 ZXOR [m] Loical XOR Data Memory to CC 1 ZNDM [m] Loical ND CC to Data Memory 1Note ZORM [m] Loical OR CC to Data Memory 1Note ZXORM [m] Loical XOR CC to Data Memory 1Note ZND x Loical ND immediate Data to CC 1 ZOR x Loical OR immediate Data to CC 1 ZXOR x Loical XOR immediate Data to CC 1 ZCPL [m] Complement Data Memory 1Note ZCPL [m] Complement Data Memory with reslt in CC 1 ZIncrement & DecrementINC [m] Increment Data Memory with reslt in CC 1 ZINC [m] Increment Data Memory 1Note ZDEC [m] Decrement Data Memory with reslt in CC 1 ZDEC [m] Decrement Data Memory 1Note ZRotateRR [m] Rotate Data Memory riht with reslt in CC 1 NoneRR [m] Rotate Data Memory riht 1Note NoneRRC [m] Rotate Data Memory riht throh Carry with reslt in CC 1 CRRC [m] Rotate Data Memory riht throh Carry 1Note CRL [m] Rotate Data Memory left with reslt in CC 1 NoneRL [m] Rotate Data Memory left 1Note NoneRLC [m] Rotate Data Memory left throh Carry with reslt in CC 1 CRLC [m] Rotate Data Memory left throh Carry 1Note C
Rev. 1.00 98 st 1 01 Rev. 1.00 99 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Mnemonic Description Cycles Flag AffectedData MoveMOV [m] Move Data Memory to CC 1 NoneMOV [m] Move CC to Data Memory 1Note NoneMOV x Move immediate data to CC 1 NoneBit OperationCLR [m].i Clear bit of Data Memory 1Note NoneSET [m].i Set bit of Data Memory 1Note NoneBranch OperationJMP addr Jmp nconditionally NoneSZ [m] Skip if Data Memory is zero 1Note NoneSZ [m] Skip if Data Memory is zero with data movement to CC 1Note NoneSZ [m].i Skip if bit i of Data Memory is zero 1Note NoneSNZ [m].i Skip if bit i of Data Memory is not zero 1Note NoneSIZ [m] Skip if increment Data Memory is zero 1Note NoneSDZ [m] Skip if decrement Data Memory is zero 1Note NoneSIZ [m] Skip if increment Data Memory is zero with reslt in CC 1Note NoneSDZ [m] Skip if decrement Data Memory is zero with reslt in CC 1Note NoneCLL addr Sbrotine call NoneRET Retrn from sbrotine NoneRET x Retrn from sbrotine and load immediate data to CC NoneRETI Retrn from interrpt NoneTable Read OperationTBRD [m] Read table (specific page) to TBLH and Data Memory Note NoneTBRDC [m] Read table (crrent pae) to TBLH and Data Memory Note NoneTBRDL [m] Read table (last pae) to TBLH and Data Memory Note NoneMiscellaneousNOP No operation 1 NoneCLR [m] Clear Data Memory 1Note NoneSET [m] Set Data Memory 1Note NoneCLR WDT Clear Watchdo Timer 1 TO PDFCLR WDT1 Pre-clear Watchdo Timer 1 TO PDFCLR WDT Pre-clear Watchdo Timer 1 TO PDFSWP [m] Swap nibbles of Data Memory 1Note NoneSWP [m] Swap nibbles of Data Memory with reslt in CC 1 NoneHLT Enter power down mode 1 TO PDF
Note:1.Forskipinstructions,iftheresultofthecomparisoninvolvesaskipthentwocyclesarerequired,ifnoskiptakesplaceonlyonecycleisrequired.
2.AnyinstructionwhichchangesthecontentsofthePCLwillalsorequire2cyclesforexecution.3.For the"CLRWDT1"and"CLRWDT2"instructions theTOandPDFflagsmaybeaffectedbytheexecution status.TheTOandPDF flagsareclearedafterboth "CLRWDT1"and"CLRWDT2"instructionsareconsecutivelyexecuted.OtherwisetheTOandPDFflagsremainunchanged.
Rev. 1.00 100 st 1 01 Rev. 1.00 101 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Instruction Definition
ADC A,[m] AddDataMemorytoACCwithCarryDescription ThecontentsofthespecifiedDataMemory,Accumulatorandthecarryflagareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+[m]+CAffectedflag(s) OV,Z,AC,C
ADCM A,[m] AddACCtoDataMemorywithCarryDescription ThecontentsofthespecifiedDataMemory,Accumulatorandthecarryflagareadded. TheresultisstoredinthespecifiedDataMemory.Operation [m]←ACC+[m]+CAffectedflag(s) OV,Z,AC,C
ADD A,[m] AddDataMemorytoACCDescription ThecontentsofthespecifiedDataMemoryandtheAccumulatorareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+[m]Affectedflag(s) OV,Z,AC,C
ADD A,x AddimmediatedatatoACCDescription ThecontentsoftheAccumulatorandthespecifiedimmediatedataareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+xAffectedflag(s) OV,Z,AC,C
ADDM A,[m] AddACCtoDataMemoryDescription ThecontentsofthespecifiedDataMemoryandtheAccumulatorareadded. TheresultisstoredinthespecifiedDataMemory.Operation [m]←ACC+[m]Affectedflag(s) OV,Z,AC,C
AND A,[m] LogicalANDDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwiselogicalAND operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″AND″[m]Affectedflag(s) Z
AND A,x LogicalANDimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalAND operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″AND″xAffectedflag(s) Z
ANDM A,[m] LogicalANDACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalAND operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″AND″[m]Affectedflag(s) Z
Rev. 1.00 100 st 1 01 Rev. 1.00 101 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
CALL addr SubroutinecallDescription Unconditionallycallsasubroutineatthespecifiedaddress.TheProgramCounterthen incrementsby1toobtaintheaddressofthenextinstructionwhichisthenpushedontothe stack.Thespecifiedaddressisthenloadedandtheprogramcontinuesexecutionfromthis newaddress.Asthisinstructionrequiresanadditionaloperation,itisatwocycleinstruction.Operation Stack←ProgramCounter+1 ProgramCounter←addrAffectedflag(s) None
CLR [m] ClearDataMemoryDescription EachbitofthespecifiedDataMemoryisclearedto0.Operation [m]←00HAffectedflag(s) None
CLR [m].i ClearbitofDataMemoryDescription BitiofthespecifiedDataMemoryisclearedto0.Operation [m].i←0Affectedflag(s) None
CLR WDT ClearWatchdogTimerDescription TheTO,PDFflagsandtheWDTareallcleared.Operation WDTcleared TO←0 PDF←0Affectedflag(s) TO,PDF
CLR WDT1 Pre-clearWatchdogTimerDescription TheTO,PDFflagsandtheWDTareallcleared.Notethatthisinstructionworksin conjunctionwithCLRWDT2andmustbeexecutedalternatelywithCLRWDT2tohave effect.RepetitivelyexecutingthisinstructionwithoutalternatelyexecutingCLRWDT2will havenoeffect.Operation WDTcleared TO←0 PDF←0Affectedflag(s) TO,PDF
CLR WDT2 Pre-clearWatchdogTimerDescription TheTO,PDFflagsandtheWDTareallcleared.Notethatthisinstructionworksinconjunction withCLRWDT1andmustbeexecutedalternatelywithCLRWDT1tohaveeffect. RepetitivelyexecutingthisinstructionwithoutalternatelyexecutingCLRWDT1willhaveno effect.Operation WDTcleared TO←0 PDF←0Affectedflag(s) TO,PDF
CPL [m] ComplementDataMemoryDescription EachbitofthespecifiedDataMemoryislogicallycomplemented(1′scomplement).Bitswhich previouslycontaineda1arechangedto0andviceversa.Operation [m]←[m]Affectedflag(s) Z
Rev. 1.00 10 st 1 01 Rev. 1.00 103 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
CPLA [m] ComplementDataMemorywithresultinACCDescription EachbitofthespecifiedDataMemoryislogicallycomplemented(1′scomplement).Bitswhich previouslycontaineda1arechangedto0andviceversa.Thecomplementedresultisstoredin theAccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]Affectedflag(s) Z
DAA [m] Decimal-AdjustACCforadditionwithresultinDataMemoryDescription ConvertthecontentsoftheAccumulatorvaluetoaBCD(BinaryCodedDecimal)value resultingfromthepreviousadditionoftwoBCDvariables.Ifthelownibbleisgreaterthan9 orifACflagisset,thenavalueof6willbeaddedtothelownibble.Otherwisethelownibble remainsunchanged.Ifthehighnibbleisgreaterthan9oriftheCflagisset,thenavalueof6 willbeaddedtothehighnibble.Essentially,thedecimalconversionisperformedbyadding 00H,06H,60Hor66HdependingontheAccumulatorandflagconditions.OnlytheCflag maybeaffectedbythisinstructionwhichindicatesthatiftheoriginalBCDsumisgreaterthan 100,itallowsmultipleprecisiondecimaladdition.Operation [m]←ACC+00Hor [m]←ACC+06Hor [m]←ACC+60Hor [m]←ACC+66HAffectedflag(s) C
DEC [m] DecrementDataMemoryDescription DatainthespecifiedDataMemoryisdecrementedby1.Operation [m]←[m]−1Affectedflag(s) Z
DECA [m] DecrementDataMemorywithresultinACCDescription DatainthespecifiedDataMemoryisdecrementedby1.Theresultisstoredinthe Accumulator.ThecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]−1Affectedflag(s) Z
HALT EnterpowerdownmodeDescription Thisinstructionstopstheprogramexecutionandturnsoffthesystemclock.Thecontentsof theDataMemoryandregistersareretained.TheWDTandprescalerarecleared.Thepower downflagPDFissetandtheWDTtime-outflagTOiscleared.Operation TO←0 PDF←1Affectedflag(s) TO,PDF
INC [m] IncrementDataMemoryDescription DatainthespecifiedDataMemoryisincrementedby1.Operation [m]←[m]+1Affectedflag(s) Z
INCA [m] IncrementDataMemorywithresultinACCDescription DatainthespecifiedDataMemoryisincrementedby1.TheresultisstoredintheAccumulator. ThecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]+1Affectedflag(s) Z
Rev. 1.00 10 st 1 01 Rev. 1.00 103 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
JMP addr JumpunconditionallyDescription ThecontentsoftheProgramCounterarereplacedwiththespecifiedaddress.Program executionthencontinuesfromthisnewaddress.Asthisrequirestheinsertionofadummy instructionwhilethenewaddressisloaded,itisatwocycleinstruction.Operation ProgramCounter←addrAffectedflag(s) None
MOV A,[m] MoveDataMemorytoACCDescription ThecontentsofthespecifiedDataMemoryarecopiedtotheAccumulator.Operation ACC←[m]Affectedflag(s) None
MOV A,x MoveimmediatedatatoACCDescription TheimmediatedataspecifiedisloadedintotheAccumulator.Operation ACC←xAffectedflag(s) None
MOV [m],A MoveACCtoDataMemoryDescription ThecontentsoftheAccumulatorarecopiedtothespecifiedDataMemory.Operation [m]←ACCAffectedflag(s) None
NOP NooperationDescription Nooperationisperformed.Executioncontinueswiththenextinstruction.Operation NooperationAffectedflag(s) None
OR A,[m] LogicalORDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwise logicalORoperation.TheresultisstoredintheAccumulator.Operation ACC←ACC″OR″[m]Affectedflag(s) Z
OR A,x LogicalORimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″OR″xAffectedflag(s) Z
ORM A,[m] LogicalORACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalOR operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″OR″[m]Affectedflag(s) Z
RET ReturnfromsubroutineDescription TheProgramCounterisrestoredfromthestack.Programexecutioncontinuesattherestored address.Operation ProgramCounter←StackAffectedflag(s) None
Rev. 1.00 104 st 1 01 Rev. 1.00 105 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
RET A,x ReturnfromsubroutineandloadimmediatedatatoACCDescription TheProgramCounterisrestoredfromthestackandtheAccumulatorloadedwiththespecified immediatedata.Programexecutioncontinuesattherestoredaddress.Operation ProgramCounter←Stack ACC←xAffectedflag(s) None
RETI ReturnfrominterruptDescription TheProgramCounterisrestoredfromthestackandtheinterruptsarere-enabledbysettingthe EMIbit.EMIisthemasterinterruptglobalenablebit.Ifaninterruptwaspendingwhenthe RETIinstructionisexecuted,thependingInterruptroutinewillbeprocessedbeforereturning tothemainprogram.Operation ProgramCounter←Stack EMI←1Affectedflag(s) None
RL [m] RotateDataMemoryleftDescription ThecontentsofthespecifiedDataMemoryarerotatedleftby1bitwithbit7rotatedintobit0.Operation [m].(i+1)←[m].i;(i=0~6) [m].0←[m].7Affectedflag(s) None
RLA [m] RotateDataMemoryleftwithresultinACCDescription ThecontentsofthespecifiedDataMemoryarerotatedleftby1bitwithbit7rotatedintobit0. TherotatedresultisstoredintheAccumulatorandthecontentsoftheDataMemoryremain unchanged.Operation ACC.(i+1)←[m].i;(i=0~6) ACC.0←[m].7Affectedflag(s) None
RLC [m] RotateDataMemoryleftthroughCarryDescription ThecontentsofthespecifiedDataMemoryandthecarryflagarerotatedleftby1bit.Bit7 replacestheCarrybitandtheoriginalcarryflagisrotatedintobit0.Operation [m].(i+1)←[m].i;(i=0~6) [m].0←C C←[m].7Affectedflag(s) C
RLCA [m] RotateDataMemoryleftthroughCarrywithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedleftby1bit.Bit7replacesthe Carrybitandtheoriginalcarryflagisrotatedintothebit0.Therotatedresultisstoredinthe AccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC.(i+1)←[m].i;(i=0~6) ACC.0←C C←[m].7Affectedflag(s) C
RR [m] RotateDataMemoryrightDescription ThecontentsofthespecifiedDataMemoryarerotatedrightby1bitwithbit0rotatedintobit7.Operation [m].i←[m].(i+1);(i=0~6) [m].7←[m].0Affectedflag(s) None
Rev. 1.00 104 st 1 01 Rev. 1.00 105 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
RRA [m] RotateDataMemoryrightwithresultinACCDescription DatainthespecifiedDataMemoryisrotatedrightby1bitwithbit0rotatedintobit7. TherotatedresultisstoredintheAccumulatorandthecontentsoftheDataMemoryremain unchanged.Operation ACC.i←[m].(i+1);(i=0~6) ACC.7←[m].0Affectedflag(s) None
RRC [m] RotateDataMemoryrightthroughCarryDescription ThecontentsofthespecifiedDataMemoryandthecarryflagarerotatedrightby1bit.Bit0 replacestheCarrybitandtheoriginalcarryflagisrotatedintobit7.Operation [m].i←[m].(i+1);(i=0~6) [m].7←C C←[m].0Affectedflag(s) C
RRCA [m] RotateDataMemoryrightthroughCarrywithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedrightby1bit.Bit0replaces theCarrybitandtheoriginalcarryflagisrotatedintobit7.Therotatedresultisstoredinthe AccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC.i←[m].(i+1);(i=0~6) ACC.7←C C←[m].0Affectedflag(s) C
SBC A,[m] SubtractDataMemoryfromACCwithCarryDescription ThecontentsofthespecifiedDataMemoryandthecomplementofthecarryflagare subtractedfromtheAccumulator.TheresultisstoredintheAccumulator.Notethatifthe resultofsubtractionisnegative,theCflagwillbeclearedto0,otherwiseiftheresultis positiveorzero,theCflagwillbesetto1.Operation ACC←ACC−[m]−CAffectedflag(s) OV,Z,AC,C
SBCM A,[m] SubtractDataMemoryfromACCwithCarryandresultinDataMemoryDescription ThecontentsofthespecifiedDataMemoryandthecomplementofthecarryflagare subtractedfromtheAccumulator.TheresultisstoredintheDataMemory.Notethatifthe resultofsubtractionisnegative,theCflagwillbeclearedto0,otherwiseiftheresultis positiveorzero,theCflagwillbesetto1.Operation [m]←ACC−[m]−CAffectedflag(s) OV,Z,AC,C
SDZ [m] SkipifdecrementDataMemoryis0Description ThecontentsofthespecifiedDataMemoryarefirstdecrementedby1.Iftheresultis0the followinginstructionisskipped.Asthisrequirestheinsertionofadummyinstructionwhile thenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogram proceedswiththefollowinginstruction.Operation [m]←[m]−1 Skipif[m]=0Affectedflag(s) None
Rev. 1.00 106 st 1 01 Rev. 1.00 10 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
SDZA [m] SkipifdecrementDataMemoryiszerowithresultinACCDescription ThecontentsofthespecifiedDataMemoryarefirstdecrementedby1.Iftheresultis0,the followinginstructionisskipped.TheresultisstoredintheAccumulatorbutthespecified DataMemorycontentsremainunchanged.Asthisrequirestheinsertionofadummy instructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0, theprogramproceedswiththefollowinginstruction.Operation ACC←[m]−1 SkipifACC=0Affectedflag(s) None
SET [m] SetDataMemoryDescription EachbitofthespecifiedDataMemoryissetto1.Operation [m]←FFHAffectedflag(s) None
SET [m].i SetbitofDataMemoryDescription BitiofthespecifiedDataMemoryissetto1.Operation [m].i←1Affectedflag(s) None
SIZ [m] SkipifincrementDataMemoryis0Description ThecontentsofthespecifiedDataMemoryarefirstincrementedby1.Iftheresultis0,the followinginstructionisskipped.Asthisrequirestheinsertionofadummyinstructionwhile thenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogram proceedswiththefollowinginstruction.Operation [m]←[m]+1 Skipif[m]=0Affectedflag(s) None
SIZA [m] SkipifincrementDataMemoryiszerowithresultinACCDescription ThecontentsofthespecifiedDataMemoryarefirstincrementedby1.Iftheresultis0,the followinginstructionisskipped.TheresultisstoredintheAccumulatorbutthespecified DataMemorycontentsremainunchanged.Asthisrequirestheinsertionofadummy instructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot 0theprogramproceedswiththefollowinginstruction.Operation ACC←[m]+1 SkipifACC=0Affectedflag(s) None
SNZ [m].i SkipifbitiofDataMemoryisnot0Description IfbitiofthespecifiedDataMemoryisnot0,thefollowinginstructionisskipped.Asthis requirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwo cycleinstruction.Iftheresultis0theprogramproceedswiththefollowinginstruction.Operation Skipif[m].i≠0Affectedflag(s) None
SUB A,[m] SubtractDataMemoryfromACCDescription ThespecifiedDataMemoryissubtractedfromthecontentsoftheAccumulator.Theresultis storedintheAccumulator.Notethatiftheresultofsubtractionisnegative,theCflagwillbe clearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation ACC←ACC−[m]Affectedflag(s) OV,Z,AC,C
Rev. 1.00 106 st 1 01 Rev. 1.00 10 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
SUBM A,[m] SubtractDataMemoryfromACCwithresultinDataMemoryDescription ThespecifiedDataMemoryissubtractedfromthecontentsoftheAccumulator.Theresultis storedintheDataMemory.Notethatiftheresultofsubtractionisnegative,theCflagwillbe clearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation [m]←ACC−[m]Affectedflag(s) OV,Z,AC,C
SUB A,x SubtractimmediatedatafromACCDescription TheimmediatedataspecifiedbythecodeissubtractedfromthecontentsoftheAccumulator. TheresultisstoredintheAccumulator.Notethatiftheresultofsubtractionisnegative,theC flagwillbeclearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation ACC←ACC−xAffectedflag(s) OV,Z,AC,C
SWAP [m] SwapnibblesofDataMemoryDescription Thelow-orderandhigh-ordernibblesofthespecifiedDataMemoryareinterchanged.Operation [m].3~[m].0↔[m].7~[m].4Affectedflag(s) None
SWAPA [m] SwapnibblesofDataMemorywithresultinACCDescription Thelow-orderandhigh-ordernibblesofthespecifiedDataMemoryareinterchanged.The resultisstoredintheAccumulator.ThecontentsoftheDataMemoryremainunchanged.Operation ACC.3~ACC.0←[m].7~[m].4 ACC.7~ACC.4←[m].3~[m].0Affectedflag(s) None
SZ [m] SkipifDataMemoryis0Description IfthecontentsofthespecifiedDataMemoryis0,thefollowinginstructionisskipped.Asthis requirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwo cycleinstruction.Iftheresultisnot0theprogramproceedswiththefollowinginstruction.Operation Skipif[m]=0Affectedflag(s) None
SZA [m] SkipifDataMemoryis0withdatamovementtoACCDescription ThecontentsofthespecifiedDataMemoryarecopiedtotheAccumulator.Ifthevalueiszero, thefollowinginstructionisskipped.Asthisrequirestheinsertionofadummyinstruction whilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0the programproceedswiththefollowinginstruction.Operation ACC←[m] Skipif[m]=0Affectedflag(s) None
SZ [m].i SkipifbitiofDataMemoryis0Description IfbitiofthespecifiedDataMemoryis0,thefollowinginstructionisskipped.Asthisrequires theinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwocycle instruction.Iftheresultisnot0,theprogramproceedswiththefollowinginstruction.Operation Skipif[m].i=0Affectedflag(s) None
Rev. 1.00 108 st 1 01 Rev. 1.00 109 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
TABRD [m] Readtable(specificpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(specificpage)addressedbythetablepointerpair (TBHPandTBLP)ismovedtothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None
TABRDC [m] Readtable(currentpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(currentpage)addressedbythetablepointer(TBLP)is movedtothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None
TABRDL [m] Readtable(lastpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(lastpage)addressedbythetablepointer(TBLP)ismoved tothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None
XOR A,[m] LogicalXORDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwiselogicalXOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″XOR″[m]Affectedflag(s) Z
XORM A,[m] LogicalXORACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalXOR operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″XOR″[m]Affectedflag(s) Z
XOR A,x LogicalXORimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalXOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″XOR″xAffectedflag(s) Z
Rev. 1.00 108 st 1 01 Rev. 1.00 109 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Package Information
Note that thepackage informationprovidedhere is for consultationpurposesonly.As thisinformationmaybeupdatedatregularintervalsusersareremindedtoconsulttheHoltekwebsiteforthelatestversionofthePackage/CartonInformation.
Additionalsupplementaryinformationwithregardtopackagingislistedbelow.Clickontherelevantsectiontobetransferredtotherelevantwebsitepage.
• FurtherPackageInformation(includeOutlineDimensions,ProductTapeandReelSpecifications)
• PackingMeterialsInformation
• Cartoninformation
Rev. 1.00 110 st 1 01 Rev. 1.00 111 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
16-pin NSOP (150mil) Outline Dimensions
SymbolDimensions in inch
Min. Nom. Max. — 0.36 BSC —
B — 0.154 BSC —
C 0.01 — 0.00C’ — 0.390 BSC —D — — 0.069E — 0.050 BSC —F 0.004 — 0.010G 0.016 — 0.050H 0.004 — 0.010α 0° — 8°
SymbolDimensions in mm
Min. Nom. Max. — 6 BSC —B — 3.9 BSC —C 0.31 — 0.51C’ — 9.9 BSC —D — — 1.5E — 1. BSC —F 0.10 — 0.5G 0.40 — 1.H 0.10 — 0.5α 0° — 8°
Rev. 1.00 110 st 1 01 Rev. 1.00 111 st 1 01
BA45F0082Fire Protection Flash MCU
BA45F0082Fire Protection Flash MCU
Copyriht© 01 by HOLTEK SEMICONDUCTOR INC.
The information appearin in this Data Sheet is believed to be accrate at the time of pblication. However Holtek assmes no responsibility arisin from the se of the specifications described. The applications mentioned herein are used solely for the prpose of illstration and Holtek makes no warranty or representation that sch applications will be sitable withot frther modification nor recommends the se of its prodcts for application that may present a risk to hman life de to malfnction or otherwise. Holtek's prodcts are not athorized for se as critical components in life spport devices or systems. Holtek reserves the riht to alter its products without prior notification. For the most up-to-date information, please visit or web site at http://www.holtek.com/en/.