Vaasa University

TehoFPGA20th Nov 2013Matti Tommiska, Altera

AgendaAgenda

Altera University Program Altera Industrial Market Solutions

Industrial Networking Functional Safety HSR/PRP

Altera University ProgramAltera University Program

http://www.altera.com/education/univ/unv-index.html Provides complete support for introducing students to

digital technology Hardware

Development and Education boards (DE0, DE1, DE2-115, and DE4) Software

Quartus II Nios II soft processor Simulation tools

Teaching materials Tutorials Laboratory exercises

university@altera.com

Example DE board, DE2-115Example DE board, DE2-115

http://www.altera.com/education/univ/materials/boards/de2-115/unv-de2-115-board.html

Designed by professors, for professors Academic price $299

Altera and Industrial SolutionsAltera and Industrial Solutions

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Industrial Networking

Functional Safety

Qsys

SoC EDK, DS5

C(ARM)

HDL

C-based Design Entry Model-based Design Entry

C(ARM)

HDL

Design Flow and Tools

Development KitsReference Designs

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Commitment To Long Industrial Life CyclesCommitment To Long Industrial Life Cycles

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R&D 2 – 4 years

Military, Industrial, Automotive,

Computer, Medical Active

5 – 10 years

Alignment to application lifecycle dynamics

Phase Out 1- 3 years

Obsolete

ASSP5 years (typical)

Low Prices, Consumer Driven

MCU7- 10 years (typical)

Low Prices, Embedded Driven

Altera PLD15+ years (typical)

ASIC10 years (typical)

High NRE, 100% Application Specific

t = 0

Long life,Lower cost of ownership, Off-the-shelf, Wide MIC customer base

Altera’s PCN procedure meets or exceeds industry standards (JEDEC, ISO-9000, etc.)

Key Industrial Ethernet Implementation TrendsKey Industrial Ethernet Implementation Trends

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…Modules Discrete Device Integrated Function…

Flexibility to support any one of multiple protocols

Altera Industrial Ethernet OfferingAltera Industrial Ethernet Offering

Simplified, no-hassle implementation for most of the popular Industrial Ethernet protocols + Profibus

Hardware tested protocols – HW IP & SW protocol stack

NO upfront license fee Royalty embedded in the security

CPLD Uniform software API and HW I/F

Profinet RT Profinet IRT EtherCATEthernet POWERLINKEthernet/IP (soft DLR)ModBus/TCPProfibus DPEthernet/IP (hard DLR)

Profinet RT Profinet IRT EtherCATEthernet POWERLINKEthernet/IP (soft DLR)ModBus/TCPProfibus DPEthernet/IP (hard DLR)

Functional Safety with Altera

Value Proposition

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Functional Safety Trends, ChallengesFunctional Safety Trends, Challenges

Legislation forces the machinery market into certification Providing safety certified automation components is mandatory for industrial

companies in EU/NA/JP (2012)

Time to market Functional Safety development process increases TTM by 18 - 24 months

Development and material costs Functional Safety increases development & material costs significantly Machine builders will not pay a significant premium over long term Quality and project management required

Productivity 24/7 operation - cost of maintenance down time (time to recovery)

Functional Safety Assessors (TÜV, UL, Exida) Experience and uncertainty of cooperating with independent certification bodies

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Functional SafetyValue Proposition of Altera FPGAsFunctional SafetyValue Proposition of Altera FPGAs

Reduce Cost of Functional Safety Designs Fewer components, lower obsolescence risk Combine FS with application + Networking enables lower cost designs

Reduces development time by as much as 2 years Safety Data Package lowers hurdles to start with FS designs

Significantly reduces TÜV interaction and certification risks

Reduce obsolescence risk by replacing ASICs/ASSPs and microcontrollers

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Altera Deliverables for Functional SafetyAltera Deliverables for Functional Safety

TÜV-Qualified Safety Data Package: Safety Manuals

FPGA Device All devices fully supported by Quartus version below will be qualified for use

based upon currently available FIT rates and SEU data Toolflow

QuartusII v11.0 SP1 and QuartusII v9.0 SP2- TÜV qualified Standard IP

Altera IP available in QuartusII will be qualified Include NIOSII and SOPC Builder

Altera Safety Manuals will contain a TÜV qualification approval document

Diagnostic IP Diagnostic IP blocks will be developed in accordance with IEC 61508

SIL3 CRC Check, SEU Check, Derived Clock Checker

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Reduces Development TimeReduces Development Time

Safe Requirement Specification

Qualification of Used Devices

and Tools

Implementation of Safe

Functionality

Certification by TÜV

Development Without “TUV-Qualified Safety Package”

Safe Requirement Specification

Certification by TÜV

Development with “TUV-Qualified Safety Package”

Development ofApplication-Specific

Hardware and/or Software

Development of Application-Specific

Hardware and/or Software

Implementation of Safe Diagnostic

Functions

Altera’s TÜV-Qualified Functional Safety Data PackageAltera’s TÜV-Qualified Functional Safety Data Package

Altera Functional Safety Value

Altera tools and IP are sufficiently free of systematic errors

The Altera Functional Safety Data Packagesaves 18-24 months in certifying

a safe application

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Announcement – February 25, 2013 @ Embedded WorldAnnouncement – February 25, 2013 @ Embedded World

Altera announced a High-availability Seamless Redundancy (HSR) and Parallel Redundancy Protocol (PRP) reference design targeting smart grid substation automation equipment.

The solution strives to improve system efficiency, reliability, economics, and sustainability to meet electric service needs

The IEC 62439-3-compliant reference design includes Flexibilis Redundant Switch (FRS) IP implemented on a low-power, low-cost Cyclone class FPGA or Cyclone V SoC

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Flexibility Evolving with standards

PRP/HSR with IEEE 1588 Add/change I/O interfaces

Integration PRP/HSR GbE switch with

monitoring/control functions Reliability with fewer components

Performance Hardwired real-time detection PRP/HSR Gbps Ethernet switch traffic

over microcontroller unit/DSP capabilities

FPGAs For PRP/HSR High-Availability NetworksFPGAs For PRP/HSR High-Availability Networks

Total Cost of Ownership Integration, device longevity to

lower total cost Hassle-free business model

No up-front non-recurring fees Reduce development risk Time to market

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Example: Protection relay IED with PRP/HSR module

PRP/HSR Reference DesignPRP/HSR Reference Design

Target markets: Substation & utility automation, factory automation Flexibilis Redundant Switch (FRS) IP for mission-critical systems Support for Cyclone IV and V FPGAs, and Cyclone V SoCs Demo shows 4-port FRS on CIV, CV, and CV SoC platforms

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From PRP/HSR on Cyclone ® IV or V Integrated SoC

• Scalable 3-8 port PRP/HSR Gigabit Ethernet switch • Ethernet Layer 2 switch compatible with IEC

62439-3 PRP and HSR standards• Compatible with IEEE 1588 PTP transparent clock

• Scalable 3-8 port PRP/HSR Gigabit Ethernet switch • Ethernet Layer 2 switch compatible with IEC

62439-3 PRP and HSR standards• Compatible with IEEE 1588 PTP transparent clock

SecurityCPLD

Thank YouThank You