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Final Exam Review

CSE 241B.Ramamurthy

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Place and Time

Date: 12/11/2013 Time: 8.00 – 11.00 AMPlace: Cooke 121Please bring Pencils, pens and erasers.

Closed book exam

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Topics • Chapter 4: HDL Models of combinational

circuit: Gate level modeling and behavioral modeling: 164-181

• Chapter 5: Sequential circuit analysis: pages 201-217

• Chapter 5: Synthesizable HDL models of sequential circuits: pages 217-220, p.229-231

• Chapter 5: Sequential circuit design: p.236-p.245

• All the homework problems

How do I study? Help!

Writing a test bench: pages 176-181, read every line of these pages, and understand Example 4.10 on p.181From state diagram to Verilog HDL simulation: see example on p.229, only state diagram based model and ONLY its test bench on the next page (p.230)Analysis example: see figure 5.18, table 5.4, up to figure 5.19 on p.214Design example; p.238-241: figure 5.27, table 5.11, figure 5.28, figure 5.29Counter design: figure 5.32, table 5.14, figure 5.33, figure 5.34

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Format & possible questions

• Sequential circuit analysis• Sequential circuit design• Counter design• Verilog HDL verification (means test

bench included) of combinational circuits

• Verilog HDL verification of sequential circuits

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Remember…Learn from the home works assignedFind ways to efficiently answer questionsFind ways to not make silly mistakesCreate a mental checklist to make sure you have not missed anything important on the exam (like your name of the exam paper!)Read the question paper and strategize on the order in which you will answer the questionsCome prepared: there is no substitute for hard workBuild up competencies and not deficiencies…Good luck.

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