Ipsita Praharaj, Shalaka GhawateAdvisor: Dr. David
ParentDate:05/11/04
AgendaAbstractIntroduction - why - Simple Theory -
BackgroundSummary of resultsProject DetailsCost
AnalysisConclusions
AbstractGoal is to design a 4-bit ALU driving upto 30fF that can
perform the following operations -FULL ADDER -AND -OR -NOR
IntroductionALU is a building block of several
circuits.Understanding how an ALU is designed and how it works is
essential to building any advanced logic circuits.Using this
knowledge and experience, we can move on to designing more complex
integrated circuits.Design consists of different kind of
logicRipple carry adder, full adder, AND, OR, NOR, DFF, MUX.
Block diagram of 4 bit ALU
Project Details-There are total of 19 pin outs in our design.
including VDD and GND. -There are 9 D flip-flops at the input and 4
at the output. -There is a 4:1 MUX to select the output. -Create
schematics and layouts for adder, AND, OR, MUX, in the cadence
tool. -Test the schematic using test bench. -Create schematic and
layout for 1 bit ALU now using the schematics for the basic logical
units. -Test the schematic for 1 bit ALU.-Create the single bit ALU
to create a 4 bit ALU layout.-Run DRC extracted and LVS check to
verify the design.
DFFDFF are placed on either side of the combinational logic.Hold
time= 0.586n(Fall) =0.515n(Rise)Setup time=0.521n(Fall)
=0.450n(Rise)
Long path calculations
Full Adder Schematic
Full Adder Layout
Full Adder LVS Report
2-to-1 MUX schematic
4-to-1 MUX layout
4-bit ALU schematic
4-bit ALU layout
4 bit ALU(LVS Report)
DFF schematic
DFF layout
DFF LVS report
4 bit ALU with DFF schematic
4 bit ALU with DFF layout
4 bit ALU with DFF LVS report
Transient Analysis
Worst case (Tphl)
Worst case (Tplh)
Post extraction simulation
ResultsThe ALU performs all 4 functions at a 200Mhz clock and a
load of 30fF.We meet the power specifications.Area of the our
layout=192micron*375micron.
Cost AnalysisTime spent on each phase of the project. - Logic
design 1 week. - Logic check 1 week -Individual schematic 5 days -
Integration of schematic blocks 1 week - Layouts 2 weeks - Post
extraction check 2 days
AcknowledgementsThanks to Cadence Design systems for the VLSI
labsThanks to Professor David Parent for his guidance.
