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Coursework Brief for the module VLSI Technology, 2015-2016

Electrical Engineering Department, Faculty of Engineering, BUE

Module Leader: Dr Hassan Mostafa

1. Module details

i. The programme title: Electronics and Communications Engineering

ii. Module code: 15ELEC17H

iii. Module title: VLSI Technology

iv. Module length: S1 (12 weeks)

v. Academic Year: 20152016

vi. Coursework Components (weights): Mini-project using Mentor Graphics or alternative

CAD tool (30%) + In-Class Test (10%)

2. Mini-project

i. Mini-Project total weight : 30% of total mark.

ii. Mini-Project Form: The project target is to simulate and layout a 16-bit multiplier using the

techniques learned throughout the course. The project covers design flow and different layout

techniques such as:

1- Design Simulation 2- Technology Files 3- Gates Layout 4- Floor Planning 5- Standard Cells 6- DRC 7- Layout vs. Schematic 8- Post Layout simulations

iii. Group/Individual Assignment: Group; 2-3 students perform the required project tasks. iv. Questions: Technical report as will as group presentation should be delivered.

v. Assignment Marking Criteria: Technical Report with the following:

1. Design Entry [10 marks] 2. Layout [20 marks] 3. Simulation [10 marks] 4. DRC [10 marks] 5. Layout vs. Schematic [10 marks] 6. Post Layout Simulation [10 marks]

In addition to group presentation and discussion [30 marks] The presentation time will be 15 minutes and will be assessed based on the following: 1. Design completeness [15 marks] 2. Design novelty [5 marks] 3. Design performance [5 marks] 4. Presentation skills [5 marks] Total [100 marks]

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vi. Word Limit : The technical report is limited to 6 pages in IEEE double column PDF format.

vii. Submission Mode, Assessment Form, Marks Announcement, and Feedback:

- On the deadline, students submit their technical reports on a working CD/DVD, and

- Then they perform a group presentation to go through their project design. The

presentation is typically within 2-4 days from the deadline of the technical report

submission.

- Marks will be announced within one week from the presentation assessment, and

- Feedback will be given in the forms specified in the Module Specs right after the marks

announcement. Some feedback may also be given straight after the presentation.

viii. Deadline: The submission date is at week 11. No submission will be accepted after the

group presentation date (unless university regulations allow otherwise, in special

circumstances) and the students will receive zero marks in the mini-project.

ix. Regulations, Plagiarism, and Collusion: All assessed work must conform to BUEs Exam

and Assessment Regulations. Any student suspected of plagiarism, or collusion, will be

subject to the procedures set out in the GAR.

x. Other notes: Turnitin submission not necessary, but Turnitin may be used on the discretion

of the examiner if deemed necessary.

3. In class tests:

xi. How many? ONE in-class test.

xii. In-Class Tests total weight: 10% of total mark.

xiii. Test Form: Questions will be given in a tutorial session to assess students in the materials given up to the point of assessment.

xiv. Group/Individual Assignment: Individual; each student writes his/her own answers. xv. Questions: The questions of the test will span the course contents covered in class up to

the week before the test. See model questions and answers, with full mark distribution in the pages attached below.

xvi. Assignment Marking Criteria: See marks distribution in the model answer provided. xvii. Word limit: Not applicable.

xviii. Submission Mode, Assessment Form, Marks Announcement, and Feedback:

- On the announced date of test, students take the in-class test during a tutorial session,

- Usually marks will be announced within one week from the tests date, and

- Feedback will be given in the forms specified in the Module Specs right after grades

announcement.

xix. Deadline and Penalties: The test will be in weeks 7. Not sitting the test will result in zero

marks in that test (unless university regulations allow, in special circumstances, to re-take

the test using special arrangements).

xx. Regulations, Plagiarism, and Collusion: All assessed work must conform to BUEs Exam

and Assessment Regulations. Any student suspected of plagiarism, or collusion, will be

subject to the procedures set out in the GAR.

xxi. Other notes: Turnitin submission not applicable.

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Module Code: 15ELEC05H

Module Title: VLSI Technology Module Leader: Dr. Hassan Mostafa

Semester : ONE Total mark : 100

Instructions:

1. Answer all questions.

2. The exam consists of 2 questions in 3 pages including this cover page.

3. A formula sheet is attached at end of this booklet.

4. The exam allowed time is ONE hour.

5. Electronic calculators are allowed.

6. Clearly show all steps used in your solutions.

7. The allocation of marks is shown in brackets next to each question. 8. This is a closed book exam.

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Q1. Given the following logic expression, answer the following questions:

= (A.B) + (A.C.E) + (D.E) + (D.C.B)

Hint: Calculate the delays in terms of the equivalent inverter resistances RN and RP and the output node capacitance CL.

Q2. A CMOS inverter has the following device parameters:

NMOS: VTn = 0.5 V, Kn = 115A/V2, and (W/L)n = 2

PMOS: VTp = -0.6V, Kp = -30A/V2, and (W/L)p= 4

The power supply voltage is VDD=2.5V, and the output load capacitance is 0.5pF. Assuming that the CMOS inverter is

implemented with long channel devices and the channel modulation is neglected.

I. Implement the above logic expression using static CMOS logic. [6 marks]

II. How many transistors have you used in your design? [2 marks]

III. Size the NMOS and PMOS devices such that the output resistance is the

same as that of an inverter with an NMOS W/L = 1 and PMOS W/L =2 . [6 marks]

IV. What are the input patterns that results in the worst case LOW-to-HIGH

and HIGH-to-LOW propagation delay times? [8 marks]

V. Calculate the worst case LOW-to-HIGH and HIGH-to-LOW propagation

delay times. [8 marks]

VI. Draw a stick diagram for the above CMOS transistor network and

estimate the layout area. [10 marks]

VII. Implement the above logic expression using only 10 transistors. [10 marks]

[Total 50]

I. Calculate the low-to-high and high-to-low delay times of the output signal. [12 marks]

II. Determine the maximum frequency of the output signal. [4 marks]

III. Calculate the static power and the dynamic power dissipation at this

maximum frequency. Neglect any diffusion capacitances. [6 marks]

IV. Assume that the output load capacitance is mainly dominated by fixed

fan-out components (i.e., independent of the inverter sizing). We want to

redesign the inverter so that the propagation delay times are reduced by

25%. Determine the required channel dimensions of the NMOS and

PMOS transistors.

[8 marks]

V. How does this re-design influence the static power dissipation and the

dynamic power dissipation? [6 marks]

VI. Which of the two designs produces lower power-delay-product? [4 marks]

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Formula sheet:

-------------------You may make use of the following formulas--------------------

MOSFET UNIFIED MODEL:

50% propagation delay = 0.69 RC

RN = (kn*W/L*(VGS-Vt))-1

VII. How does this redesign influence the switching threshold of the CMOS

inverter? [4 marks]

VIII. If the supply voltage is to be reduced to achieve the requirement of part

IV. above while keeping the NMOS and PMOS transistors sizes, calculate

the new VDD value.

[6 marks]

[Total 50]

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