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a. w. 1. f. b. w. 2. w. d. 3. c. (a). Circuit. Fault. detected. Test. w. w. w. a /0. a /1. b /0. b /1. c /0. c /1. d /0. d /1. f. /0. f. /1. 1. 2. 3. 000. . . . 001. . . . . 010. . . . . 011. . . . . 100. . . 101. . . - PowerPoint PPT Presentation
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Figure 11.1 Fault detection in a simple circuit
(a) Circuit
Test Fault detected
w 1 w 2 w 3 a/0 a/1 b/0 b/1 c/0 c/1 d/0 d/1 f /0 f /1
000
001
010
011
100
101
110
111
(b) Faults detected by the various input valuations
f
a
b
c d
w 1
w 2
w 3
Figure 11.2 A sensitized path
f
a b
c
w 1
w 2 1 =
w 3 0 =
w 4 1 =
Figure 11.3 Circuit for Example 11.1
fb
c
d
w1
w2
w3
w4
Figure 11.5 Circuit with a tree structure
f
w 1
w 3
w 4
w 2
w 3
w 4
w 1
w 2
w 3
Figure 11.6 Derivation of tests for the circuit in Figure 11.5
Product term TestNo. w 1 w 3 w 4 w 2 w 3 w 4 w 1 w 2 w 3 w 1 w 2 w 3 w 4
1 1 1 1 0 1 0 0 0 0 1 0 0 0 Stuck-at-0 2 0 1 0 1 1 1 1 1 0 0 1 0 1
tests 3 0 0 0 1 0 1 1 1 1 0 1 1 1
4 0 1 1 1 1 0 1 1 0 0 1 0 0
5 1 0 1 1 0 0 0 1 1 1 1 1 0 Stuck-at-1 6 1 1 0 0 1 1 0 0 0 1 0 0 1
tests 7 1 0 0 1 0 1 0 1 1 1 1 1 1
8 0 0 0 0 0 1 1 0 1 0 0 1 1
Figure 11.7 All two-variable functions
w 1 w 2 f 0 f 1 f 2 f 3 f 4 f 5 f 6 f 7 f 8 f 9 f 10 f 11 f 12 f 13 f 14 f 15
00 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
01 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
10 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
11 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Figure 11.8 The XOR circuit
w 1
w 2
d b
c
h
k
f
Figure 11.9 The effect of various faults
Fault Circuit implements
b/0 f 5 = w 2
b/1 f 10 = w 2
c/0 f 3 = w 1
c/1 f 12 = w 1
d/0 f 0 = 0
d/1 f 7 = w 1 + w 2
h/0 f 15 = 1
h/1 f 4 = w 1 w 2
k/0 f 15 = 1
k/1 f 2 = w 1 w 2
Figure 11.10 Effectiveness of random testing
Percentfaults
detected
Number of tests
Figure 11.13 The testing arrangement
x 0
Testvector
generator
Circuit under test
Testresult
compressor
Signature
x n 1 –
p 0
p m 1 –
Figure 11.14 Pseudorandom binary sequence generator (PSRG)
x 3 1 1 1 1 0 1 0 1 1 0 0 1 0 0 0 1 ···
x 2 0 1 1 1 1 0 1 0 1 1 0 0 1 0 0 0 ···
x 1 0 0 1 1 1 1 0 1 0 1 1 0 0 1 0 0 ···
x 0 0 0 0 1 1 1 1 0 1 0 1 1 0 0 1 0 ···
f 1 1 1 0 1 0 1 1 0 0 1 0 0 0 1 1 ···
(b) Generated sequence
(a) Circuit
x 3 x 2 x 1 x 0
Clock
f
PRBS
D Q
Q
D Q
Q
D Q
Q
D Q
Q
Figure 11.15 Single-input compressor circuit
p
Clock
Signature
D Q
Q
D Q
Q
D Q
Q
D Q
Q
Figure 11.16 Multiple-input compressor circuit (MIC)
Clock
Signature
p 3 p 2 p 1 p 0
D Q
Q
D Q
Q
D Q
Q
D Q
Q
Figure 11.17 BIST in a sequential circuit
Combinational circuit
W
Flip-flopsand
multiplexers
SIC
MIC
X
0
1
Normal Test
y Y
Z-signature
Y-signature
Scan-out
Scan-in
Z
PRBSG-X
PRBSG-y
Figure 11.19 Using BILBO circuits for testing
Combinational network
Scan-out
Scan-in
CN1
Combinational network
CN2 BIL
BO
1
BIL
BO
2
Figure P11.1 Circuit for problem 11.1
w 1
w 2
f w 3
Figure P11.2 Circuit for problem 11.2
w1
w2
fw3
w4
Figure P11.3 Circuit for problem 11.3
w 1 w 2
f w 3
w 4 w 5
Figure P11.4 Circuit for problem 11.4
w1
w2 f
w3
Figure P11.5 Circuit for problem 11.5
w 1
w 2
p
w 3
w 4
