Slide 1
FIFO Controller
Made by:Mikul Patel12116033Amit Kumar12116007Anil
Mor12116008Vijay Kumar12213020Pankaj Kakkad12213013
What is FIFO?First In First Out(FIFO)is a method of processing
data where the data first received is the first to be sent out
after processed.
For example
For booking a train ticket, the person entering first gets the
ticket first.Or, a person who FIRST gets IN the line, is the FIRST
to come OUTSimilarly in memory, FIFO controller is used to read and
write the data following the FIFO principle.
Problem statement:
FIFOs are used commonly in electronic circuits for buffering and
flow control which is from hardware to software. In hardware form a
FIFO primarily consists of a set of read and write pointers,
storage and control logic. Storage may be SRAM, flip-flops, latches
or any other suitable form of storage. For FIFOs of non-trivial
size a dual-port SRAM is usually used where one port is used for
writing and the other is used for reading.
In this project, you need to design a FIFO to store up to 1024
items of 32 bits each and a FIFO controller assuming that FIFO will
not be read when it is empty, not to be written when it is full.
Write and read port share a common bus.
FIFO Controller
32 bit input32 bit outputReadLet us first see what are the
inputs and outputs of a FIFO controller.WriteEmptyFull
FIFO Controller
1102432
32 bit parallel shift register1 2 3 4 32
D Flip-Flop
1 0 0 1 1INPUTOUTPUT32 bit parallel shift register
Let us see with an example, how the data will be read in and
written out from the controller.
For ease of understanding, consider a FIFO controller which
stores maximum 5 alphabets.
Input :
14235WRITEREADOutput :
FWRITE QQWRITE TTWRITE FREADFWRITE AWRITE MAMWRITE YYWRITE
ZOVERFLOWREADEMPTY
Write Controller
Write
2 Bit InputReadController2 Bit Output
ReadError DetectorEmptyFullOverview
DECODER(2X4)
Counter(2 Bit)
2 Bit InputWriteSimplified Circuit of Write Controller
Wire C
Read2 Bit Output
4x1MUXCounterSimplified Circuit of Read ControllerWire D
Up-DownCounter
ReadWriteEmptyOverflowSimplified Circuit of Error CheckerWire
CWire D
DECODER(2X4)
counter(2 Bit)
2 Bit InputWrite
counter4x1MUX2 Bit Output
Read
Up down counter
EmptyOverflowCircuit Diagram of FIFO Controller
For the proper functioning of Fifo Controller 2-bit input and
the clock reach the Register at the same time for the proper entry
of the data at the proper index.
In this design we have assumed that there is no input from the
processor as any of the empty or overflow error is detected.
LIMITATIONS
Components of VHDL fileCounter
VHDL Code:entity counter_4 isgeneric(n: natural
:=2);port(clock:in std_logic;clear:in std_logic;count:in
std_logic;Q:out std_logic_vector(n-1 downto 0));end
counter_4;-----------------------------------------------------------------architecture
counter_4_arch of counter_4 is signal Pre_Q: std_logic_vector(n-1
downto 0);begin -- behavior describe the counterprocess(clock,
count, clear)beginif clear = '1' thenPre_Qreg2_output); reg3:
register_2bit port
map(I=>input1,clock=>clk,load=>write_decoder_output(3),clear=>'1',
Q=>reg3_output);
read_counter: counter_4 port map(clock=>clk, clear=>'1',
count=> read2,Q=>read_counter_output); read_mux: mux_4x1 port
map( I3=>reg3_output
,I2=>reg2_output,I1=>reg1_output,I0=>reg0_output,S=>read_counter_output,O=>output1);
total_counter: up_down_counter port map(clk=>clk, rst_a=>'0',
mode_r=>read1,
mode_w=>write1,q=>total_counter_output);
process(total_counter_output,read1,write1)beginempty
