February 19, 2015 IEEE EDS MQ, WIMNACT 45, Tokyo ...February 19, 2015 IEEE EDS MQ, WIMNACT 45, Tokyo Institute of Technology, Yokohama, Japan Hiroshi Iwai Frontier Research Center,

February 19, 2015IEEE EDS MQ, WIMNACT 45,Tokyo Institute of Technology, Yokohama, Japan

Hiroshi Iwai

Frontier Research Center, Tokyo Institute of Technology

Future of Electron Devices Technologies

1

1. Brief introduction of our research group in Tokyo Institute of Technology

Outline of my talk:

2. Innovations of logic device technology for past 60 years

3. Innovations of logic device technology for next 60 years

2 & 3 based on ESSDERC Tutorial & IEDM Panel, both in2014

ESSDERC Tutorial, September 22, 2014, Venice, Italy

60 Years of IEDM and Counting: Did we push silicon based devices for integrated electronics to the ultimate and what does the future hold?

IEDM Panel, December 18, 2014, San Francisco, USA

Moderator: Krishna Saraswat (Stanford University)

Panelist:Jesus del Alamo (MIT), Compound/PowerChenming Hu (University of California, Berkeley): Si DeviceHiroshi Iwai (Tokyo Institute of Technology):Process/DeviceYoshi Nishi (Stanford University):MemoryKurt Petersen (Co-founder of MEMS companies):MEMS/sensorPhilip Wong (Stanford University):Nano technology

1. Brief introduction of my research group in Tokyo Institute of Technology

Outline of my talk:




Tokyo Institute of Technology (東京工業大学）

Suzukakedai Campus （鈴懸台校庭）

Interdisciplinary Gradate School of Science and Engineering（大学院総合理工学研究科）

Department of Electronics and Applied Physics（物理電子系統創造専攻）

Frontier Research Center （先端研究機構）

Department of Electronics and Applied Physics（集積機能素子分野）

Research Project: Creation of Green Nanoelectronic Devices（環境保全極微電子素子創生事業）

Suzukakedai Campus

Interdisciplinary Gradate School of Science and Engineering

Frontier Research Center

Members of Iwai & Kakushima Laboratory November, 2014

SecretaryBachelorStudents

M. NishizawaA. Matsumoto

L. PuchengM. Okamoto X. H. Tan Y. Nakamura H. Hasegawa S. Munekiyo M. MotokiH. Imamura

Y. Lei J. Jin

T. Shoji

M. Yoon T. Ohashi T. Katou M. Sugiura H. Hori A. Miyawaki

K. Ohga K. MatsuuraT. Suzuki

T. Baba R. Fukui R. Miyazawa

Prof.K. Natori

Prof.H. Iwai

A. Prof.K. Kakushima

Prof.N. Sugii

Prof.K. Tsutsui

Prof.S. M. Sze

Prof.A. Nishiyama

Prof.Y. Kataoka

Prof.H. Wakabayashi

Prof.H. Ohashi

MasterStudents

Researcher

T. Kawanago

DoctorStudents

M. Koyama S. YamaguchiW. Li C. J. Ning A. SasakiH. Yabuhara

研究風景

9

Research Project: Creation of Green Nanoelectronic Devices（環境保全極微電子素子創生事業）

Information Technology

Renewable Energy

Power Saving Technology

Integrated Circuit Technology

Si nanowire-FET, High-k gate stack, silicide S/D

InGaAs/Ge-FET, T-FET, RRAM

CMOS Image sensor, Other sensor

Photovoltaic devices: Si-nanowire, BaSi/FeSi

Si-IGBT, GaN, SiC Power devices

Brain: Integrated Circuits

Hands, Legs：Power device

Stomach：PV device

Ear, Eye：Sensor

Mouth：RF/Opto device

Various semiconductor devicesBrain is very important

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Outline of my talk:




Lee De Forest

Electronics started by the invention of vacuum tube (Triode) in 1906

Cathode(heated) Grid

Anode(Positive bias)

Thermal electrons from cathodecontrolled by grid bias

Same mechanism as that of transistor

1947: 1st transistor W. Bratten,

W. ShockleyBipolar using Ge

However, they found amplification phenomenon when investigatingGe surface when putting needles.This is the 1st Transistor: Not Field Effect Transistor, But Bipolar Transistor (another mechanism)

J. Bardeen

14

1960: First MOSFET by D. Kahng and M. Atalla

Al

SiO2Si

Si/SiO2 Interface is extraordinarily good

Top View

Gate Oxd

ChannelSource Drain

Gate electrodeSurface

S D

G

Electron flow

15

1970,71: 1st generation of LSIs (Si-MOSFETs)1k bit DRAM Intel 1103 MPU Intel 4004

(Clock 750 KHz)

1970 Microelecrtonics started

16

2000 “Nano-Electronics” started.

Intel Pentium 4 : Clock 1 ~ 2 GHz

180 nm

17

Now, 2015 “Nano-Electronics” continued.

Device: Still, Si CMOS integrated circuitsDevice feature size: a few 10 nmMajor Appl.: Still Digital (µ-processor, cell phone, etc.)

Still evolution and innovation are going on.

Broadwell SoC (Intel)

http://download.intel.com/newsroom/kits/14nm/pdfs/Intel_14nm_New_uArch.pdf18

1900 1950 1960 1970 2000

VacuumTube

Transistor IC LSI VLSI

10 cm cm mm 10 µm 100 nm

In 100 years, the size reduced by ten million times.There have been many devices from stone age.We have never experienced such a tremendous reduction of devices in human history.

10-1m 10-2m 10-3m 10-5m 10-7m

Downsizing of the components has been the driving force for circuit evolution

2014

VLSI

14 nm

10-8m

19

What is the innovations in the past 60 years.

That is from the beginning of IEDM

IEDM:International Electron Devices Meeting60 year history

1st IEDM, October 24-25, 1955 in Washington DC

10 sessions in total

1 general session

6 Vacuum tube sessions

3 Semiconductor sessions

“Semiconductor Devices” by J. A. Morton, Bell Labs.

“Thermionic Cathodes” by L. S. Nergaad, RCA Labs.

“Microwave Tubes” by L. M. Field, Huges Aircraft Co.

1954: 1st Si Bipolar Transistor by Bell Labs• 1st Commercial Si Bipolar Transistor by TI

1947: 1st Bipolar Transistor (Ge) by Bell Labs.

1952: Diffusion Process by Bell Labs1954: Photo lithography by Bell Labs

http://www.computerhistory.org/semiconductor/welcome.html

1955: Thermally grown SiO2 film by Bell Labs1950’s: Pure Si substrate by Czochralski method by TI 1950’s: Thin film deposition evaporation/sputtering/CVD

Innovations for semiconductor devices before the 1st IEDM (1955)

• But no MOSFETs nor IC.

• Most of Process techniques existed before the 1st IEDM

http://www.nobelprize.org/nobel_prizes/physics/laureates/2014/

The Nobel Prize in Physics in 2014

The Nobel Prize in Physics 2014 was awarded jointly to Isamu Akasaki, Hiroshi Amano and Shuji Nakamura "for the invention of efficient blue light-emitting diodes which has enabled bright and energy-saving white light sources".

Isamu Akasaki Hiroshi Amano Shuji Nakamura

So, what semiconductor materials are related to Nobel Prize?

Innovations recognized as Nobel Prize

What semiconductor materials are related to Nobel Prize?


1956 W. B. Shockley, J. Bardeen, W. S. Brattin, Ge bipolar transistor (Germanium)



1973 L. Esaki, I. GIaever, for tunneling effect, Ge-diode (Germanium)




2000 J. S. Kilby, for Integrated Circuits, Ge bipolar transistor (Germanium)





2000 Z. I. Alferov, H. Cromer, for Semiconductor Hetero-junction: (Compound)






2009 W. S. Boyle, G. Smith, for CCD device (Silicon)







2010 A. Geim, K. Novoselov, for 2D Graphene device (Carbon)














2014 I. Akasaki, H. Amano, S. Nakamura, for GaN Blue (Compound: GaN)









7 items

2014 I. Akasaki, H. Amano, S. Nakamura, for GaN Blue (Compound: GaN)


Germanium:3, Compound:2, Silicon:1, Carbon:1

Innovations for Process/Device Technologies for MOS LSIs

Innovations for Process/Device Technologies for MOS LSIs So many


1955 – 1960 BJT Bipolar IC, Ge Si1957: Selective diffusion into Si using SiO2 as a mask by Bell Labs.

1958: Integrated circuit for Ge bipolar transistors by TI.

1959: Planar technology for Si bipolar by Fairchild.

1960: Planar Integrated Circuit by Fairchild.

So many


1955 – 1960 BJT Bipolar IC, Ge Si1957: Selective diffusion into Si using SiO2 as a mask by Bell Labs.

1958: Integrated circuit for Ge bipolar transistors by TI.

1959: Planar technology for Si bipolar by Fairchild.

1st MOSFET by Bell Labs. (1960)1960 – 1970 MOSFET MOS IC

PMOS Technology with Al gate

Prevention of MOS instability by HCl cleaning and Phosphorus gettering by Fairchild & IBM(1964 -69)

Poly Si gate and self-align between gate and source/drain by Bell Labs and Fairchild (1967-68)

Idea of CMOS by Fairchild (1963)

1960: Planar Integrated Circuit by Fairchild.

MOS IC by RCA (1964)

CVD oxide film depositionLOCOS isolation by Philips

So many

1970 – 1980 LSI, PMOS NMOS, 10 um 3 um

Scaling scheme by IBM and Caltech prevention of SCE (1972)

Ik DRAM, 1k SRAM, microprocessor (Intel, etc.) in early 1970’

CAD Layout tool (Calma, Applicon) late 1970’s

E-gun Al evaporation film deposition

LPCVD for Poly-Si, SiO2, SiN

Ion Implantation for channel doping, isolation

Reflow (planarization) by PSG and BPSG: BPSG by Toshiba 1975

Proximity lithography and projection lithography; Projection by Perkin Elmer

Al-Si and Al-Si-Cu interconnects for prevention of Al-spike and electron migration

Plasma etching (Isotropic) for Poly Si and SiN; CED by Toshiba

LDD and gate sidewall formation for suppressing hot-carrier degradation by Bell Labs.

1980 – 1990 VLSI, NMOS CMOS, 3 um 0.5 umDry process;

Planarization by etch-back

TCAD SEDAN, Suprem, Pisces by Stanford

Circuit simulator, SPICE by UC Berkeley

RIE for anisotropic etching poly Si and contact hole

Ion implantation for S/D for shallow junction by Linttot

Stepper lithography by GCA-Mann

Plasma CVD for SiO2 and SiN

Arsenic Source/Drain for shallow junction

Polyside (WSi2/Poly Si) for gate electrode

Metal sputter

IG (Intrinsic gettering) wafer

Planarization by CMP

200 mm wader and related process equipment

1990 – 2000 0.25 0.1 umOxynitride gate insulator

Tunneling gate oxide by Toshiba Dual gate process n+-poly Si for NMOS, p+-poly Si for PMOS

Salicide with TiSi2 and CoSi2NiSi silicide by Toshiba (1991)

Ultra-shallow implantation for S/D

Channel engineering for Halo and pocket

SOI technologySOI wafer technology for smart-cutOPC for lithography resolution

Phase shift mask for lithography resolutionKrF excimer stepper, Victor Pol/Bell Lab. (1986)

Rapid Thermal Process by lamp heating

Trench IsolationCu interconnectsLow-k interlayer300 mm wafer

2000 – 2014 0.1um 30 ~ 20nm

High-k/matal gate stack by Intel

FinFET by Intel (idea, research AIST, Hitachi, UC Berkeley … 1980s, 1990s)

ArF Eximer scanner (1997)

Double/multiple patterning lithography for high resolution

Fully-depleted SOI by STmicroelectronics and IBM (idea, research NTT & others before)

Immersion lithography (2002, 2005)

Air-gap insulation for interconnectDouble/multiple patterning lithography for high resolution

Multi-core microprocessors

Then, what are 5 most important innovations in past 60 years?

Too many important innovations which are 1 ~ 2 for every year!

Conclusions!

5 most important innovations in past 60 years

1960 1st MOSFET operation; Si/SiO2 structure

1971 1st Microprosessor; >1k MOSFETs; 10 um PMOS Tech.

1955 1st IEDM; Already Si BJT, Already most of Process Technologies

2014 Multi-core processor; >1G Fin-FET; 30 ~ 20 nm CMOS Tech.






1. Planar BJT (or printing) technology IC technology






1. Planar BJT (or printing) technology IC technology2. Si MOSFET (Lateral Device) Suitable: planar (IC) process







3. Clean & passivation processes Electrical Stability of MOS

2. Si MOSFET (Lateral Device) Suitable: planar (IC) process








4. Miniaturization (Scaling) Moore’s law


Not only one, in fact, so many innovations for enabling miniaturization








4. Miniaturization (Scaling) Moore’s law


Not only one, in fact, so many innovations for enabling miniaturization

5. CMOS LSI Power saving


Outline of my talk:




• What would be a future innovations for next 60 years?

• I will present the most probable scenario by my own view.




• I am very sorry, if your research area is not included as the most probable candidate!



• Please not be disappointed in that case!






• Because, even the 5 most important innovations in the past were not recognized by Nobel Prize.





• Because, even the 5 most important innovations in the past were not recognized by Nobel Prize.

• You have even a higer a chance, because Nobel Prize will be given to those accomplished mission-impossible (like Akasaki & Amaya or Nakamura)!.

(1970) 10 μm 8 μm 6 μm 4 μm 3 μm 2 μm 1.2 μm

0.8 μm 0.5 μm 0.35 μm 0.25 μm 180 nm 130 nm

90 nm 65 nm 45 nm 32 nm (28 nm ) 22 nm(2012)

Feature Size / Technology Node

From 1970 to 2013 (Last year)

18 generationsLine width: 1/450

Area: 1/200,000

43 years 1 generation2.5 years

Line width: 1/1.43 = 0.70

Area: 1/2 = 0.5

14 nm (2014)

57

More Moore to More More Moore

65nm 45nm 32nm

Technology node

M. Bohr, pp.1, IEDM2011 (Intel)P. Packan, pp.659, IEDM2009 (Intel)C. Auth et al., pp.131, VLSI2012 (Intel)T. B. Hook, pp.115, IEDM2011 (IBM)S. Bangsaruntip et al., pp.297, IEDM2009 (IBM)

Lg 35nm Lg 30nm

Main stream(Fin,Tri, Nanowire)

22nm 14nm 10nm, 7nm, 5nm, 3.5nm

Alternative

Alternative (III-V/Ge) Channel FinFET

Emerging Devices

Tri-Gate

Now Future

Si channelSi

Others

(FDSOI)

Planar

Si is still main stream for future !! FD: Fully Depleted

58

High-k gate dielectrics

Continued research and development

SiO2 IL (Interfacial Layer) is used at Si interface to realize good mobility

Technology for direct contact of high-k and Si is necessary

Remote SiO2-IL scavengingHfO2 (IBM)

EOT=0.52 nm

Si

La-silicate

MG

Direct contact with La-silicate (Tokyo.Tech)

T. Ando, et al., p.423, IEDM2009, (IBM) T. Kawanago, et al., T-ED, vol. 59, no. 2, p. 269, 2012 (Tokyo Tech.)

K. Mistry, et al., p.247, IEDM 2007, (Intel)

TiN

HfO2

Si

SiO2EOT=0.9nmHfO2/SiO2(IBM)

T.C. Chen, et al., p.8, VLSI 2009, (IBM)

Hf-based oxides

45nmEOT:1nm

32nmEOT:0.95nm

22nmEOT:0.9nm

10nm, 7nm, 5nm, 3.5nm,

K. Kakushima, et al., p.8, IWDTF 2008, (Tokyo Tech.)

EOT=0.37nm EOT=0.40nm EOT=0.48nm

0.48 → 0.37nm Increase of Id at 30%

14nmEOT:0.?nm

59

http://download.intel.com/newsroom/kits/14nm/pdfs/Intel_14nm_New_uArch.pdf

Merit for downsizing to 14 nm (Intel case)

Merit for cost, power consumption, and performance

60

http://download.intel.com/newsroom/kits/14nm/pdfs/Intel_14nm_New_uArch.pdf

Interconnects

SRAM Cell

Intel 14nm Technology by Mark Bohr, August 11. 2014

61

Near term until 2025 (in 10 years)

?


Si-CMOS deep-miniaturization

Very difficult because of :

1. Subtheshlod leakage current increase.

2. Mobility degradation with deceasing EOT and tSi3. Problem for EUV lithography

4. C & R increase for interconnects

5. Variability, yield, reliability problem

Vg (V)1

0.3 V

0.5 V 1.0 V

Ion

Ioff

Id (A/µm)

10-7

10-5

10-11

10-9

Vd

Vth

0.15 V

0 0.5

Subthreshold leakage current

Electron EnergyBoltzmann statics

Exp (qV/kT)

Lg 1/2Vd, Vg 1/2Vth 1/2

Ioff 103 in this exampleHowever

Because of log-linear dependence64

0

50

100

150

200

250

300

0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

EOT (nm)

Mob

ility

(cm

2 /Vse

c)

at 1 MV/cm

Open : Hf-based oxidesSolid : La-silicate oxide

K. Uchida et al., pp.47, IEDM2002 (Toshiba)T. Kawanago, et al., (Tokyo Tech.) T-ED, 2012

T. Ando, et al., (IBM) IEDM 2009L.-Å. Ragnarsson, et al., (IMEC) Microelectron. Eng,. 2011.

2015 2017 2019 20252021 2023 20272013Year10 7 5 1.83.5 2.5 1.314Commercial name (nm)

6.1 5.1 4.3 2.53.6 3.0 2.07.4TSi (nm) 0.73 0.67 0.61 0.470.56 0.51 0.430.80EOT (nm)

ITRS 2013

tox tSiµ µ

65

µ(mobility) degradation

tSi Si

tSi

Si

tSi

Si

tSi

Nano-wire Fin / Tri

SOI

tox

µ

Gate electrode

Si channel

Gate oxidetox

Gate stack

Metal/Oxideinterface

dd

d

d

d

dd

d dd

dd

d

Si surface

d

Strong interaction betweencarriers and metal/oxide interface

Strong interaction betweencarriers and Si surface (or interface)

µ

d

66

Carrier density decrease

2015 2017 2019 20252021 2023 20272013Year10 7 5 1.83.5 2.5 1.314Commercial name (nm)

6.1 5.1 4.3 2.53.6 3.0 2.07.4TSi (nm)

ITRS 2013

tSi Volume DOS Carrier density

Si nanowireband structure

1 nm 2 nm 3 nm 4 nm 6 nm

Iwata et al., Journal of Computational Physics 229 (2010) 2339–2363

Diameter

67


Let us see what ITRS says about futureminiaturization!

2015 2017 2019 20252021 2023 20272013

10 7 5 ?3.5 ? ?14

Year

Commercial name (nm)

ITRS 2013 (Published in April 2014)

What about below 3 nm?Continue to miniaturize

69

2015 2017 2019 20252021 2023 20272013

10 7 5 ?3.5 ? ?14

Year



Reach limit after 2021?

Below 3 nm?

70

2015 2017 2019 20252021 2023 20272013

10 7 5 1.83.5 2.5 1.314

Year



Not limit at all ! Even 1.3 nm technology!!

71

2015 2017 2019 20252021 2023 20272013

10 7 5 1.83.5 2.5 1.314

? ? ? ?? ? ??

Year

Half pitch (HP) (nm)

Commercial technologyname (nm)


What about HP?

72

2015 2017 2019 20252021 2023 20272013

10 7 5 1.83.5 2.5 1.314

32 25.3 20 1015.9 12.6 840

Year


CommercialTechnology name (nm)


Much larger than the commercial technolgyname

73

2015 2017 2019 20252021 2023 20272013

10 7 5 1.83.5 2.5 1.314

32 25.3 20 1015.9 12.6 840

16.8 14.0 11.7 6.79.7 8.1 5.620.2

Year

Lg (nm)




Lg is also larger than the name.

74

2015 2017 2019 20252021 2023 20272013

10 7 5 1.83.5 2.5 1.314

32 25.3 20 1015.9 12.6 840

16.8 14.0 11.7 6.79.7 8.1 5.620.2

Year

Lg (nm)




So, people will be disappointed by the gap between the name and reality.

gap

75

2015 2017 2019 20252021 2023 20272013

10 7 5 1.83.5 2.5 1.314

32 25.3 20 1015.9 12.6 840

16.8 14.0 11.7 6.79.7 8.1 5.620.2

Year

Lg (nm)




Now, HP: X 0.80 / 2 years, Lg: X 0.83 / 2 years Thus, now more generations and more years until reaching limit

Before, HP: X 0.70 / 2 years, Lg: X 0.70 / 2 years

76

ITRS 2013 (Just published in April 2014)

Lg (nm)Metal half pitch (nm) Commercial name (nm)

Vdd (V) EOT (nm)

TSi (nm)

X 0.70 / 2 yearsX 0.80 / 2 yearsX 0.83 / 2 yearsX 0.96 / 2 yearsX 0.91 / 2 years

X 0.84 / 2 years

Only the commercial names decreases X0.7/ 2 years

Year 20271.3 (nm)

8 (nm)5.6 (nm)

0.43 (nm)0.65 (V)

2.0 (nm)

Year 201314 (nm)40 (nm)

20.2 (nm)

0.80 (nm)0.86 (V)

7.4 (nm)

Difference between the commercial name andphysical parameters becomes larger

1.3 nm technology!but HP = 8nm

Lg = 5.6 nm

Recently, companies become not to disclose Lg values at conferences

77

However, careful about the commercial name of technology!

22 nm Technology by Intel

Lg (Gate length) = 30 nm (HP), 34 nm (MP), 34 nm or larger (SP) IEDM 2012, VLSI 2013

10 nm Technology by Leti (FD-SOI)

Lg (Gate length) = 25 nm Euro SOI 2014

Recently, Gate length (Lg) is much larger than the Technology name

14 nm Technology by Global

Lg (Gate length) = 15 nm ECS Fall 201378

Near term until 2025 (in 10 years) Possible solutions

a) Less-aggressive shrink rate to extend the endb) Integration to vertical directionc) Decrease production cost

1. Stick to Si-CMOS device

2. Change channel materials (Alternative channel)a) InGaAs NMOS / Ge PMOS

c) 2D material with Bandgap; MoS2, etc.b) Carbon channel; Graphene/CNT

3. Change operational mechanism (New mechanism) a) T(Tunneling)-FET

d) Spin transistor, etc.

b) RTD (Resonance Tunneling Diode)c) SET (Single Electron transistor)


1. Stick to Si-CMOS device

2. Alternative channel

Low-risk/Low-return: Possible solution

High-risk/High-return: Not likely, but chance for Novel Prize

3. New mechanismSome of them already shows superior characteristics as a single device, while most of not.

However, very few report for circuit level performance, large size wafer, variability, yield (defect), reliability, etc.,necessary for production.

Middle term from 2025 to 2045 (10 to 30 years)

What will be the our society after 30 years?


Wearable What is next?


Wearable Minimum Wearing


Wearable Minimum/No Wearing



We do not want bring, many electronic items,such as smart-phone, battery charger, extra battery, PC, etc.




Everywhere in the environment, sensor to detect what human want to do,




Everywhere in the environment, sensor to detect what human want to do, display to watch,




Everywhere in the environment, sensor to detect what human want to do, display to watch, speaker to listen,




Everywhere in the environment, sensor to detect what human want to do, display to watch, speaker to listen, wireless power supply if necessary, ….


Thus, burden to the data processing of the smart phone will become light. And even no mobile smart phone may be necessary,


Thus, burden to the data processing of the smart phone will become light. And even no mobile smart phone may be necessary,

Sensor, short length wireless communication, display maybe powered by solar cell and operated by small scale microprocessor, will become more important.

What will be LSI fabrication process in 2030?

Today’s large size wafer process is necessary?

There are no miniaturization, thus cost reduction for fabrication by new concept will become important.

Today’s large clean room necessary?

For example, how about the chip size fabrication with many parallel chips on belt conveyer?

Middle term from 2025 to 2045 (10 to 30 years)

For minimum/no wearing?

Smart sensor, short length communication,display, speaker, well-distributed in the environment operated by small microprocessor and powered by solar cell.

For fabrication cost reduction?

New fabrication process idea is necessary.

Long term from 2045 to 2075 (30 to 60 years)

???


Direct communication between electron device and bio system / brain (insect/animal/human)

Use brain (insect/animal) for data processing

Self-assembly by using DNA.

Introduce the brain algorithm into semiconductor microprocessor.

Brain Ultra small volumeSmall number of neuron cellsExtremely low power

Real time image processing(Artificial) Intelligence3D flight control

Sensor

InfraredHumidityCO2

Mosquito

Dragonfly is further highperformance

System andAlgorism becomes more important!

But do not know how?


Self-assembling using DNA.

A kind of dream.


Self-assembling using DNA.

A kind of dream.

Assembling a device structure such like coral designed by DNA.

Thank you very much for your attention

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Documents

February 19, 2015 IEEE EDS MQ, WIMNACT 45, Tokyo ...February 19, 2015 IEEE EDS MQ, WIMNACT 45, Tokyo Institute of Technology, Yokohama, Japan Hiroshi Iwai Frontier Research Center,