FChapter 2 - Intro to MC68000

7/21/2019 FChapter 2 - Intro to MC68000

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Chapter 2

Introduction To MicroprocessorMC68000

Objectives

At the end of this topic, students be able to :

Identify the advantages of microprocessor 68000. Identify the programming model / software model 68000. Identify each list contained in the programming model 68000. Briefly describe the function of each list contained in the programming model

68000. Identifying the organization of memory in 68000 microprocessor. Byte addressing, word and long word in memory 68000 microprocessor


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Chapter 2


Popular in

embeddedsystem

ComprehensiveInstruction Set Bigger in

memorysize

Neatdesign

Easier to use byuser and compiler

P gettingmore

complex

2.1 Why Choose 68000

Why

68k?


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2.1 Why Choose 68000

Chapter 2


System based on 68000 Family
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2.3 68000 Programming Model

Chapter 2


P 68000 contains 3 main components:

a) Register : store data temporaryb) ALU : Data processed (+,-,*,/)c) Control unit : Controlling operations of all units with

provide control signals and timing.

In the MC68000 are internal registers that can be used by programmers to

model all MC68000 programming instruction.

Registers referred to as programming model MC68000

In other words, the programming model is what is seen by the programmer.(on-chip user-visible storage)


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CPU 86kD0

D15

A0

A23

Data BUS

AddressBU

S

$000000 $000001

$000002 $000003

$FFFFFF$FFFFFE

Memory Map

Data Register

Address Register

Program Counter

D0

A0

D7D6D5D4D3D2D1

Stack PointerA7A7

A6A5A4A3A2A1

31 1516 8 7 0

31 1516 8 7 0

31 1516 8 7 0

31 1516 8 7 0

Stack PointerUSPSSP

Status Register

15 0

7 0Even Odd


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Chapter 2


Following are the table for registers in 68000.


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Chapter 2


Data Register 32 bit : 8 (D0-D7)

Address Register : 7 (A0-A6)32 bit

Stack pointer (A7) : 2 (USP & SSP)32 bit

Program Counter : 1 (PC)32 bit

Register Status 16 bit : 1 (SR)


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2.4 68000 Registers

Chapter 2


a) Data Register (Dn)- Its main function is to store information that will and has been processed by

the ALU.

- Only the saved data only, the program is stored in the memory.- The data is stored in the 68k itself.- Contains 8 registers (D0 - D7), each size 32 bits.- Each data size is 32 bits (long word), 16 bit (word) and 8 bit (byte).


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2.4 68000 Registers

Chapter 2


b) Address Register(An)

Used for storing the location / address of an available data in memory. The address refers to the address stored in the memory (external memory).

It also acts as a pointer (pointer).

Contains 7 registers (A0 - A6), each size 32 bits.

Byte operation is not allowed due to address size is 16 bits (words) / 32 bit(long word).

If the value of 16 bits completed, it will be extended to 32 bits.


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2.4 68000 Registers

Chapter 2


For 68k, is 24-bit address bus (A1 - A23 and UDS * & LDS *), so only the

lowest 24 bits of the 32 bits in the register address used to access memory.

Therefore 68k address range is ~16 MB (224= 16777216, from

010/0000000016to 1677721510 / 00FFFFFF16)


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2.4 68000 Registers

Chapter 2


c) Stack Pointer (SP) An address register A7. Same behavior as register A0 - A6 but its main function is to execute a

subroutine. There are two stack pointer (each of size 32 bits)

i. Supervisor Stack Pointer(SSP)

ii. User Stack Pointer (USP)

- Special instruction such as STOP / RESET can not be executed (block usersdisrupt / stop operation of the entire system)

Only one active stack pointer at a time depending on the current processormode of the supervisor or user mode.

Provide important security features in the operating system


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2.4 68000 Registers

Chapter 2


d) Program Counter(PC)

Sized programmable 32-bit counter and is used to point to the instruction that

will be executed. To execute an instruction, the PC register is filled with the instruction

address.

During the instruction is decoded by the control unit, PC added to point to thenext instruction.

Hence, after instruction executes, the CPU has had enough information to dothe next instruction.


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2.4 68000 Registers

Chapter 2


e) Status Register (SR)

Status register can be divided into two parts, namely:

- Temple system (System Byte)

- Temple of users (User Byte) / Check Code Conditions (Condition CodeRegister) (CCR)

Supervisor mode, the entire list can be read and modified while in user mode,

the two bytes can be read but only the lowest byte can be changed.

X N Z V CT S I0I1I2

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

User ByteSystem Byte

CCR


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2.4 68000 Register

Chapter 2


X N Z V CT S I0I1I2

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


Carry

Overflow

Zero

Negative

Extend

Trace

Supervisor

InterruptMask

C (carry) : Value 1 when there is a carry during operation plus / minus borrowduring operation.

: In shift operations it contains a bit that is shifted out of theoperating

V (overflow) : Arithmetic value 1 when overflow occurs.: Arithmetic overflow occurs when operating on unsigned integer

exceed the space provided.


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2.4 68000 Register

Chapter 2


X N Z V CT S I0I1I2

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


Carry

Overflow

Zero

Negative

Extend

Trace

Supervisor

InterruptMask

Z (zero) : Value 1 when the operation result is zero

N (negative) : Value 1 when the operation result is negative

X (extend) : Copying the value of C for arithmetic operation

Note: Changes of CCR also depends on the instruction used.


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2.4 68000Register

Chapter 2


X N Z V CT S I0I1I2

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


Carry

Overflow

Zero

Negative

Extend

Trace

Supervisor

InterruptMask

Interrupt Mask (bit 8bit 10)

Modified supervisor mode to determine the lowest interrupt level CPU received.

Consists of 7 levels of interrupt (0012until 1112)

Example : If the interrupt mask bits have a value of 2 / 0102then interrupt levels 1 and 2are ignored. Only interrupt levels 3 to 7 are allowed..


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2.4 68000 Register

Chapter 2


X N Z V CT S I0I1I2

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


Carry

Overflow

Zero

Negative

Extend

Trace Supervisor

InterruptMask

Bit S (Supevisor) Selection for user mode (bit 13 = 0) / supervisor mode (bit 13 = 1)

Supervisor Mode : Can access the Supervisor Stack Pointer (SSP): The entire list of registers status can be achieved: All the instructions can be used.

User Mode : Can access the Supervisor Stack Pointer (SSP)

: Only the low byte status register can be accessed: Some instruction can not be executed.


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2.4 68000 Register

Chapter 2


X N Z V CT S I0I1I2

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


Carry

Overflow

Zero

Negative

Extend

Trace Supervisor

InterruptMask

Bit T (Trace) Trace bits that can be accessed while in supervisor mode

Bit T = 0: The instructions execute normally. Bit T = 1: 68k operating in trace mode

: After each instruction, a trace exception occurs and the processorexecute specific routines for debugging.

: This exception causes the CPU register value is displayed on theterminal.


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2.5 CPUAddressing Space

Chapter 2


MC68000 is commonly referred to as a machine / 16-bit microprocessor.

All external data enters the CPU at 16 bidirectional data lines (D0 - D15)

A total of 23 address lines (A1 - A23) along with online UDS* & LDS*, making68k capacity reaching up to 16Mbyte memory.

Limited to the size of the address space the address bus. Address range thatcan be achieved with n-bit address bus is 0 to 2n- 1.

For 68k, the address space is from $ 000000 - $ FFFFFF.

Each byte in memory with address unknown position. Address of a bytebeing written in hexadecimal (hexadecimal)


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2.7 Memory Mapping

Chapter 2


For 68k memory space that can be achieved only as much as 16Mbyte. This memory can be considered as a list of compartments / cells, each stores

8 bit / 1 byte of data.

$000000

$000002

$000001

$FFFFFF

$FFFFFE

$000003

1100 1010

1100 1101

1000 1100

1000 1100

8 bit


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2.7 Memory Organization

Chapter 2


Memory map can be redrawn to display one word per line. Here is a map of memory standard in programming 68k.

$000000

$000004

$000002

$FFFFFE

$FFFFFC

$000006

1100 1010

1000 1100

16 bit

$000001

$000005

$000003

$FFFFFF

$FFFFFD

$000007

1100 1101

1000 1100


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2.7 Memory Organization

Chapter 2


Memory cells numbered from zero up to the maximum capacity of memory. Memory addresses are usually written in hexadecimal. In the documentation Motorola, hexadecimal number specified by the symbol

'$'.

Data bus is 16bit 68k, making it capable of reaching a number of 16-bit datamemory data in one step.

Data stored in memory can be divided into1. Byte / byte (8 bits @ 1 @ 2 Nibbles bytes)2. Word / word (16 bits @ 2 bytes @ 4 Nibbles)3. Long word / longword (32 bit @ 4 bytes @ 8 Nibbles).


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2.7 Byte Addressing in Memory

Chapter 2


In memory, bytes can be placed in any position of the address, means theaddress can be odd or even.


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2.7 Word Addressing in Memory

Chapter 2


Word must begin at an even address High byte at address even while the low byte at an odd address

Example : 76EE16 is stored ataddress 00 Word 0 1

2 Word 1 3

4 Word 2 5

16777212 Word 16777213

16777214 Word 16777215

15 7 0$000000 01110110 11101110 $000001

$000002 Word 1 $000003

$000004 Word 2 $000005


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2.7 Long Word Addressing in Memory

Chapter 2


Password length must begin at an even address

Example : ABCD123416 is stored

at address 00Long Word 0

1

2 3

4Long Word 1

5

6 7

16777212Long Word

16777213

16777214 16777215

15 7 0

$000000 10101011 11001101 $000001

$000002 00010010 00110100 $000003

Long Word 2


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References

i. Antonakos, J. L., The 68000 Microprocessor: Hardware and SoftwarePrinciples and Applications 5th edition , Prentice Hall, 2004.

ii. Clements, A., Microprocessor Systems Design: 68000 Hardware, Software,and Interfacing 3rd edition, PWS, 1997.

iii. Tocci, R. J., Digital Systems: Principles and Applications 9th edition, PrenticeHall,2004.

iv. Floyd, T. L., Digital Fundamentals 8th edition, Prentice Hall, 2003.

v. Spasov, P., Microcontroller Technology: The 68HC11 and 68HC12 5th edition,Prentice Hall, 2004.

Chapter 2


Documents

FChapter 2 - Intro to MC68000