Fault-tolerant operation of multicell-inverters with a space phasor modulator

EUROPEAN TRANSACTIONS ON ELECTRICAL POWEREuro. Trans. Electr. Power 2008; 18:532–545Published online 20 August 2007 in Wiley InterScience
(www.interscience.wiley.com) DOI: 10.1002/etep.197
*CyE-

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Fault-tolerant operation of multicell-inverters witha space phasor modulator

Pablo Correa1,*,y, Mario Pacas2 and Jose Rodrıguez1

1Technical University Federico Santa Maria, Chile2University of Siegen, Siegen, Germany

SUMMARY

This paper presents a new space phasor modulation (SPM) scheme for the operation of the H-bridge multicellinverter under fault conditions. The topology of this inverter consists of several single-phase H-bridge inverterswhich can be independently bypassed if a fault is detected. As this action may result in an asymmetrical invertertopology, a new method based on the SPM is proposed to avoid voltage unbalances. Simulations and experimentalresults obtained in a five-level multicell inverter prototype validate the proposed fault-tolerant method.Copyright # 2007 John Wiley & Sons, Ltd.

key words: medium voltage drives; fault-tolerance; multicell inverters; space phasor modulation

1. INTRODUCTION

Multilevel voltage source inverters (VSI) are nowadays the standard approach in the market of medium

voltage drives and have replaced older solutions such as the current source inverter and the two-level

inverter in most applications. The main goal of multilevel inverters is to synthesize a stepped output

voltage waveform, so that the torque ripple and the harmonic distortion of the load currents are reduced

compared with the standard two-level topology. Due to the fact that the power switches have a lower

voltage stress and their switching frequency is lower than a conventional two-level inverter topology,

multilevel inverters are ideal for high power applications. Further advantages include a reduced

common mode voltage (CMV) generation and a lower electromagnetic interference (EMI) compared to

the two-level VSI. On the other hand, multilevel topologies require a higher number of power

semiconductors than the two-level inverter, as a consequence, the probability of the occurrence of a

fault is increased. This can be considered as a disadvantage in industrial processes with high associated

standstill costs. Nevertheless, multilevel topologies offer several freedom degrees that can be used to

allow the operation of the inverter with faulty components. This approach follows the basic ideas of

fault-tolerant operation, that is, once the fault is detected, the faulty components are isolated and the

orrespondence to: Pablo Correa, Technical University Federico Santa Maria, Av. Espana 1680, Valparaiso, Chile.mail: [email protected]

pyright # 2007 John Wiley & Sons, Ltd.

FAULT-TOLERANT OPERATION OF MULTICELL-INVERTERS 533

control is reconfigured to operate with the remaining healthy components. Some solutions have been

reported for flying capacitor topologies in References [1,2] and for the serial-connected H-bridge

(SCHB) topologies in References [3,4]. This work deals with the operation of the SCHB-VSI under

fault conditions.

According to the state of the art solution presented in the Reference [3], a bypass switch permits the

isolation of the affected cell and preserves the current path in the corresponding phase. Obviously, the

bypass of one cell results in an asymmetrical inverter topology which can be compensated in different

ways by means of a reconfiguration in the modulator unit. Some solutions for this problem have been

discussed in References [3,4] and make use of the well-known phase shift carrier PWM (PSC-PWM).

In Reference [3], balanced line-to-line voltages are obtained by means of an appropriate phase-shift in

the voltage references. In Reference [4], further simplifications allow the operation with an

unsymmetrical topology by adding a third sequence component to the voltage reference waveforms.

However, this last approach either generates line-to-line voltages with a small unbalance or requires a

closed loop controller for the modulator.

The main objectives of this work are to accomplish a balanced operation of a five-level SCHB-VSI

with bypassed cells and at the same time to generate output voltages with lower harmonic distortion and

with reduced switching losses. In order to achieve these aims, a new approach based on the multilevel

space phasor modulation (SPM) is analysed. Experimental results using a five-level SCHB multilevel

inverter are reported that validate the proposed method.

2. TOPOLOGY OF THE SCHB MULTILEVEL INVERTER

The SCHB multilevel inverter comprises several single-phase inverters or cells connected in series, as it

is shown in Figure 1a. Each cell contains a three-phase rectifier, a DC-link and an H-bridge inverter, as

it is depicted in Figure 1b. The H-bridge inverter can generate three different levels: �Ud, 0, Ud; where

Ud is the DC-link voltage which is assumed in this work to be constant. In this way, a topology

including two cells connected in series generates five different levels: �2Ud,�1Ud, 0, 1Ud, 2Ud. For the

sake of simplicity, the phase output levels will be referred to as Ud.

Most of the usual faults occurring in the cells can be detected by the standard protection system. For

example, the IGBT drivers include the detection of a short circuit in one leg of a cell whereas a damaged

capacitor is detected when the ripple of the DC-link voltage exceeds the limits. After the fault has been

detected, the bypass contactor is used to isolate the faulty cell and to permit the flow of current in the

phase dealing with fault, as it is shown in Figure 1b.

Once the cell has been bypassed, the modulator must be reconfigured; otherwise a voltage unbalance

may appear. The simplest solution to deal with this problem consists in the bypass of other two cells in

the other phases. For the five-level inverter with one faulty cell, this results in an equivalent three-level

inverter topology which can deliver only half of the maximum voltage corresponding to the healthy

inverter case. This solution is clearly suboptimal since healthy cells are also bypassed in order to regain

balanced voltages. Therefore, a solution which considers all healthy cells is desired.

3. EFFECTS OF THE BYPASS OF CELLS ON THE SPACE PHASOR MODULATION

A simple way to analyse the effect of the bypass of cells is by inspecting the resulting space phasor

diagram in each case. For the case of a healthy five-level inverter, 125 different phase output voltage

Copyright # 2007 John Wiley & Sons, Ltd. Euro. Trans. Electr. Power 2008; 18:532–545

DOI: 10.1002/etep

Figure 1. SCHB multilevel inverter: (a) topology; (b) inverter cell with a bypass contactor.

534 P. CORREA, M. PACAS AND J. RODRIGUEZ

states uUN, uVN, uWN give rise to 61 different voltage space phasors after applying the space phasor

transformation:

uðtÞ ¼ uaðtÞ þ j � ubðtÞ ¼2

3uUNðtÞ þ uVNðtÞ � e j2p3 þ uWNðtÞ � e j4p3

� �(1)

The resulting space phasor diagram is depicted in Figure 2a. Many of these space phasors are

actually generated by more than one voltage state, defining in this way a redundancy degree which can

be useful if one state becomes invalid after the bypass of one cell. Those space phasors lacking in

redundancy degrees, as it is the case of the ones located in the boundaries of the space phasor diagram,

disappear after the bypass of one or more cells. Thus, the bypass of cells affects the operation of the

modulator in two ways: first, the reference must be limited to a region with valid voltage space phasors,

and second, the voltage states corresponding to each space phasor must be selected considering the

states which are discarded after the occurrence of a fault.

For the following analysis, the modulation index a is defined as the quotient between the amplitude

of the reference voltage space phasor u�1 and the maximum amplitude of the reference space phasor for

linear operation considering a healthy inverter topology:

a¼u�1�� u_�

1

�� ; a � 1 (2)


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Figure 2. Voltage space phasor diagram of a five-level inverter; ‘o’ represents a missing space phasor after thebypass of cells: (a) healthy inverter; (b) with a single cell bypassed in phase U; (c) with a single cell bypassed inphase V; (d) with a single cell bypassed in phase W; (e) with cells U1 and U2 bypassed; (f) with cells U2 and V2

bypassed; (g) with cells U1, U2, V2 and W2 bypassed.


The representative fault configurations give rise to the following restrictions:

Co

a) O

pyri

ne cell bypassed in phase U means that the inverter can produce only voltages with three-levels

in this phase. In this case, there are 75 possible voltage states which generate the space phasor

diagram depicted in Figure 2b. The maximum modulation index a is given by the inner boundary

of the diagram, which is depicted by the circumference included in the same figure, that is,

a¼ 0.75. The outer regions represented by dashed lines are available if a higher voltage during

transients is desired, but they will not be considered in this first approach. The bypass of a cell in

the phase V or in the phase W generates a similar space phasor diagram but with a rotation of

1208, as it is shown in Figure 2c and Figure 2d. In the general case, the maximum modulation

ght # 2007 John Wiley & Sons, Ltd. Euro. Trans. Electr. Power 2008; 18:532–545

DOI: 10.1002/etep

Copyri


index at which the modulator can be adjusted if the operation with one faulty cell is allowed is

a¼ 0.75.

b) T
wo cells bypassed in the same phase permit the generation of 25 different voltage states and the
same quantity of voltage space phasors. Figure 2e shows this case, assuming that two cells are

bypassed in the phase U. Under this condition, each voltage space phasor is defined by only one

output voltage state, thus the redundancy degree is zero. The modulation index must be limited to

a¼ 0.5 to enable the operation of the inverter with the available space phasors. It has to be

remarked that despite the fact that the inverter generates voltages with two phases, there are still

three phases delivering currents, which differentiate this operation mode from the operation of a

single-phase inverter.

c) T
wo cells bypassed in different phases produce 45 different voltage states. Assuming that the cells
U1 and V1 of Figure 1 are bypassed, the resulting space phasor diagram depicted in

Figure 2f shows that a maximum modulation index of a¼ 0.5 is possible. Since in this case

the space phasors provided by the extra cell in phase W do not allow a higher voltage for steady

state operation, the bypass of all three cells in the same row is recommended. It is evident that

every healthy cell cannot always be used to provide higher voltages.

d) F
our cells bypassed, for example three cells bypassed in the first row and one cell bypassed in
the second row, generate the space phasor diagram shown in Figure 2g. From this diagram

it follows that the operation of the machine is still possible with a maximum modulation index

of a¼ 0.25. Similar to case (b), the redundancy degree of each voltage space phasor is equal to

zero.

After limiting the maximum modulation index, the next step is the generation of an appropriate

sequence of voltage states according to the selected space phasors. The bypass of cells reduces the

number of redundant voltage states, affecting the selection of an optimal sequence, as is shown in

Figure 3a. The selection of an optimal sequence obeys two criteria: on one hand, it should generate the

minimum CMV component, and on the other hand the sequence selection should minimize the number

of commutations. In a healthy inverter configuration, a sequence which accomplishes these criteria is

depicted in Figure 3b. Since some voltage states in sector A are missed after one bypassed cell in phase

U, a new sequence must be selected using the remaining ones, as it is illustrated in Figure 3c. Then,

although a sequence that considers a minimum number of switching actions can be still selected, a

higher CMV is generated.

4. OPERATION OF THE SPM WITH BYPASSED CELLS

The multilevel SPM algorithm developed in this work carries out three main tasks: the selection of a set

of voltage space phasors, the generation of an optimum sequence of voltage states and the generation of

the firing pulses.

4.1. Voltage space phasor selection

Similar to the SPM algorithm for two-level inverters, the reference space phasor is used to select the

corresponding set of three nearest adjacent inverter voltage space phasors. The determination of the

space phasors is easy in two-level topologies, as there are only six sectors available. In the case of a

five-level inverter, this process can be simplified by applying the following transformation to the

ght # 2007 John Wiley & Sons, Ltd. Euro. Trans. Electr. Power 2008; 18:532–545

DOI: 10.1002/etep

Figure 3. Sequences of voltage states with two configurations: (a) available voltage states for a sector of afive-level inverter with a single bypassed cell in phase U; (b) phase voltage waveforms and the corresponding CMVfor the sector A with a healthy inverter; (c) phase voltage waveforms and the corresponding CMV for the sector A

with a single bypassed cell in phase U.


Reference u�1 [5]:

u0�1 ¼ 3=2 �ffiffiffi3

p=2

0ffiffiffi3

p� �

u�1 (3)

This transformation locates every voltage space phasor in positions defined by integer numbers, as

shown in Figure 4. The coordinates of the three nearest inverter space voltage phasors u0a; u0b; u

0c can be


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Figure 4. Voltage space phasor diagram of a five-level inverter in the original frame of coordinates and resultingvoltage space phasor diagram after the transformation.


determined by applying the elementary arithmetic functions ‘smallest integer greater than x’, denoted

by the brackets de, and ‘greatest integer smaller than x’, denoted by the brackets bc, to the real and

imaginary part of u0�1 as follows:

u0a ¼ Reðu0�1Þ� �

þ Imðu0�1Þ

j

u0b ¼ Reðu0�1Þ

þ Imðu0�1Þ� �

j

if Reðu0�1Þ þ Imðu0�1Þ � Reðu0aÞ � Imðu0aÞ� �

> 0

u0c ¼ Reðu0�1Þ� �

þ Imðu0�1Þ� �

j

else

u0c ¼ Reðu0�1Þ

þ Imðu0�1Þ

j

9>>>>>>>>>=>>>>>>>>>;

(4)

The duty cycles corresponding to each voltage space phasor are equivalent to the projections of the

reference space phasor on the sides of the respective sector. After the transformation, the duty cycles

are given by the fractional parts of the reference space phasor u0�1 :

if u0�a þ u0�b� u0�a� �

þ u0�b

j k� �� > 0

then

da ¼ Imðu0c � u0�Þ��

db ¼ Reðu0c � u0�Þ��

dc ¼ 1 � da � db

else

da ¼ Reðu0c � u0�Þ��

db ¼ Imðu0c � u0�Þ��

dc ¼ 1 � da � db

9>>>>>>>>>>>>>>>>=>>>>>>>>>>>>>>>>;

(5)


DOI: 10.1002/etep


4.2. Optimal sequence selection

As it was remarked in Section 3, the voltage space phasors are represented by multiple redundant

voltage states whose difference is the CMV. The CMV is usually defined as

uCMV ¼ uUN þ uVN þ uWN

3(6)

It has been reported that the operation with low levels of CMV mitigates the occurrence of bearing

failures and EMI [6,7]. For this reason the CMV will be kept at the lowest possible level by selecting

only those states which generate the minimum value. Different algorithms are available to generate a

sequence with reduced CMV and at the same time with the minimum number of commutations [8]. In

this work, the following transformation is proposed to calculate the voltage state with minimum CMV

for a given space phasor u0:

u¼ uUNuVNuWN½ � ¼round 1

3ð2 � Reðu0Þ þ Imðu0ÞÞ

� ��Reðu0Þ þ uUN

�Reðu0Þ þ uVN

24

35T

(7)

After calculating the voltage states, the sequence with minimum number of voltage transitions in

each phase is determined by sorting the voltage states according to the CMV. Considering for example

the sector depicted in Figure 3, an optimal sequence using this criterion is given by the following

vector:

S ¼1 0 �2½ �1 1 �2½ �1 1 �1½ �

24

35; (8)

where each element represents a voltage state, and the order of the elements in S corresponds to the

sequence of the switching states. Since the voltage in one phase is kept constant over one modulation

period, this type of modulation scheme is called discontinuous modulation. On the other hand,

sequences with one voltage transition in each phase can be obtained by using an extra redundant state, if

it is available:

S1A ¼1 0 �2½ �1 1 �2½ �1 1 �1½ �

1 0 �2½ � þ 1 1 1½ �

264

375 or S1B ¼

1 1 �1½ � � 1 1 1½ �1 0 �2½ �1 1 �2½ �1 1 �1½ �

264

375 (9)

A redundant state can be calculated by adding CMV to the first or the last voltage state of the

sequence. If several sequences with the same CMV generation are available, such as S1A and S1B, then

the modulator selects a sequence depending on the sequence applied for the last sector, minimizing in

this way also the switching actions between sectors [9]. Since in this case each phase presents a single

voltage transition per modulation period, this modulation mode is known as continuous modulation.

Similar to the case of a two-level inverter, the order of the elements in the sequence is reversed in the

next half of the modulation period.

As it was discussed in Section 3, some states are missed after the bypass of one or more cells,

therefore an alternative valid sequence must be determined from the available redundant states. In the


DOI: 10.1002/etep


general case, a vector containing all redundant voltage states of a sector can be calculated out of the

original voltage states ua, ub, uc with minimum CMV as follows:

S ¼

..

.

uc � 2 2 2½ �ua � 1 1 1½ �ub � 1 1 1½ �uc � 1 1 1½ �

ua

ubuc

ua þ 1 1 1½ �ub þ 1 1 1½ �uc þ 1 1 1½ �ua þ 2 2 2½ �...

26666666666666666666664

37777777777777777777775

(10)

The voltage states which are not viable under the new inverter configuration are discarded and one

sequence with minimum CMV is selected. For the sake of simplicity, sequences with three voltage

states, which means discontinuous modulation, are preferred during this operation mode.

The calculation of this vector and the determination of the sequence obviously constitute a very

time consuming task for a conventional processor, however this is not a problem for implementation in

an FPGA, since Boolean operations are mainly required.

4.3. Firing pulses generation

After the sequence is determined, a state machine is used to distribute the switching actions evenly

among the available healthy power semiconductors of each phase. The details of this state machine can

be found in References [9,10].

5. EXPERIMENTAL SET-UP AND RESULTS

The proposed fault-tolerant modulation scheme was implemented in a five-level 10 kW SCHB

multilevel inverter, which was used to supply a 5.5 kW induction machine coupled to a load, as depicted

in Figure 5. Each cell includes a diode bridge in the input and a chopper for the regenerative operation.

A stator flux-oriented control was used for the control of the machine, which was implemented in a

floating point DSP platform ADSP-21062. The modulation task was programmed in a LFEC20E

FPGA.

Figure 6a shows the firing pulses of two power switches, the output voltages of two cells in the same

phase, the respective phase voltage and the line-to-line voltage of the inverter working in healthy

conditions with a modulation index of a¼ 0.98. In order to compare the performance of the SPM

scheme, simulated waveforms with the standard PSC.PWM were included in Figure 6b. It can be seen

that both modulation schemes produce similar firing pulse patterns; however, the line-to-line voltage of


DOI: 10.1002/etep

Figure 5. Experimental set-up.

Figure 6. Voltage waveforms of a healthy inverter without load, Ud¼ 80 V, THD calculated considering the first26 harmonics: (a) SPM (experimental) and (b) PSC-PWM (simulated).


DOI: 10.1002/etep


Figure 7. Voltage and carrier waveforms generated by the proposed SPM strategy, Ud¼ 80 V, Id¼ 5 A (exper-imental): (a) a single bypassed cell and (b) two bypassed cells in the same phase.


the SPM presents a lower harmonic distortion compared with the PSC-PWM. It has been demonstrated

in other works that the standard PSC-PWM scheme is harmonically suboptimal compared to other

modulation schemes such as SPM and phase disposition PWM (PD-PWM) [11,12]. This can be

explained by the fact that the SPM strategy eliminates the double steps in the line-to-line voltages, as

shown in the same figure.

In Figure 7a, the voltage waveforms of the inverter supplying the induction machine with one

bypassed cell are shown. It can be observed that despite the unsymmetrical topology, the line-to-line

voltages as well as the output currents are balanced.

A more stringent fault test is presented in Figure 7b, where two cells are bypassed in the same phase.

By using the proposed inverter reconfiguration method, it can be seen that both line-to-line voltages and

currents are balanced. Since in this case only 50% of the output voltage is available, the machine is

driven at half of the nominal speed. It can be seen that the currents exhibit a slight unbalance, but this is

caused by the operation of the DC-link choppers at low voltages.


DOI: 10.1002/etep


6. CONCLUSIONS

The operation of the SCHB multilevel inverter with SPM has been analysed under different fault

conditions. The presented fault-tolerant approach reduces the maximum modulation index and

makes use of an alternative redundant sequence to compensate the asymmetry in the topology

caused by the bypass of cells. Simulated and experimental results show that balanced currents

are generated, despite the highly unsymmetrical topology of the inverter resulting after the bypass

of one and two cells. Additionally, the proposed SPM approach exhibits a reduced harmonic

distortion if it is compared with the standard modulation strategy used in industrial SCHB multilevel

inverters.

7. LIST OF SYMBOLS AND ABREVIATIONS

7.1. Symbols

a m

Copyrigh

odulation index

N n
eutral point of the inverter
u1 s
tator voltage space phasor
Ud D
C link voltage
U p
hase U of the inverter
U1 fi
rst cell in phase U
U2 s
econd cell in phase U
uUN v
oltage in phase U with respect to the inverter neutral point N
uVN v
oltage in phase V with respect to the inverter neutral point N
uWN v
oltage in phase W with respect to the inverter neutral point N
V p
hase V of the inverter
V1 fi
rst cell in phase V
V2 s
econd cell in phase V
W p
hase W of the inverter
W1 fi
rst cell in phase W
W2 s
econd cell in phase W � r eference value
^ m
aximum value
7.2. Abbreviations

CMV c

t # 200

ommon mode voltage

CPLD c
omplex programmable logic device
EMI e
lectromagnetic interference
FPGA fi
eld programmable gate array
PWM p
ulse width modulation
PSC-PWM p
hase shift carrier PWM
SPM s
pace phasor modulation
SCHB s
eries-connected H-bridge
THD to
tal harmonic distortion
VSI v
oltage source inverter
7 John Wiley & Sons, Ltd. Euro. Trans. Electr. Power 2008; 18:532–545

DOI: 10.1002/etep


ACKNOWLEDGEMENTS

The author thanks the support of the German Service for Academic Interchange DAAD and the cooperation of theDireccion de Investigacion of the Technical University Federico Santa Maria.

REFERENCES

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3. Rodrıguez J, Hammond P, Pontt J, Musalem R, Lezana P, Escobar M. Operation of a medium-voltage drive under faultyconditions. IEEE Transactions on Industrial Electronics 2005; 52: 1080–1085.

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Letters 2002; 38: 1398–1400.9. McGrath B, Holmes D, Lipo T. Optimised space vector switching sequences for mutilevel inverters. IEEE Applied Power

Electronics Conference (APEC) Anaheim, 2001; 2: 1123–1129.10. Correa P, Pacas M, Rodrıguez J. A fault-tolerant operation of multicell-inverters with a space phasor modulator. Proceedings

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AUTHORS’ BIOGRAPHIES

Pablo Correa (31), received the Engineer and the Dr.-Ing degrees from the TechnicalUniversity Federico Santa Maria in Chile and the University of Siegen in Germany in2001 and 2006, respectively, both in electrical engineering. He is currently working as apost-doctoral researcher in the electronics department of the Technical University FedericoSanta Maria, Chile. His research interests include modern control strategies for multilevelconverter, current source converters and matrix converters.

Mario Pacas (53), VDE, Senior Member IEEE, studied Electrical Engineering at theUniversity of Karlsruhe in Germany obtaining the Dipl.-Ing. and the Dr.-Ing. degrees in1978 and 1985, respectively. From 1985 to 1995 he worked for BBC/ABB in Switzerland andGermany in different R&D and management positions with a very wide experience ininternational projects. In the last years with ABB he was responsible for the developmentof servo drives and later Product Responsible Manager for these products. Since 1996, he is amember of the Faculty of Electrical Engineering and Computer Sciences at the University ofSiegen and heads the Institute of Power Electronics and Electrical Drives. His special fields ofinterest are motion control, diagnostics, system identification and optimisation of mechatronic
systems.

DOI: 10.1002/etep


Jose Rodrıguez (53) received the Engineer and the Dr.-Ing degrees from the UniversityFederico Santa Maria in Chile and the University of Erlangen in Germany in 1977 and 1985,respectively, both in electrical engineering. He works since 1977 at the University FedericoSanta Marıa in Valparaıso, Chile. He is currently Professor and Rector at the same university.During his sabbatical leave in 1996 he was responsible for the mining division of the SiemensCorporation in Chile. He has a large consulting experience in the mining industry, especially inthe application of large drives like cycloconverter-fed synchronous motors for SAG mills, highpower conveyors, controlled drives for shovels and power quality issues. His research interestsare mainly in the area of power electronics and electrical drives. Currently, his main research
interests are in multilevel inverters and new converter topologies. He has authored andco-authored more than 130 refereed journal and conference papers and contributed to onechapter in the Power Electronics Handbook published in 2001 by Academic Press.

DOI: 10.1002/etep

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Fault-tolerant operation of multicell-inverters with a space phasor modulator