Fast digital signal processing of Fast digital signal processing of beam signal at ESRFbeam signal at ESRF

E. Plouviez on behalf of :

J. Cerray, Georges Gauthier, Gerard Goujon, Jean Marc Koch, Graham Naylor

Fast digital signal processing of Fast digital signal processing of beam signals at ESRFbeam signals at ESRF

DSP based:Global feedback

Booster tune monitor

FPGA based Injection rate monitor BPM processor:

HOM instability detector

Multibunch feedback

DDC basedGraychip 4016 DDC:

SR tune monitor Fast digitizer based:

Frequency mapping

Fast digital signal processing of Fast digital signal processing of beam signal at ESRFbeam signal at ESRF

DSP: continuous deterministic process, large amount of data processed at audio frequency rate

FPGA: continuous process, data processed at video to IF frequency rate => feedback, monitoring

DDC: frequency selective detection with flexible tuning

Fast digitizer: fast acquisition at video to IF frequency rate, slow but flexible processing

DSP pros and conDSP pros and con

Pros: Floating point calculation Powerful processed data handling, with a proper

OS C programming Fully deterministic

Con: Assembly math routine library mandatory => code

not easily reusable on another DSP! Fast data input and output bottleneck

upgraded Global feedback upgraded Global feedback

32BPMs

24 correctors

vertical and horizontal correction

C60 Floating point DSP

C40 ports taxi bus interface

BPMs:(2 BPMs spaced by 5m)

correctors: Front end DSP:

C40 links

Beam signal

RF mixer local oscillator and FPGA

clock generation

ADC inputs

(AD9226)

FPGA 45.44 MHz clock input

DAC OUTPUT

Processed data output

352,2 MHz / 10 MHz BW Band pass

filter

Mixer oscillator 278.35 MHz

352.2 MHz RF clock

75,53 MHz / 30 MHz BW Band pass

filter

Xilinx FPGA

FPGA clock and IF frequencies choice results in a synchronous I/Q sampling of the beam signal:Amplitude detection => positionPhase detection: longitudinal signal

FPGA beam signal processorFPGA beam signal processor

ESRF developed CUB board

CUB board layoutCUB board layout

cPCI ESRF developed board: Virtex 1 processor

Mezzanine:4 X 12 bits/ 65 Msps ADC1 X 12 bits/ 65 Msps DAC

Linux device server

ADC/DAC mezzanine

Simulink environmentSimulink environment

FPGA programmingFPGA programming

CubDSserver

MATLABGUI

Matlab GUIMatlab GUI

Position calculated by FPGA based Position calculated by FPGA based BPM (1 shot)BPM (1 shot)

FFT taken over 1000 turns after FFT taken over 1000 turns after injection kickinjection kick

FFT taken over 1000 turns after FFT taken over 1000 turns after injection kickinjection kick

HOM longitudinal instabilities HOM longitudinal instabilities detectiondetection (RF group project)(RF group project)

500 MHz and 900 MHz RF cavities HOM drive longitudinal instabilities

Beam signals around 150 MHz:

3 X 352,2 MHz- 900 MHz

500 MHz- 352.2 MHz

HOM instabilities show on the beam signal as side bands of the revolution frequencies harmonic shifted by the synchrotron frequency:

N X 355 KHz +/- 1.8 KHz

HOM longitudinal instabilities HOM longitudinal instabilities detectiondetection

ESRF developed CUB boards used as DDC to scan the beam and cavity signals to find which cell of a RF cavity drives the instability

Longitudinal feedbackLongitudinal feedback

At least 20MHz BW and maybe 180MHz BW (bunch by bunch) feedback:

FPGA is the obvious candidate for the signal processing

Tune monitor upgradeTune monitor upgrade

BPM pick up

RFtransfo

RFtransfo

RFtransfo

RFtransfo

RFcombiner

278.5 MHz oscillator

output 72.7 MHz / 10 MHz BW Band pass

filter

14 bits ADC and DDC board

Spectrum analysis

and display(DS + LabView)

Signal preprocessing using a digital down converter board =>large data compressionTune obtained by FFTBeam excitation by noise or small kicks

Transtech cPCI DDC board

Frequency mapFrequency map Many tune measurements after vertical and

horizontal transverse kicks of every amplitudes combinations

mapping BPM set upmapping BPM set up

BPM pick up RFcombiner 352.2 MHz

RF clock

output

H output

ADAS 12 bits 22Msps

ADC boars4 inputs

cPCI board:

1000 turns memory depth\

resolution:2.m/turn

Low Z.I signal

high X.I signal

I signal

V shaker signal

Cell 4-3 BPM

V output

Kicker trig signal

64 X frev clock signal

Resonant RF matching

circuitstuned at

352.2 MHz

Hm

=> H maxmm

Vm

=> Vmaxmm

LPF

LPF

LPF

Transverse phase space study at Transverse phase space study at large oscillation amplitudelarge oscillation amplitude

Will be used to study the non linearity of the beam transverse oscillation at high amplitude