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Fall 2018
ECEN 248: Introduction to Digital Logic design
Sections: 301, 302, 303
Lecture: MWF, 12:40PM -1:30PM, ZACH 241
Lab: All sections meet in CVLB 418 (NOT ZACH 333):
Sec 519 W 6PM – 8:50PM; Sec 520 R 8AM – 10:50AM; Sec 521 R 11:10AM – 2PM;
Sec 522 R 2:20PM – 5:10PM; Sec 523 R 5:30PM – 8:20PM
Course Description and Prerequisites Introduction to Digital Systems Design. (3-3). Credit 4. Combinational and sequential digital system design
techniques; design of practical digital systems. The covered topics are listed at the end of this syllabus.
Prerequisite: MATH 152 and PHYS 208 with a grade of C or better.
Learning Outcomes or Course Objectives
A student who successfully fulfills the course requirements will have demonstrated the ability to convert desired
system functionality into a digital design. Specific learning outcomes include the following: (1) ability to
analyze and design combinational logic circuits, (2) ability to analyze and design sequential logic circuits, (3)
ability to design high-level digital systems using Register-Transfer Level (RTL) design, and (4) utilize the
Verilog hardware design language, logic simulation, and Field Programmable Gate Array (FPGA) technology to
implement combinational, sequential, and RTL-based digital systems.
Instructor Information
Dr. Sam Villareal, Senior Lecturer, Department of Electrical and Computer Engineering
WEB 218D [email protected]
TR, 2PM – 4PM and by appointment 979-862-6334
Textbook: Digital Design with RTL Design, VHDL, and Verilog, 2nd Edition 2011, by Frank Vahid, John
Wiley & Sons. ). The textbook is required. Exams are open book and notes, but no electronics. You will have to
print textbook sections for the exam if you have an electronic version of the textbook
Laboratory Manual: Available online through eCampus (ecampus.tamu.edu)
Grading Policy
In-Class Assignments: 10% (2 team problems and 1 individual quiz; assigned each class with no
Exam or Scheduled Review)
Team Projects: 7%
2 Exams: 38% (18% Exam1 Sep 26, 2018; 20% Exam2 Oct 31 2018)
Final Exam: 20% (10:30AM – 12:30PM Dec 10, 2018)
Laboratory: 25%
The two exams (9/26/18 and 10/31/18) and the final exam (12/10/18) will be open book and open notes. While
the final exam will be cumulative, 70% of the final will be on material subsequent to the second exam (i.e.,
10/31/2018 through 12/5/2018). No electronic devices are allowed in Exam I. The only electronic device
allowed during Exam II and the Final Exam is a calculator. Please put your cell phone, smartphone, smartwatch,
laptop, etc. in your backpack during the exam. The two exams will be in-class and are on the schedule. The
Final Exam is at the scheduled time for final exams (December 10, 10:30AM – 12:30PM).
Note: ALL EXAMS & LABS ARE REQUIRED.
Attendance and Makeup Policy
Attendance to class is required in order to do the in-class problems and quizzes. If you miss class you should
email me, preferably before class is over and tell me the circumstances. This does not guarantee makeup
work is possible, but is required if there is to be makeup. Please do your best to be present for the exams and the
final exam. If you miss a class you will get a 0 for the in-class assignments and quiz. I will work with you to
give you another set of problems if you have a university excused absence. If you miss an exam or the final and
have a university excused absence, you will have the option of a makeup exam or scaling up the exam and/or
final exam percentages. If you do not have an excused absence, you will receive a zero unless there are
extenuating circumstances. Please see me before the scheduled time for the exam if possible. I expect written
documentation for an excused absence from an exam or the final. Please review the Student Rule on attendance
http://student-rules.tamu.edu/rule07.
Labs If you have to make up a missing lab, you can attend any other lab session as long as you get permission from
the TA of that section. After finishing the demo, ask that TA to send a confirmation email to your TA. You
must make up any excused missed or late lab report or demo within 7 class days of your missed lab, unless
you have a written exception from YOUR TA that gives you more time. ALL WORK IN LAB IS
INDIVIDUAL UNLESS YOU GET WRITTEN PERMISSION TO SHARE FROM YOUR TA.
Grading Scale A = 90% - 100%
B = 80% - 89.9%
C = 70% - 79.9%
D = 60% - 69.9%
F =< 60%
Course Topics, Calendar of Activities, Major Assignment Dates
Week Topic Required Reading & Watching
8/27-8/31
1 (NO Lab)
M Intro to course and analog vs digital
Intro to Digital Design; Digital vs
Analog; Binary Numbers
W Implement Dig. Systems; Switches;
MOS Transistors; Logic Gates
F Using Gates; Boolean Algebra;
Representing Boolean Functions
Syllabus, Due Dates, Labs (121)
Text 1.1-1.3
Text 2.1-2.4 (342)
Watch how MOSFETs work
https://www.youtube.com/watch?v=
QO5FgM7MLGg (~8.5 min) -cc
Watch how to build basic gates out of
MOSFETS-CMOS
https://www.coursera.org/learn/elec
tronics/lecture/TA8qw/6-3-cmos-
logic-gates (~10.5 min)- subtitles
Text 2.4-2.6 App A (563)
Watch Basic Boolean Axioms and
Theorems (be careful of last example
where text in video notes slight error
in circuit drawing)
https://www.youtube.com/watch?v=
TIYTI8rhaN8 (~22 min) -cc
9/3-9/7
2 (Lab 1)
M Continuing Boolean Algebra and
truth tables, more gates
W Decoders and Muxes
Text 2.6-2.8 (784)
Watch video on De Morgan’s Laws
https://www.youtube.com/watch?v=
W4KICOSIQGs (~4.5 min) - *
Watch canonical representation
https://www.youtube.com/watch?v=
Gjsfx-o7nnQ (~8 min)-cc
Text 2.9 (9105)
F K-Maps
Watch Video decoders
https://www.youtube.com/watch?v=
DgVkEVI6_Ws (~10.25 min) -cc
Watch Video on Mux
https://www.youtube.com/watch?v=
kpGEL7Xynjc (~19 min) –cc
Text 6.2 (11126)
Watch K-Maps
https://www.youtube.com/watch?v=
CpsJoAwreqo (~5.5 min) -cc
9/10-9/14
3 (Lab 2)
M Propagation Delay; Minimization
W Data Paths – Registers and Adders
Text 2.10 6.2 (13147)
Watch Propagation Delay
https://www.youtube.com/watch?v=
RWvppe0XMx4 (~3 min) -cc
Text 4.1-4.3 (15168)
Watch 4-Bit Register
https://www.youtube.com/watch?v=
PwsDLAFE1sE (~ 7.3 min) -cc
Watch PISO Register
https://www.youtube.com/watch?v=
7LmBcGiiYwk (~7.5 min) -cc
Watch Half and Full Adders
https://www.youtube.com/watch?v=
mZ9VWA4cTbE (~ 13 min) -cc
F Comparator; Multiplier
Text 4.4-4.5 (17189)
Watch Comparators
https://www.youtube.com/watch?v=
U9YPDgd0p9s (~ 18 min) -cc
Watch Array Multiplier
https://www.tutorialspoint.com/com
puter_organization/multiplication_us
ing_array_multiplier.asp (~ 7 min) -*
9/17-9/21
4 (Lab 3)
M Subtractors and Signed Numbers
W Arithmetic Logic Units
F REVIEW
Text 4.6 (19,20,10)
Watch Full Subtractor
https://www.youtube.com/watch?v=
IukUkIs5kL4 (~15Min) -cc
Subtraction with 2’s complement
https://www.youtube.com/watch?v=
vfY7bN_3VKw (~ 5min) -cc
Watch 2’s Complement
https://www.youtube.com/watch?v=
zWWWZJ_w2CA (~2.3 min)-cc
Text 4.7 (212211)
Watch ALU
https://www.youtube.com/watch?v=
1I5ZMmrOfnA (~11 min) -cc
9/24-9/28 M Verilog
5 (Lab 4)
W EXAM 1 ON 9/26
F SR Latches and D Flip Flops
Text 9.2 -9.3 (232412)
Watch Intro
https://www.youtube.com/watch?v=
q1QwC3YlHG0 (~4.7 min) -cc
Look at slides at
http://www.ece.tamu.edu/~sunilkhat
ri/courses/ee449/notes/verilog.pdf
Text 3.1-3.2 (252613)
Watch SR Latch and Gated SR Latch
https://www.youtube.com/watch?v=
-aQH0ybMd3U (~ 12.2 min) -cc
https://www.youtube.com/watch?v=
eFivBsjjlvo (~9.5 min) -cc
Watch D Flip Flop
https://www.youtube.com/watch?v=
Sh6B0lbiw4E (~6 min) -cc
10/1-10/5
6 (Lab 5)
M Verilog and Simulation
Text 9.4 (272814)
Watch Adder in Verilog
https://www.youtube.com/watch?v=
bL3ihMA8_Gs (~ 16 min) -cc
Continue to review slides in
http://www.ece.tamu.edu/~sunilkhat
ri/courses/ee449/notes/verilog.pdf
W Propose Project 1
F PROJECT 1 DAY
Project 1 for team As must be
approved by 1PM
Team work on project
10/8-10/12
7 (Lab 6)
M Finite State Machine and Controller
Design
W Metastability and Glitches
F State Reduction
Text 3.3 3.4 (293015)
What is a FSM
https://www.youtube.com/watch?v=
-WlrfGUg6tk (~9 min) -cc
Watch Reduced State Machine
https://www.youtube.com/watch?v=
bBcACMJotYg (-16.5 min) -cc
Text 3.5 (313216)
Watch Timing Issues
https://www.youtube.com/watch?v=
IoPp9AKagYs (~18 min) -cc
NOTE: Your Project 1 must be
uploaded by 10/15
Text 6.3 (333417)
Watch state reduction
https://www.youtube.com/watch?v=
mxyLoatx3Fg (~9 min) -cc
Watch state assignments
https://www.youtube.com/watch?v=
PvTeAJw9QF0 (~1.5 min) – no spoken
Watch Mealy vs Moore
https://www.youtube.com/watch?v=
S352lyPZP00 (~12.5 min) –cc
10/15-10/19
8 (Lab 7)
M Verilog for FSM and Testing
W Shifters, Counters, and Timers
F Register Files, and Component
tradeoffs
Text 9.5 (353618)
Watch 2 videos –both examples
https://www.youtube.com/watch?v=
9fex4Tt10-g ( ~16min) –cc
https://www.youtube.com/watch?v=
ENH-8zZLbK8 (~5.5 min)-cc
Text 4.8-4.9 (373819)
Watch Shift register
https://www.youtube.com/watch?v=
54AssCQ2w80 (~19.75 min) -cc
Watch Counter
https://www.youtube.com/watch?v=
kdF-U8xROKI (~11.33 min) -cc
Text 4.10-4.11 (394020)
Watch Registers
https://www.youtube.com/watch?v=
24MqCDIvQVI (~8 min) -cc
Text 4.13
Watch how ultrasound works
https://www.youtube.com/watch?v=
vloFWz-041k (~3 min)- cc
Watch beamforming
https://www.youtube.com/watch?v=
8rMtqRObvvU (~3 min) -cc
10/22-10/26
9 (Lab 8)
M Design Examples- FSM Controller
W Design Examples- Computers
F REVIEW
Watch Vending Machine
https://www.youtube.com/watch?v=
KHanq9mriJI (~11.75 min) -cc
Watch traffic controller
https://www.youtube.com/watch?v=
kgABPjf9qLI (~15 min) –cc
Watch Turing Machine (414221)
https://www.youtube.com/watch?v=
gJQTFhkhwPA (4.3 min) -cc
(434422)
10/29-11/2
M Register Transfer Language
Text 5.1-5.3 (454623)
Watch RTL
https://www.youtube.com/watch?v=
Tus1Tjhnd2w (4.3 min) -cc
Watch Languages Difference in HLSM
and FSM
10 (Lab 9)
W Exam 2 ON 10/31
F PROJECT 2 DAY
https://www.youtube.com/watch?v=
kAMlJeYG9J8 (15 min) -cc
Note: Your Project 2 must be
approved by 11/1
11/5-11/9
11 (Lab 10)
M Design and clock frequency
W RAM, Rom, Flash memory
F FIFOs and multiple processors
Text 5.4-5.5 (474824)
Watch datapath timing
https://www.youtube.com/watch?v=
2boNpfT2Jmc (~6.3 min) -cc
Watch Parallelism
https://www.youtube.com/watch?v=
m4T7p9k3LgE (~2 min) -cc
Text 5.7 (495025)
Watch RAM
https://www.youtube.com/watch?v=
o_h8YHeW5sg (~15 min) -cc
Watch SRAM vs DRAM
https://www.youtube.com/watch?v=
mwNqzc1o5zM (~4.25 min) -cc
Watch ROM
https://www.youtube.com/watch?v=
9-ivunH8Aps (~13.25 min) -cc
Text 5.8-5.9
Watch a use of FIFO (515226)
https://www.mathworks.com/videos/a
synchronous-fifo-design-and-buffer-
modeling-68922.html (4.5 min) -*
11/12-11/16
12 (Lab 11)
M Hierarchies-Cell Phone
W RTL design Optimization and
tradeoffs
F Manufacturing ICs
Text 5.10, 5.13 (535427)
Watch How cell phone works
https://www.youtube.com/watch?v=
xv9dRENgDoc (~ 3.3 min) -cc
Watch how cell networks work
https://www.youtube.com/watch?v=
cJQZvxfDFug (~14.75 min) -cc
Text 5.11, 6.5-6.6, (555628)
Watch Pipelining
https://www.youtube.com/watch?v=
Sk4puph6GCI (~11.6 min) -cc
Text 7.1-7.2 (575829)
Watch Full custom vs ASIC
https://www.youtube.com/watch?v=
XhzEhMcHGGI (~10.6 min) -cc
11/19
13 M FPGAs
Text 7.3 (596030)
Watch FPGA basics
https://www.youtube.com/watch?v=
CfmlsDW3Z4c (`13.3. min) -cc
Watch History of programmable logic
https://www.coursera.org/learn/intr
o-fpga-design-embedded-
(NO Lab)
NO class on WED 11/21
systems/lecture/YaCfa/2-a-brief-
history-of-programmable-logic (~9.7
min) –subtitles
NOTE: Your Project 2 Report due no
later than 11/20 AND
You must have approval for Project
3 by no later than 11/21
11/26-11/30
14 (Lab 12)
M IC Tradeoffs
W Processors M Processors Continued
F Error Detection and Correction
Testing and Encryption
Text 7.5 (616231)
Text 8.1-8.5 (636432)
Watch datapaths
https://www.youtube.com/watch?v=
ibYYqvp9FmU (~ 15 min) -cc Text 8.6
Watch Fetch/Decode/Execute
https://www.youtube.com/watch?v=
XM4lGflQFvA (~5 min) -cc
NOTES (656633)
Watch Hamming Code
https://www.youtube.com/watch?v=
cBBTWcHkVVY (~ 5.5 min) -cc
Watch
https://www.youtube.com/watch?v=
3fhNN4OdHZI (~9min)
12/3-12/4
15
M Redefined Friday REVIEW
W PROJECT 3 DAY
NOTE: Project 3 must be uploaded
by 12/5
Final Exam on Monday December 10th
Other Pertinent Course Information
It is acceptable to look on-line and in notes or the book for in class assignments, quizzes, and labs,but
the work you submit , as a team or individually, should be your own work- (not copied or heavily
borrowed from others or other resources). In class assignments and projects are team work, but
quizzes, labs, and exams are individual work.
Americans with Disabilities Act (ADA)
The Americans with Disabilities Act (ADA) is a federal anti-discrimination statute that provides
comprehensive civil rights protection for persons with disabilities. Among other things, this legislation
requires that all students with disabilities be guaranteed a learning environment that provides for
reasonable accommodation of their disabilities. If you believe you have a disability requiring an
accommodation, please contact Disability Services, currently located in the Disability Services building
at the Student Services at White Creek complex on west campus or call 979-845-1637. For additional
information, visit http://disability.tamu.edu.
Academic Integrity
Students are expected to be aware of the Aggie Honor Code and the Honor Council rules and
procedures (see http://aggiehonor.tamu.edu). For additional information please visit:
http://aggiehonor.tamu.edu
“An Aggie does not lie, cheat, or steal, or tolerate those who do.”