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UC Davis 1 Hussain Al-Asaad
UNIVERSITY OF CALIFORNIA—DAVISDEPARTMENT OF ELECTRICAL & COMPUTER ENGINEERING
EEC180A—DIGITAL SYSTEMS I
FALL 2010
EXAM II
STUDENT INFORMATION
INSTRUCTIONS
The exam is closed book and notes. A single double-sided cheat sheet is allowed.Print your name and your ID number.There are four problems in the exam. Solve all of them and show your work.If you need more space for your solution, use the back of the sheets.
EXAM GRADE
Name
ID Number
Problem Maximum Points
Student Score
1 25
2 25
3 25
4 25
Total 100
UC Davis 2 Hussain Al-Asaad
1. ARITHMETIC CIRCUITS (15 + 10 = 25 POINTS)
Let X be a 3-bit two’s complement number represented by X2X1X0 and let Y be a 9-bit two’scomplement number represented by Y8Y7Y6Y5Y4Y3Y2Y1Y0.
1.1 Design a gate-level circuit C that computes the function . Minimize the numberof gates in your design. Assume that the input combination X2X1X0 = 100 will never appear at theinputs of C. Moreover, you can assume that the literals and their complements are available.
1.2 Suppose that we have an 8-bit adder (shown below), show how we can implement thefunction .
Y X2 4–=
Y 48X 47+=
a0 b0
s0
a7 b7
s7
a6 b6
s6
a5 b5
s5
a4 b4
s4
a3 b3
s3
a2 b2
s2
a1 b1
s1c8 c0
UC Davis 3 Hussain Al-Asaad
2. FLIPFLOPS (5 + 6 + 6 + 8 = 25 POINTS)
Consider a new type of a positive edge-triggered flip-flop that we call the AB flip-flop. Thecharacteristic equation of the AB flip-flop is . Moreover, the mode AB = 11 is notallowed.
2.1 Complete the table below.
2.2 Complete the excitation table of the AB flip-flop.
2.3 Implement the AB flip-flop using an RS flip-flop and logic gates.
2.4 Using AB flip-flops, design a counter that counts 2, 1, 0, and repeat.
Q Q+ A B0 00 11 01 1
Q+ AQ B+=
A
B
Q
Q
CLK
A B Mode0 00 11 01 1 Not allowed (Forbidden)
UC Davis 4 Hussain Al-Asaad
3. ADDERS AND COUNTERS (10 + 15 = 25 POINTS)
3.1 Draw the state diagram of the counter shown below.
cin
a b
Q3
FA
D flip-flopD3
1
0cout s cin
a b
Q1
FA
D flip-flopD1
1
cout scin
a b
Q2
FA
D flip-flopD2
1
cout s cin
a b
Q0
FA
D flip-flopD0
1
cout s
UC Davis 5 Hussain Al-Asaad
3.2 By using four D flip-flops and four full adders only (components shown below), design a 4-bit binary counter with two inputs U (up) and D (down) that works as follows:
1. If U = 1, the counter counts up.2. If D = 1, the counter counts down.3. If U = 0 and D = 0, the counter hold its state.
Assume that the input combination (U = 1, D = 1) is considered a don’t care. Moreover, assumethat the literals and their complements are available. Show the schematic of your design.
cin
a bFA
cout s QD flip-flop
D
Q3 Q2 Q1 Q0
4-bit up-down binary counter
U D
UC Davis 6 Hussain Al-Asaad
4. COUNTING SEQUENCE IDENTIFICATION (25 POINTS)
Suppose that we know the following information about the counter shown below:• The state 7 must be on the counting sequence of the counter.• For every state on the counting sequence other than state 7, the next state must be larger than
the current state.
Design the combinational circuit C using the minimum number of logic gates, so that thecounter produces the largest counting sequence. Also, draw the resulting state diagram of thecounter (Use the order of Q2Q1Q0 in labeling the states). Is the resulting counter self starting?
T2 Q2 T1 Q1 D0 Q0
ClockQ2 Q1 Q0
f(X,Y,Z) YX
C
Q2 Q1 Q0
Z
