Exploring the Design Space for Crossbar Arrays Built With ... · NARAYANAN et al.: EXPLORING THE DESIGN SPACE FOR CROSSBAR ARRAYS BUILT WITH MIEC ADs FIGURE 2. Scaled MIEC Access

Received 27 February 2015; revised 24 April 2015; accepted 11 May 2015. Date of publication 5 June 2015; date of current version 21 August 2015.The review of this paper was arranged by Editor S. Moshkalev.

Digital Object Identifier 10.1109/JEDS.2015.2442242

Exploring the Design Space for Crossbar ArraysBuilt With Mixed-Ionic-Electronic-Conduction

(MIEC) Access DevicesPRITISH NARAYANAN1 (Member, IEEE), GEOFFREY W. BURR1 (Senior Member, IEEE),

ROHIT S. SHENOY2 (Member, IEEE), SAMANTHA STEPHENS3, KUMAR VIRWANI1 (Member, IEEE),ALVARO PADILLA4, BÜLENT N. KURDI1, AND KAILASH GOPALAKRISHNAN5 (Member, IEEE)

1 IBM Research—Almaden, San Jose, CA 95120, USA2 Intel, Santa Clara, CA 95054, USA

3 Department of Physics, Wellesley College, Wellesley, MA 02481, USA4 SanDisk, Milpitas, CA 95035, USA

5 IBM T. J. Watson Research Center, Yorktown Heights, NY 10598, USA

CORRESPONDING AUTHOR: P. NARAYANAN (e-mail: [email protected])

ABSTRACT Large-scale 3-D crossbar arrays offer a path to both high-density storage class memory andnovel non-Von Neumann computation. However, such arrays require each non-volatile memory (NVM)element to have its own non-linear access device (AD), which must pass high currents through one or moreselected cells yet maintain ultra-low leakage through all other cells. Using circuit-level SPICE simulations,we explore design constraints on crossbar arrays composed of a generic NVM element (+1R) together withthe novel AD developed by our group, based on Cu-containing mixed-ionic-electronic-conduction (MIEC)materials. We show that power consumption during write, not read margin, is the most stringent constraintfor large 1AD+1R crossbar arrays. As array size grows, in order to keep NVM write power-efficient,the voltage at which the AD “turns on” must outpace the NVM switching voltage. Failure to achievethis condition causes the total array power, injected into the array to ensure the success of the worst-casesingle-bit write, to greatly exceed the actual NVM write power. Extensive tolerancing results show thatNVM switching current and other AD parameters (subthreshold slope and series resistance) are alsoimportant, but not to the same degree as AD and NVM voltage characteristics. We show that scaledMIEC devices (Voltage Margin Vm ∼ 1.54V) can support 1 Mb arrays for NVM switching voltagesup to 1.2V, and that stacking two MIEC devices could enable ∼2.4V. The impact of Vm variability isquantified—we show that there is minimal degradation in write power and read margin at variabilities(standard deviation in Vm) not very different from those already demonstrated experimentally.

INDEX TERMS MIEC, access device, 1S1R, 1AD1R, circuit simulation, non-volatile memory, crossbarmemory, selector.

I. INTRODUCTIONResistive RAM, PCM and STT-MRAM are emergingas promising non-volatile memory (NVM) candidates forStorage Class Memory — technologies that could combinethe low latency and robustness of a solid-state memory withthe non-volatility and low cost of storage technologies suchas NAND Flash or magnetic hard disks [1], [2]. One possi-ble path towards manufacturing such memories at low costper bit is a 3D crossbar array of NVM devices.

To minimize sneak path currents, each NVM must be inseries with an Access Device (AD) with a strongly non-linearI-V characteristic. For 3D stacking, an AD must also be Back-End-Of the-Line (BEOL) compatible, and fit within the same4F2 footprint as the NVM in a crossbar array. A numberof potential AD candidates have been proposed [3]. Withoutan AD, “sneak path” currents can easily mask read currents,closing the read margin needed to distinguish between NVMelements in their high and low resistance states [4]. Worse yet,

2168-6734 c© 2015 IEEE. Translations and content mining are permitted for academic research only.Personal use is also permitted, but republication/redistribution requires IEEE permission.

VOLUME 3, NO. 5, SEPTEMBER 2015 See http://www.ieee.org/publications_standards/publications/rights/index.html for more information. 423

NARAYANAN et al.: EXPLORING THE DESIGN SPACE FOR CROSSBAR ARRAYS BUILT WITH MIEC ADs

NVM writes tend to require high current density through asmall number of selected cells. This means that the maximumachievable array size — while still ensuring that all writeoperations are successful — rapidly diminishes without asimilarly strong nonlinearity [5]. The larger such arrays canbe made, the lower the area overhead due to peripheralcircuitry, and the higher the efficiency in terms of number ofaccessible bits per unit area of silicon (and thus, at least tofirst order, per unit fabrication cost).Maximum array size is constrained by numerous device

and circuit level parameters, including NVM switchingcurrents and voltages, AD non-linearity, off-state leakage,AD series resistance, and interconnect resistance. Such adesign space — extending across NVM, AD and circuitparameters — can be quantitatively explored through cir-cuit analysis, in order to identify critical design parametersand constraints, to study the compatibility of an AD againsta range of NVM switching properties, and to quantify theimpact of technology scaling.To be maximally useful, such a study should:1) Use SPICE [6], [7] or another framework [8] capable

of modeling non-linear ADs and NVMs;2) Consider both write and read operations self-

consistently, addressing the constraints for each;3) Consider large array sizes (∼1Mb or higher);4) Account for interconnect resistance, which becomes

important at higher (write) currents and larger arraysizes, and in scaled technology nodes;

5) Provide design guidance with every datapoint, com-puting injected power required to ensure NVM writesuccess, and best-case read margin while avoiding readdisturb;

6) Use accurate behavioral representations of NVM andAD I-V characteristics to determine exact switchingconditions, power consumption, and read voltages, and;

7) Employ crossbar-bias schemes that can offer bet-ter leakage power mitigation than simple fixed-ratio(e.g., V/2 or V/3) schemes.

In this paper, we present a SPICE-based circuit analysisof 1AD+1R crossbar arrays that meets all of these cri-teria, expanding upon our earlier brief summary [9]. TheADs used in these simulations are copper-containing MixedIonic Electronic Conduction (MIEC) ADs [10]–[15], pre-viously shown to have many desirable characteristics forintegration into 1AD+1R crossbar arrays. A conferencework that extended the present analysis to other publishedaccess devices has also been published [16], but this workis not included in the present manuscript due to spaceconsiderations. Similarly, peripheral circuitry for NVM tech-nology is not discussed — the interested reader is referredto References [17]–[20].In Section II we present our DC behavioral model for the

bipolar selectors and a generic NVM element, and a circuitreduction technique for simulation of large arrays with rea-sonable run times. We then present results for write powerconsumption (Section III) and read margin (Section IV) and

FIGURE 1. Circuit schematic of 1AD+1R crossbar array with one selectedcell (blue), partially selected cells along the same horizontal WL (red),partially selected cells sharing the same BL (green), and unselectedcells (light blue). Colors available in online version.

their dependence on various device and circuit parameters. InSection V, we compare this work to previous efforts at cross-bar analysis, and show that no prior work has achieved allseven of the items listed above. In Section VI, we concludethe paper.

II. SIMULATION FRAMEWORKFig. 1 shows a circuit schematic of a 1AD+1R crossbararray with an Access Device and an NVM at each intersec-tion node. In this array, the nonlinearity of the AD helps itmaintain ultra-low leakage on a large number of unselectedcells and low to moderate leakage on a small number ofpartially selected cells, while remaining capable of passingmuch higher read or write currents through one or moreselected cells.

A. MIEC ACCESS DEVICESCu-containing Mixed Ionic Electronic Conduction (MIEC)ADs have previously been shown to have a range of desir-able characteristics [10], including BEOL compatibility, largeON/OFF ratios, high voltage margin Vm, the high currentdensities needed for PCM, and the fully bipolar operationneeded for high performance RRAM and MRAM [11]–[15].Vm is always measured at the 10nA current level, roughlycorresponding to the partial-select condition. Integrationof these selectors at 100% yield (at 512kBit scale) hasbeen shown [13]. These devices can provide write level(>100μA) currents within 15ns [14], read level (5-10μA)currents within 50ns [15], and can be scaled to the <30nmCDs and <12nm thicknesses found in advanced technologynodes [14].The I-V characteristic of a scaled MIEC device (top CD

∼ 35nm, Fig. 2) exhibits a voltage margin Vm of 1.54V. Theturn-on slope (S) — technically inverse-slope: the change involtage for each 10× increase in current — is 85mV/dec,

424 VOLUME 3, NO. 5, SEPTEMBER 2015


FIGURE 2. Scaled MIEC Access Devices exhibit voltage margins Vm(at 10nA) of ∼1.54V, ON-OFF contrast in excess of 107 and ultra-lowleakage at low bias[11]–[15], suitable for large arrays with manyunselected devices. Dotted red line shows simulation model with fitparameters.

FIGURE 3. Generic NVM model for SPICE, with switching between anohmic LRS and an HRS exhibiting Poole-Frenkel conduction. Inset showsequivalent circuit for SPICE modeling of the bipolar, highly non-linearMIEC-based Access Device.

with high current response dominated by an effective seriesresistance of 2.85k�. This I-V characteristic can be modeledin SPICE using a simple equivalent circuit (inset, Fig. 3) oftwo anti-parallel diodes with fitted parameters (IS, n) andseries resistors (Rseries), together with a current source INF)to model the low-voltage leakage current (3pA).

B. MODELING NVM I-V CHARACTERISTICSThe I-V switching characteristics of a generic bipolar NVMelement (Fig. 3) alternate between a positive-polarity SEToperation (high to low resistance switching) and a negative-polarity RESET operation. The high resistance state (HRS)either can be ohmic or can follow a Poole-Frenkel (PF) (orSchottky Emission) relationship (I ∝ √

V). When devicevoltage and current increase beyond a switching threshold(VHRS, IHRS), the I-V characteristic undergoes a ‘snap-back’,transitioning into a linear region with holding voltage Vhand dynamic resistance Rdyn. This lower effective resistancecorresponds to increasing crystal fraction in PCM, or tofilament growth in RRAM. For MRAM, Vh ∼ 0 with bothstates ohmic. An explicit external compliance is not enforced.During voltage sweep of the SET operation, the completionpoint is determined during post-processing, by identifyingthe first DC sweep point where the voltage and current

TABLE 1. Default simulation parameters.

through the NVM are equal to or greater than VLRS, ILRS,thus guaranteeing the delivery of the necessary switchingpower.The RESET behavior is analogous, with the ohmic LRS

state (RLRS = VLRS/ILRS) switching into an HRS state whendevice voltage drops below −VLRS. The voltage across thedevice “snaps forward” (consistent with filament pinch-off inRRAM). At voltages beyond −VHRS the device is consideredto be fully RESET. The exact RESET condition (e.g., theexternal voltage necessary to produce > VHRS at the selecteddevice) is determined during post-processing. All transitionsare modeled using conditional syntax available with standardSPICE simulators such as HSPICE [6] and LTSPICE [7].Table 1 summarizes nominal values for all device and

circuit parameters. These parameters are not intended torepresent any particular NVM, but instead are chosen torepresent a desired yet still reasonable target for eitherRRAM or PCM devices. In particular, our intent is to showwhat would be required from an NVM in order to achievearrays of 1Mbit in size, not just for MIEC devices but forany access device [16]. Our choice of ILRS ensures rea-sonable IR drops even for large arrays (for a 1Mb array,total BL and WL IR drop is ∼68mV). While currentdensity (1.46MA/cm2) is close to the ITRS electromigrationthreshold (1.5MA/cm2 [21]), a non-volatile memory applica-tion will drive such peak currents less frequently than a logiccircuit, postponing the onset of electromigration–induceddamage.

C. SIMULATING LARGE ARRAYSSimulation time for arrays with millions of individual SPICEnodes (Fig. 1) can be prohibitively long. However, since cur-rent in unselected wordlines and bitlines is negligible andtheir interconnect IR drop can be neglected, the unselectedportion of the array can be replaced by a single AccessDevice/NVM pair, with leakage equal to the aggregate uns-elect leakage (see Fig. 14). This reduces the number of nodesand speeds up simulations considerably.

III. WRITE OPERATIONSThe metric of interest during a write operation is maximumtotal power consumption, which can occur at any one of

VOLUME 3, NO. 5, SEPTEMBER 2015 425


FIGURE 4. a) Total voltage required to cause a switching event is the sumof the NVM switching voltage, the diode voltage, and any IR drop acrossthe wiring. b) Our simulation approach is to fix the unselect bias (VC − VR)to ensure low leakage (10µA total), followed by a DC sweep of the linevoltages VW and VB to trigger the relevant NVM switching condition.

the four switching points (Fig. 3), for the worst-case devicefarthest from the voltage source (see Fig. 1), when all otherdevices are in the LRS state.

A. BIASING SCHEME FOR WRITEDuring write operations, all unselected rows and columnsare at voltages VR and VC, respectively. This inner volt-age separation is chosen to ensure a total unselect leakageof 10μA. For a 1Mb array, the resulting 10pA requiresVC − VR ∼ 0.6V (see Fig. 2), leading to 6μW of unselectpower. Such a design point is only possible because of theultra-low leakage offered by the MIEC-based AD.During each circuit simulation, voltages applied at the

array edge (VW and VB) are swept from low to high. Post-processing identifies the applied voltage (and thus power)at which the selected NVM element switches. As shown inFig. 4, total applied voltage is the sum of NVM switchingvoltage, selected diode voltage and IR drop across the wiring,and must be balanced by the sum of the voltages acrossthe three types of non-selected devices: partially selected(same WL), unselected, and partially selected (same BL).Fig. 5 shows simulated currents during a SET operationon a 64x64 array as total applied voltage (VW − VB) isincreased.

COMPARING POWER CONSTRAINT BIASING TO OTHERSCHEMESFixing the unselect bias based on power constraints providesfor a more optimal approach than other biasing schemes suchas V/2 and V/3. In a V/2 scheme, VR = VC = VTOTAL/2,eliminating leakage through unselected cells. However, sinceleakage through partially selected ADs increases rapidlywith increasing voltage, the maximum VTOTAL this schemecan support, for a given power budget, is lower than inthe constraint-based scheme described above. Without theultra-low (�1nA) leakage currents of the MIEC-based AD,

FIGURE 5. Simulated current through various cells during a worst-caseSET operation on a 64×64 array, as total applied voltage undergoes a DCsweep, with NVM transition points labeled.

however, our constraint-based scheme would choose a van-ishingly small inner voltage separation VC − VR, becomingeffectively indistinguishable from the V/2 scheme. In a V/3scheme, the voltage drop across all non-selected cells is∼ VTOTAL/3. While unselected and partially selected cellleakage is equal, there are quadratically more unselectedcells, so the maximum supported VTOTAL is lower than withthe constraint-based scheme.

NOTE ON TRANSIENT RESPONSE

Our circuit analysis is based on the steady-state I-V responseof the MIEC AD. However, fast switching (<10ns) of MIECdevices into high current states can require overvoltage accel-eration [15], which increases the total voltage VW −VB thatmust be applied at the edges of the array. We can considerwrite operations along a single WL held at VW , with multi-ple cells along that WL written in succession by activatingand deactivating individual BLs. Unselected and partiallyselected ADs along this WL are held for long periods oftime, at biases selected from the steady-state I-V response.However, bias points for ADs along the BL, both selectedand partially selected, should use the relevant transient I-Vfor the desired access latency. Since, for MIEC-based ADs,transient I-Vs resemble a voltage-shifted version of thesteady-state I-V [15], the overvoltage added to the selecteddevice is counter-balanced, at least to first order, by thetransient nature of leakage buildup through the BL partiallyselected devices.Another consideration for transient analysis is the impact

of the brief (1-2us) recovery period for an MIEC deviceto return to the low leakage condition. We have previouslyshown that, after a write operation of ∼50uA, MIEC devicesreturn to low leakage only after 1us held at zero volts (orfaster for negative bias). The recovery after a read operationis markedly faster. This criteria might affect the order inwhich accesses ought be arranged, and will likely affectthe effective write bandwidth. However, we believe that theprimary results of this paper, in terms of supported arraysizes and NVM switching voltages, will remain unaffectedto first order.



FIGURE 6. Total array power shows worse-than-exponential ‘tippingpoints’ for even small increases in switching voltage parameters VHRS orVLRS . Nominal values shown in parentheses. (Inset) Dependence of arraypower on the stored data pattern as VHRS is varied.

B. SIMULATION RESULTSSimulations of write operations were carried out with indi-vidual parameters from Table 1 varied one at a time. Fig. 6plots the total write power vs. individual NVM switchingparameters for the scaled MIEC device. These results area significantly different representation than earlier work oncrossbar array design: every single data point in Fig. 6 rep-resents an operating point that will result in successful writeoperations, albeit at a power cost that could easily be oner-ous. In contrast, earlier works frequently show plots in whichwrite or read operations “work” at one end of the graph, andcompletely “fail to work” at the other end, thus constituting alarge set of data that conveys only one piece of information:the location of the transition from “working” to “failing.”Fig. 6 shows that small changes in voltage parameters

VHRS or VLRS can lead to a drastic increase in power.These ‘tipping points’ arise from the turn-on of partiallyselected MIEC ADs, which exponentially increases leakagecurrent, increasing the IR drop along the selected WL andBL, and preventing increases in applied voltage from reach-ing the selected cell. This runaway condition is illustratedin Fig. 7, showing voltage along the selected WL and BLfor varying VHRS. From VHRS =1.08V to 1.32V, the totalvoltage needed externally to ensure the switching of theNVM element increases dramatically from 2.44V to 10.05V,causing runaway power consumption if not outright devicebreakdown.The inset of Fig. 6 plots total write power consumption

vs. VHRS for different stored data patterns. While randompatterns show ‘tipping points’ similar to the worst–case(all devices in LRS state), for the best-case data pattern(all HRS), power consumption remains manageable even at50% higher VHRS. Thus NVM+AD design constraints couldbe partially relaxed for ‘highly asymmetric’ data such assparse matrices or otherwise appropriately-coded data.Fig. 8 plots the dependence of total write power

consumption on VHRS (X-axis) and array size (Y-Axis). Even

FIGURE 7. Voltage along selected WL (+Y-axis) and BL (−Y-axis) as afunction of distance from edge of the array for VHRS = 1.08V (black),1.2V (blue) and 1.32V (red). Small increases in the NVM switching voltagecan cause leakage through partially selected cells and the IR drop alongthe wire to increase to unsustainable levels.

FIGURE 8. Total power consumption as a function of VHRS (X-axis) andarray size (Y-Axis). The sharp vertical transition from low to high powerindicates that small changes in VHRS can have a dramatic impact on themaximum achievable array size.

a 10% reduction in VHRS enables significant benefits in arraysize (1Mb to 2.25Mb) for a given MIEC Access Device.Conversely, a 10% increase in VHRS forces a reduction inarray size by 60%. From these results and the sensitivityanalysis in Fig. 6, we can conclude that reducing NVMswitching voltages will be extremely critical in crossbar sys-tem design, since maximum achievable array size directlytranslates into array efficiency and cost-per-bit. Reducingswitching currents is necessary only to ensure operation ofthe MIEC-based AD in its non-linear regime and to keep IRdrops reasonable.Fig. 9 plots total power consumption as AD parameters

(voltage margin Vm, turn-on slope S, and series resistance Rs)are varied. Similar to VHRS (Fig. 6), a tipping point existsfor the Vm parameter. By reducing the voltage across theselected AD, decreases in Vm reduce the total switchingvoltage and thus might be assumed to lead to lower totalleakage. However, the smaller Vm means that the inner volt-age separation for the un-selected devices must be decreasedto maintain the same un-select leakage, which increases thevoltage across (and thus the leakage through) the partiallyselected cells.Turn-on slope S also has an exponential impact on overall

power, because of the linear relationship between the slope



FIGURE 9. Analogous to the need to keep NVM switching voltage low,large voltage margin Vm (as measured at 10nA), is a more critical AccessDevice parameter than turn-on slope S or effective series resistance Rs.

FIGURE 10. Slight improvements in critical AD parameters can eithera) enable an increase in maximum achievable array size, or b) counteractincreases in line resistance due to technology scaling.

and the total applied voltage. A turn-on slope of ∼60mV/dec(∼30% from nominal, best possible at room temperature)could reduce total power consumption 4-fold. Fig. 10(a)plots the power consumption with increasing array size underfour different AD assumptions: nominal Vm, Vm improvedby 10%, Vm improved by 20% and perfect S. Even asmall improvement in Vm (10%) enables 3× larger arrays(1Mb to 3Mb) for the same power budget. A 20% improve-ment in Vm enables even larger arrays (>4× improvement).There is also tangible benefit to improving the turn-on slope(∼2.5× larger arrays). The increase of line resistance withtechnology scaling is a key challenge for crossbar mem-ories [22], [23]. Fig. 10(b) plots power consumption forincreasing interconnect line resistance, for the same fourAD parameter assumptions. Once again, the Vm parameteris critical — increasing Vm by 20% could counteract as muchas a 5× increase in line resistance (∼11nm technology nodeper ITRS 2011 [21]).Writing multiple bits in parallel into a subarray improves

overall write bandwidth. However, the resulting larger wirecurrents increase interconnect IR drop. Fig. 11(a) plots acolor map of total IR drop (along the selected wordline andbitline) as array size and the number of bits being writtenare increased. Here, we use a ‘safe’ write design point,with insignificant leakage current through partially selected

FIGURE 11. a) Total IR drop increases with both array size and the numberof bits being written in parallel. b) Write power vs. number of bits beingwritten in parallel in a 1Mb array for 3 different voltage marginassumptions.

cells, and select multiple bitlines, evenly spaced across thearray, along a single wordline. Such even spacing incurs alower cumulative IR drop than if the last k-out-of-M bitlineswere to be selected. The plot highlights the tradeoff betweenarea efficiency and write bandwidth — given a ‘maximum’permissible IR drop (say, 1V) for a particular NVM+ADcombination, large arrays require a commensurate reductionin the number of bits being written.Increases in the voltage margin of the AD allows an

increase in write bandwidth, all other parameters stay-ing equal. Fig. 11(b) plots write power consumption fora 1Mb array with nominal, 10% improved Vm, and 20%improved Vm. For nominal Vm, increasing the write par-allelism from 1 to 4 causes a > 12.5× increase in writepower, indicating a significant increase in leakage currentwhereas the corresponding number for 20% improved Vm isonly ∼ 4.5×.

All the above results indicate that array design can ben-efit from improved Vm. One way to double the overallvoltage margin is to use two MIEC ADs in series. Thisapproach would also degrade the turn-on slope and AD seriesresistance by 2×. Before undertaking the difficult task of try-ing to integrate two such MIEC ADs, separated only by athin shared metal electrode, it would be important to knowwhether the one expected positive effect (better Vm) is goingto outweigh the two negative effects (shallower slope andlarger series resistance).Based on the sensitivity analysis above, these negative

effects are indeed outweighed by benefits of the Vm improve-ment. Fig. 12 plots the maximum array size that can beachieved for a given power budget as a function of theNVM switching voltage (VHRS), both for the MIEC AD anda series stack of 2 MIEC ADs. Because the larger Vm out-weighs the increases in (and thus degradation of) turn-onslope and series resistance, the double MIEC could supportNVMs with much higher switching voltages (1Mb arrayseven with switching voltages ∼ 2.4V), and larger array sizes(up to 8Mb) at lower switching voltages. This provides astrong incentive for trying to experimentally implement suchan integrated stacked-MIEC device pair.

C. IMPACT OF VOLTAGE MARGIN VARIABILITYThe impact of Vm variability on write power was studiedusing Monte Carlo simulations. The intent is to study the



FIGURE 12. Maximum array size as a function of NVM switching voltage,for a single MIEC AD and series stack of 2 MIEC ADs.

FIGURE 13. Cumulative Distribution Functions (CDFs) showing thedistribution of write power consumption across 1000 different randomarray configurations, assuming 2%, 3.7% and 10% variation in individualMIEC voltage margin. (Inset) CDF of these assumed voltage margindistributions are compared to the experimental MIEC variability datafrom [13] (black dotted line).

impact of AD variability above and beyond any variability inthe NVM switching voltage. Therefore, in these results, theNVM switching voltage parameter must be interpreted notas the voltage of the median device, but of the worst-casedevice (or the “six-sigma” device).In keeping with experimental data [13] from large (512Kb)

arrays, Vm values for individual ADs in a 1Mb arraywere sampled independently in every Monte Carlo trial. Astandard deviation of 3.7% tracks experimentally observedVm variation {Fig. 13 (inset), [13]}. Standard deviationsof 2% and 10% were also studied. Results indicate thatat 3.7% variability, almost 8% of the trials resulted in writepower > 1mW, whereas at 2% variability, 99.8% of trials fallwithin the 1mW power budget. Further process optimization(e.g., improved Critical Dimension control) is expected tosignificantly reduce the Vm variability beyond that achievedin [13], thus yielding tighter power CDFs.

IV. READ OPERATIONSDuring read operations on a 1AD+1R array (Fig. 14), thevoltages applied at the extremities of the array develop apotential VREAD across an external load resistance RLOAD that

FIGURE 14. Read operation in 1AD+1R array. Under a total applied voltageVW − VB — lower than that used during write, and chosen to avoid eventhe easiest possible (worst-case) read disturb (inset A) — the voltageacross a load resistance at the periphery of the array is used to identify thestate of the selected cell. Insets show worst-case data patterns whilereading the worst-case device (farthest from voltage sources) when B) inthe HRS state, and C) in the LRS state.

depends upon the resistance state of the selected NVM ele-ment. This potential can be measured in various ways usingan appropriate sense amplifier (not shown). Read margin isthe difference between the large voltage that appears acrossRLOAD when the selected NVM is the LRS state, and thesmaller voltage when the selected NVM is in the HRS state.Read margin can be diminished, increasing the possibilityof bit-errors during read, if there is significant sneak pathleakage through partially selected and unselected cells.Design considerations for read operations include the

applied voltages, the biasing scheme for unselected lines,the impact of stored data patterns, and the value of RLOAD.

While a higher applied voltage increases read margin, it iscritical to ensure that no device could possibly change state(undergo read disturb) despite exposure to a large numberof such read events. Experimental work with Resistive RAMhas shown that read disturbs are possible with repeated volt-age stress over multiple cycles, even with applied voltagessignificantly lower than the switching voltage [24]. In thispaper, we assume that the read disturb condition for 106

read operations permits a maximum exposure of any NVMto the voltage VDIS = 0.25×VHRS. While we consider theHRS-to-LRS disturb for positive read voltage (inadvertentSET), our analysis is unchanged if it were the LRS-to-HRStransition that constrained the value of VDIS.

The easiest (and thus worst-case) read disturb occurs atthe cell closest to the voltage sources (Fig. 14, inset A) whenall other NVMs are in the HRS state. With this maximumpermissible applied voltage for read operations, the worst-case read margin can be calculated by reading out LRSand HRS states from the worst-case cell (the one farthestfrom the voltage sources, Fig. 14) under different stored dataconditions (e.g., in Fig. 14, insets B and C).



FIGURE 15. Across eight different bias schemes and all 16 combinationsof possible worst-case data patterns, simulations showed nearly identicalread margins for four schemes. Weak to negligible dependence on storeddata patterns was observed, primarily because of the strong nonlinearityof the MIEC-based Access Device.

A. IMPACT OF BIAS SCHEME AND STORED DATAPATTERNSUnlike the write operation, the worst-case stored data pat-terns for read can depend on the biasing scheme. Fig. 15compares eight different read bias schemes, with circuitdefinitions shown in inset, each named according to howunselected WLs and BLs are biased. Options include Float,All-GND (identical to the V/2 scheme discussed earlier), allline pull-up (ALPU), all line pull-down (ALPD), and variouscombinations. For each read scheme, all 16 possible com-binations of worst-case stored data patterns were evaluatedand the minimum read margin extracted, for three differ-ent RLOAD values (RLRS = 26.67k�,RHRS = 400k� and√RLRS × RHRS = 103k�).Four different read schemes — Float, All GND, BLPU

and WLPD — are shown to have similar read margin. Thereis also no strong dependence of read margin on stored datapatterns. In the remainder of this section, the All-GND (V/2)bias scheme is used for simulating read operations, alongwith the data patterns shown in Fig. 14, insets B and C.

B. CHOICE OF LOAD RESISTANCEThe inset of Fig. 16 plots the dependence of the read marginon the choice of RLOAD. Read margin is maximized at alarger RLOAD [4], [25], but then deteriorates due to voltagedivision between RLOAD and RHRS. When the NVM is inits HRS state, a large voltage drop across the NVM and asmall voltage drop across the load resistance are desirable.However, at high RLOAD values, this condition can no longerbe satisfied, leading to the observed drop-off in read margin.This maxima occurs at RLOAD = 8M�, a relatively high valuebecause of the PF non-linearity of the HRS state. WhileRHRS under switching conditions (VHRS = 1.2V) is 400k�,at lower read voltages the actual sensed RHRS can be muchhigher (we assume a maximum RHRS of 10M� at 0.1V).Large RLOAD also increases read times and read power.

Therefore, rather than operating at maximum RLOAD, it ismore judicious to select the minimum RLOAD required for

FIGURE 16. Sensitivity of read margin to NVM parameters VDIS , RHRSand RLRS . Inset shows plot of read margin vs. RLOAD, which reaches amaximum when the voltage divider between RLOAD and RHRS is balanced.

FIGURE 17. a) Sensitivity of read margin to AD voltage margin and slope.The impact of these parameters on read margin is considerably less criticalthan their impact on write power (compare Fig. 9). b) Read margindeteriorates significantly with decrease in resistance contrast (RHRS/RLRS).Inset: Read margin reduces in a linear fashion with increase ininterconnect resistance.

accurate detection. In the remainder of this section, an RLOADof

√RLRS × RHRS = 103k� is used.

C. SENSITIVITY ANALYSISFig. 16 shows how read margin depends on NVMdisturb voltage VDIS and resistances, RHRS and RLRS.As RHRS and RLRS are varied, NVM currents change but thedisturb voltage (and thus the maximum allowable appliedvoltage during read) remains unchanged. While read mar-gin is insensitive to RHRS and RLRS, the VDIS parameterhas a more significant effect, since it directly impacts themaximum permissible applied voltage.Fig. 17(a) plots read margin sensitivity to changes in AD

voltage margin Vm and turn-on slope S. Read margin candegrade with increasing sneak currents as Vm is decreasedby 30% or more. However, this effect is significantly moresubtle than the commensurate write power constraint, wherea decrease in Vm by even 10% increased total injected powerby orders of magnitude. Similarly, the linear degradation inread margin with increasing turn-on slope is far less criticalthan the exponential increase in write power (see Fig. 9).The inset of Fig. 17(b) plots the impact of increasing

interconnect resistance on the read margin. Once again, alinear impact on read margins is observed, compared to theorders of magnitude increase in write power seen, for even2× increase in interconnect resistance.



FIGURE 18. CDFs showing the variation of read margin under the same2%, 3.7% and 10% variations in voltage margin described in the inset ofFigure 13.

Read margin can be significantly degraded by a reductionin the contrast ratio between RHRS and RLRS [Fig. 17(b)].Here, the ON resistance is progressively increased, reduc-ing the OFF/ON resistance contrast from 15× to 1.5×. (Anohmic I-V is assumed for both RHRS and RLRS states, whichfurther diminishes the read margin.) With low resistance con-trast, as is common with many MRAM elements [2], even“good” ADs are of little help and read-out becomes a signifi-cant challenge that must be addressed through a combinationof novel read schemes and careful sense amplifier design.Fig. 18 plots the impact of Vm variation on read margins.

Under experimentally characterized Vm variability (3.7%),99.8% of trials yielded read margins in excess of 110mV.Even under relatively high Vm variation of 10%, 99.8% oftrials yielded read margins in excess of 75mV. By con-trast, under the same variability assumption, write operationswould be untenable with more than 50% of trials fallingoutside the 1mW power budget.From all of the above results, it is clear that constraints

for read operations are far less stringent than those for write.Furthermore, read margins can potentially be optimized bydesign of the external load resistance and the sense amplifier.In terms of the Access Device, if the AD supports largearrays at reasonable write power, it is quite likely to do anexcellent job at the much easier task of suppressing sneakcurrents from affecting read operations. Conversely, any signof sneak currents (such as read margins that depend on thedata patterns) during read probably indicates that the AccessDevice will simply not be capable of supporting low powerwrite operations.

V. RELATED WORKBuilding large arrays would be impossible without non-linearIV at every crosspoint [26]. Non-linearity can be part of theRRAM itself (selector-less crossbar), or incorporated througha discrete AD/selector device.The impact of RRAM non-linearity on read margin of

selector-less crossbar arrays was studied in [4], but writeoperations and interconnect resistance were not considered.[5], [27] considered both write and read operations, but

non-linearity was studied only with respect to read. Despiteconsidering only small arrays (up to 64×64) write powerwas prohibitively high (>10mW). [25] considered arrays upto 16Kb, but did not study the impact of write power. All ofthe above papers also used percentage read margin as theirdefining metric, which is less important than the absolutesensing voltage difference across an external resistance.Reference [28] considers optimal bias schemes that could

enable larger arrays than a fixed ratio scheme but does notstudy the impact of varying NVM switching current andvoltage.Reference [23] includes large arrays, the impact of inter-

connect resistance, absolute read margins and non-linearityimpact for write operations. However, they also do not studysensitivity to NVM switching voltage nor do they explicitlyaddress write power (instead using a normalized write energymetric). A key finding is that non-linearity of the LRS stateneeds to be carefully tuned to simultaneously meet require-ments for write and read — higher LRS non-linearity, whilebenefiting write operations by reducing sneak path leakage,can diminish read margins by also reducing the effectiveresistance contrast of the RRAM. The requirement of opti-mum non-linearity at the appropriate partial-select voltage,added on top of all other requirements for RRAM includinglow voltage operation, high endurance and retention char-acteristic, low variability etc. makes selector-less RRAMmanufacturing and array design extremely challenging.Reference [29] presented a selector-less RRAM cross-

bar (8×8 sub-arrays) with multi-level SET in one polarityand rectifying behavior with abrupt RESET in the oppositepolarity. This NVM is not expected to scale up to large arraysizes given the ohmic LRS state and low RESET voltage.Reference [30] showed a 2Mb chip with 54nm technologywith 16Kb sub-arrays. The authors mention that lower resetcurrent and higher non-linearity would enable larger arrays,though rigorous circuit analysis is not performed. Anotherselector-less RRAM [31] is also expected to suffer fromhigh sneak path leakage, and the authors discuss a varietyof circuit techniques such as active tuning of the analog biasvoltage, highly asymmetric arrays etc. to manage this [17].1AD1R crossbars can decouple the issue of conflicting

non-linearity requirements - AD characteristics must be opti-mized for sneak path suppression during write, whereasaccurate sensing is possible so long as the NVM has a suf-ficient resistance contrast. References [32]–[37] all quantifyread margins on 1AD1R crossbar arrays without consid-ering write power. As stated earlier, the pitfall is that ifsneak path leakage is appreciable at read voltages, it wouldbe exponentially higher for write operations making powerconsumption prohibitive. Some papers also state that higherAD non-linearity degrades read margins, but this conclusionis often a consequence of assuming that the applied readvoltage will not change with increasing AD non-linearity(which implies lower effective voltage across the NVM).Reference [8] does consider read and write operations but

does not study write power and array sizes are small (4Kb).



References [22] and [38] consider the impact of intercon-nect resistance but do not study the NVM or AD designspace. Similar to our own findings, Mandapati et al. [39]conclude that write power poses the most stringent con-straint for 1AD1R design. However, neither that paper norZhang et al. [40] study sensitivity to individual NVM param-eters such as the switching voltage. While the latter paperdoes consider optimal bias schemes and choice of readvoltage based on disturb conditions, it does not provide jus-tifications for some of its figures of merit such as a highpercentage (25%) read margin requirement. These metricslead to the conclusion that read margin can be more criticalthan write power at certain design points.A 1AD1R, 2-layer RRAM was presented in [18] and [19].

The select device provides a relatively low half-select non-linearity ratio of 150 which implies relatively small sub-arraysizes (16 WLs × 576 BLs across 2 layers) and poor areaefficiency. Reference [20] presented circuit designs for large1D1R sub-arrays with up to 62% area efficiency. HoweverNVM and selector characteristics that could accommodatesuch large arrays were not demonstrated.

VI. CONCLUSIONWe have explored the NVM-AD design space, using exten-sive sensitivity analyzes across device and circuit parameters.For both write and read, we carefully considered bias-ing schemes, interconnect resistance, and the impact ofstored data patterns. From these evaluations, we derive thefollowing key insights:1) Power consumption during write operations poses the

most stringent constraint in determining the maximumarray size that can be achieved for a given AD-NVMcombination, not read margin.

2) Power consumption during write is highly sensitiveto voltage parameters such as the switching voltagesof the NVM and the voltage margin of the AD. Forthese parameters, our simulations show clear ‘tippingpoints,’ beyond which even a small change in the volt-age parameter leads to a several orders-of-magnitudeincrease in write power.

3) Developing ADs with wide voltage margins, and NVMdevices with low switching voltages and reasonableswitching currents, are key requirements for crossbarsystem design. We show that experimentally demon-strated scaled MIEC ADs can support 1Mb arraysof NVMs with switching voltages up to 1.2V. Smallimprovements in Vm can yield significant benefits inarray size. For example, a 20% increase in Vm wasshown to either enable a 4× increase (1Mb to 4Mb)in array size, or to counteract up to a 5× increase inthe interconnect line resistance.

4) While variability can in fact cause the worse-casewrite power or read margin to increase, these effectsremain within tractable bounds for selector variabilitynot much different than what has already been achievedexperimentally.

REFERENCES[1] R. Freitas and W. Wilcke, “Storage-class memory: The next stor-

age system technology,” IBM J. Res. Develop., vol. 52, nos. 4–5,pp. 439–447, Jul. 2008.

[2] G. W. Burr et al., “Overview of candidate device technologies forstorage-class memory,” IBM J. Res. Develop., vol. 52, nos. 4–5,pp. 449–464, Jul. 2008.

[3] G. W. Burr et al., “Access devices for 3-D crosspoint memory,”J. Vac. Sci. Technol. B, vol. 32, no. 4, 2014, Art. ID 040802.

[4] A. Flocke, T. G. Noll, C. Kugeler, C. Nauenheim, and R. Waser,“A fundamental analysis of nano-crossbars with non-linear switchingmaterials and its impact on TiO2 as a resistive layer,” in Proc. 8th IEEEConf. Nanotechnol. (NANO), Arlington, TX, USA, 2008, pp. 319–322.

[5] J. Liang and H.-S. P. Wong, “Cross-point memory array without cellselectors—Device characteristics and data storage pattern dependen-cies,” IEEE Trans. Electron. Devices, vol. 57, no. 10, pp. 2531–2538,Oct. 2010.

[6] Synopsys. HSPICE. [Online]. Available: http://www.synopsys.com/tools/Verification/AMSVerification/CircuitSimulation/HSPICE/Pages/default.aspx

[7] Linear Technologies. LTSPICE. [Online]. Available:http://www.linear.com/solutions/1066

[8] A. Chen, “A comprehensive crossbar array model with solutionsfor line resistance and nonlinear device characteristics,” IEEE Trans.Electron Devices, vol. 60, no. 4, pp. 1318–1326, Apr. 2013.

[9] P. Narayanan et al., “Exploring the design space for resistivenonvolatile memory crossbar arrays with mixed-ionic-electronic-conduction (MIEC)-based access devices,” in Proc. Device Res. Conf.,Santa Barbara, CA, USA, 2014, pp. 239–240.

[10] R. S. Shenoy et al., “MIEC (mixed-ionic-electronic-conduction)-basedaccess devices for non-volatile crossbar memory arrays,” Semicond.Sci. Technol., vol. 29, no. 10, 2014, Art. ID 104005.

[11] K. Gopalakrishnan et al., “Highly-scalable novel access device basedon mixed ionic electronic conduction (MIEC) materials for highdensity phase change memory (PCM) arrays,” in Proc. Symp. VLSITechnol., Honolulu, HI, USA, 2010, pp. 205–206.

[12] R. S. Shenoy et al., “Endurance and scaling trends of novelaccess-devices for multi-layer crosspoint-memory based on mixedionic electronic conduction (MIEC) materials,” in Proc. Symp. VLSITechnol., Honolulu, HI, USA, 2011, pp. 94–95.

[13] G. W. Burr et al., “Large-scale (512kbit) integration of multilayer-ready access-devices based on mixed-ionic-electronic-conduction(MIEC) at 100% yield,” in Proc. Symp. VLSI Technol., Honolulu,HI, USA, 2012, pp. 41–42.

[14] K. Virwani et al., “Sub-30nm scaling and high-speed operation offully-confined access-devices for 3-D crosspoint memory based onmixed-ionic-electronic-conduction (MIEC) materials,” in IEDM Tech.Dig., San Francisco, CA, USA, 2012, pp. 2.7.1–2.7.4.

[15] G. W. Burr et al., “Recovery dynamics and fast (sub–50ns) readoperation with access devices for 3D crosspoint memory basedon mixed-ionic-electronic-conduction (MIEC),” in Proc. Symp. VLSITechnol., Kyoto, Japan, 2013, pp. T66–T67.

[16] P. Narayanan, G. W. Burr, R. S. Shenoy, K. Virwani, and B. Kurdi,“Circuit-level benchmarking of access devices for resistive non-volatile memory arrays,” in Proc. Int. Electron Devices Meeting,San Francisco, CA, USA, 2014, pp. 29.7.1–29.7.4.

[17] B. Bateman, C. Siau, and C. Chevallier, “Low power cross-pointmemory architecture,” in Proc. IEEE Asian Solid State CircuitsConf. (A–SSCC), Jeju, Korea, 2011, pp. 173–176.

[18] A. Kawahara et al., “An 8Mb multi-layered cross-point ReRAM macrowith 443MB/s write throughput,” in Proc. ISSCC, San Francisco, CA,USA, 2012, pp. 432–434.

[19] A. Kawahara et al., “An 8 Mb multi-layered cross-point ReRAMmacro with 443 Mb/s write throughput,” IEEE J. Solid State Circuits,vol. 48, no. 1, pp. 178–185, Jan. 2013.

[20] T.-Y. Liu et al., “A 130.7mm2 2-layer 32Gb ReRAM memory devicein 24nm technology,” in Proc. ISSCC, San Francisco, CA, USA, 2013,pp. 210–211.

[21] (2011). ITRS Interconnect Tables. [Online]. Available:http://www.itrs.net

[22] J. L. Liang, S. Yeh, S. S. Wong, and H. S. P. Wong, “Effect ofwordline/bitline scaling on the performance, energy consumption, andreliability of cross-point memory,” ACM J. Emerg. Technol. Comput.Syst., vol. 9, no. 1, pp. 9:1–9:14, 2013.



[23] D. Niu, C. Xu, N. Muralimanohar, N. P. Jouppi, and Y. Xie, “Designtrade-offs for high density cross-point resistive memory,” in Proc.ACM/IEEE Int. Symp. Low Power Electron. Design, Redondo Beach,CA, USA, 2012, pp. 209–214.

[24] R. Degraeve et al., “Dynamic ‘hour glass’ model for SET and RESETin HfO2 RRAM,” in Proc. Symp. VLSI Technol., Honolulu, HI, USA,2012, pp. 75–76.

[25] A. Chen, “Accessibility of nano-crossbar arrays of resistive switch-ing devices,” in Proc. 11th IEEE Conf. Nanotechnol. (IEEE–NANO),Portland, OR, USA, 2011, pp. 1767–1771.

[26] A. Flocke and T. G. Noll, “Fundamental analysis of resistive nano-crossbars for the use in hybrid nano/CMOS-memory,” in Proc.Eur. Solid State Circuits Conf. (ESSCIRC), Munich, Germany, 2007,pp. 328–331.

[27] J. Liang and H.-S. P. Wong, “Size limitation of cross-point memoryarray and its dependence on data storage pattern and device param-eters,” in Proc. Int. Interconnect Technol. Conf. (IITC), Burlingame,CA, USA, 2010, pp. 1–3.

[28] L. Zhang, S. Cosemans, D. J. Wouters, G. Groeseneken, andM. Jurczak, “Analysis of the effect of cell parameters on the max-imum RRAM array size considering both read and write,” in Proc.ESSDERC, Bordeaux, France, 2012, pp. 282–285.

[29] K. H. Kim et al., “A functional hybrid memristor crossbar-array/CMOS system for data storage and neuromorphic applications,” NanoLett., vol. 12, no. 1, pp. 389–395, 2012.

[30] H. Lee et al., “Integration of 4F2 selector-less crossbar array 2MbReRAM based on transition metal oxides for high density memoryapplications,” in Proc. Symp. VLSI Technol., Honolulu, HI, USA, 2012,pp. 151–152.

[31] C. J. Chevallier et al., “A 0.13μm 64Mb multi-layered conductivemetal-oxide memory,” in Proc. ISSCC, San Francisco, CA, USA, 2010,pp. 260–261.

[32] G. H. Kim et al., “A theoretical model for Schottky diodes forexcluding the sneak current in cross bar array resistive memory,”Nanotechnology, vol. 21, no. 38, 2010, Art. ID 385202.

[33] C. L. Lo, T. H. Hou, M. C. Chen, and J. J. Huang, “Dependenceof read margin on pull-up schemes in high-density one selector-oneresistor crossbar array,” IEEE Trans. Electron Devices, vol. 60, no. 1,pp. 420–426, Jan. 2013.

[34] J. J. Huang, Y. M. Tseng, C. W. Hsu, and T. H. Hou, “Bipolarnonlinear Ni/TiO2/Ni selector for 1S1R crossbar array applications,”IEEE Electron Device Lett., vol. 32, no. 10, pp. 1427–1429, Oct. 2011.

[35] C.-L. Lo, M.-C. Chen, J.-J. Huang, and T.-H. Hou, “On the potentialof CRS, 1D1R, and 1S1R crossbar RRAM for storage-class memory,”in Proc. VLSI–TSA, Hsinchu, Taiwan, 2013, pp. 1–2.

[36] Y. X. Deng et al., “RRAM crossbar array with cell selection device:A device and circuit interaction study,” IEEE Trans. Electron Devices,vol. 60, no. 2, pp. 719–726, Feb. 2013.

[37] J. Zhou, K.-H. Kim, and W. Lu, “Crossbar RRAM arrays: Selectordevice requirements during read operation,” IEEE Trans. ElectronDevices, vol. 61, no. 5, pp. 1369–1376, May 2014.

[38] J. L. Liang, R. G. D. Jeyasingh, H. Y. Chen, and H. S. P. Wong, “Anultra-low reset current cross-point phase change memory with carbonnanotube electrodes,” IEEE Trans. Electron Devices, vol. 59, no. 4,pp. 1155–1163, Apr. 2012.

[39] R. Mandapati et al., “The impact of n-p-n selector based bipo-lar RRAM cross-point on array performance,” IEEE Trans. ElectronDevices, vol. 60, no. 10, pp. 3385–3392, Oct. 2013.

[40] L. Zhang et al., “Selector design considerations and requirementsfor 1S1R RRAM crossbar array,” in Proc. IEEE 6th Int. MemoryWorkshop (IMW), Taipei, Taiwan, May 2014, pp. 1–4.

PRITISH NARAYANAN (M’14) received thePh.D. degree in electrical and computer engineer-ing from the University of Massachusetts Amherst,Amherst, MA, USA, in 2013.

He joined IBM Research—Almaden, San Jose,CA, USA, as a Research Staff Member. His cur-rent research interests include emerging technolo-gies for logic, nonvolatile memory, and cognitivecomputing.

GEOFFREY W. BURR (S’87–M’96–SM’13)received the Ph.D. degree in electrical engineer-ing from the California Institute of Technology,Pasadena, CA, USA, in 1996.

He joined IBM Research—Almaden, San Jose,CA, USA, where he is currently a PrincipalResearch Staff Member. His current researchinterests include nonvolatile memory, neuralnetworks, and cognitive computing.

ROHIT S. SHENOY received the B.Tech. degreein engineering physics from IIT Bombay, Mumbai,India, and the M.S. and Ph.D. degrees in electricalengineering from Stanford University, Stanford,CA, USA.

He was a Research Staff Member with IBMResearch—Almaden, San Jose, CA, USA, from2005 to 2014. He joined Intel, Santa Clara, CA,USA, as a Device Engineer, in 2014, where he isinvolved in NAND flash development.

SAMANTHA STEPHENS received the B.A.degree in physics from Wellesley College,Wellesley, MA, USA, in 2014. She is currentlypursuing the graduate degree in materials sci-ence. She was with IBM Research—Almaden aspart of an APS/IBM Research Internship forUndergraduate Women in 2013.

KUMAR VIRWANI (S’05–M’10) received thePh.D. degree from the University of Arkansas atFayetteville, Fayetteville, AR, USA, in 2007.

He has been with IBM Research—Almaden,San Jose, CA, USA, since 2008. He has devel-oped novel conducting scanning probe microscopymethods for electrical characterization of mixedionic electronic conductor materials and devices.He is involved in projects on storage class mem-ory, lithium-air batteries, low-k dielectrics, andphotovoltaics.

ALVARO PADILLA received the B.S. degreein chemical engineering and the M.S. andPh.D. degrees in electrical engineering from theUniversity of California at Berkeley, Berkeley, CA,USA, in 1997, 2006, and 2008, respectively.

He joined SanDisk, Milpitas, CA, USA, in2014, as a Staff Device Engineer. His currentresearch interests include nanometer-scale mem-ory and logic devices for emerging energy-efficientelectronics.



BÜLENT N. KURDI received the Ph.D. degreefrom the Institute of Optics, University ofRochester, Rochester, NY, USA, in 1989.

He joined IBM Research—Almaden, San Jose,CA, USA. He joined Wavesplitter Technologies,Inc., Fremont, CA, USA, in 2000. Then, hereturned to IBM Research—Almaden, in 2003, asa Manager with the Nanoscale Device IntegrationGroup.

KAILASH GOPALAKRISHNAN (M’04) receivedthe B.S. degree from IIT Bombay, Mumbai, India,and the M.S. and Ph.D. degrees in electrical engi-neering from Stanford University, Stanford, CA,USA.

He has been with the Research Group, IBMT. J. Watson Research Center, Yorktown Heights,NY, USA, since 2013, where he focused on accel-erator microarchitectures. His current researchinterests include device physics, novel logic, andmemory materials and devices.


Documents

Exploring the Design Space for Crossbar Arrays Built With ... · NARAYANAN et al.: EXPLORING THE DESIGN SPACE FOR CROSSBAR ARRAYS BUILT WITH MIEC ADs FIGURE 2. Scaled MIEC Access