Exploration and application deployment on a SoC: efficient application

Workshop - November 2011 - Toulouse

Paul Brelet [email protected]

Exploration and application deployment on a SoC: efficient application

24/11/2011 1

SoCKET Flow

Global SoC Req.

SoCArchitecture

Functional validation

SW Performance Validation

C/C++/ASM

Functionality

Fonctionnalité +

timing

Instruction Set

Simulator

System Requirements

PlatformAssembly

MetricsHLS

SystemProperties

Hardwareproperties

Softwareproperties

TLMLT

TLMAT

Software

Software

Co-simulation/Co-emulation

Silicon SoftwareExecution

HLS

Trafficgenerator

Metrics

IP-XactSoC

Headersgeneration

RTL SoftwareR

eq

uir

em

en

ts t

raceab

ilit

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2

Use case TRT – Description App.Pedestrians detection

Algorithm of classification [Viola&Jones]

Two steps: Off-line: training by an image database On-line: detection by using the training results

Pedestrians tracking in an multi-camera environmentUse of the visual covering of the cameras in order to

carry out the trackingUtilization of descriptors of forms and/or colors in order

to improve the tracking and to manage occlusions

3Workshop - November 2011

Thales use case – App. DescriptionSchematic view of the pedestrian detection


Thales use Case – ArchitectureHost Architecture details


Thales use Case – ArchitectureAccelerator details (Engine)


Thales use Case – Flow

Host Definition: IP-XACT requirements

SystemC/TLM generation

VHDL generation

Architecture Model generation for SPEAR


Thales use Case – Flow Exploration and Simulation:

Architecture SystemC Model generation Architecture Model generation for SPEAR Catch the application on SPEAR C code exists for each SPEAR box (TE) Test of various strategies of application deployment:

Exploration of the level of granularity How calculations are paralleled and which divisions data can be apply to minimize the I/O and to reach the performances

The accelerators are simulated in SystemC from TE C codes


Phase 1: Architecture ExplorationLibrary: SystemC2.2 / TLM2.01

Tools: - SPEAR DE, - Magillem: Packager, Platform Assembly,

MRV Generator.

Validation: Transactional Level.

Links: - IPXACT_2_SPEAR Generator (XSLT Script).


IP-XACTlibrary

IPs

Template JET

Packager MDS

PLT Assembly MDS

TETE

Exploration/ Validation

SpearTE

Spear Applicatio

n

IO API

Spear Model

SystemC Skeleton

client

MRV Generator

IPXACT 2 SPEAR

KO

OK

Thales Flow: Exploration


Phase 2: HW Design Level: RTL.

Tools: - GAUT: Apply on accelerator engines. - Magillem: Packager, Platform Assembly,

Generator Studio. - SPEAR DE: Mapping Validation : Register Level.

Links : - Scripts « bash ».


Template JET

HAL

SystemC Skeleton client

GAUT

VHDL Acc. client

TE

IP-XACTlibrary

PLT Assembly MDS

Application

Spear

Netlister MDS

Vhdl

FPGA

MRV Generator

Generator Studio

Generic client

Validation

Thales Flow: RTL Validation

12

SPEAR DE ToolSPEAR Flow

Application Architecture

Parallelism

Task parallelism

Data parallelism

Tim e / Space

Optim izations

Code generation

M odel

Parallelized application

Functional application

Architecture m odel

Pragmas code/ accelerators

Virtual M achine

SPEAR

Target Architectures (ex: M PPA, G PU)


MAGILLEM ToolRTL Level:

- Bus interface, components creation, link between components: ditto TLM.

VHDL code generation:

- Using generics.

- The code is readable by an individual.

- Inter-connects are taken into account during the VHDL code generation.


GAUT ToolThe C code:

- The C code must be very close to VHDL code.

- Based on gcc4.3.0 for the “cdfgcompiler”Comparison with commercial tools:

- Roccc, ImpulseC.

Some troubles during VHDL code generation:

- The generated code can be synthesizable but it does not work well in placement/routing.


Using graphic interface


Using Bash Script


VHDL code generation


DFG Visualization

Comparison: VHDL code generation

Principe

Results

Minimum between two images

3X3 Convolution Integral Image


OutlinesTo propose the projections of the tools for synthesis: - GAUT is an academic alternative compared to

industrial tools. - MAGILLEM makes it possible to re-use the

IPs blocks.

To consolidate the Thales Design Flow.

To transfer the Thales Design flow to an operational level.


ConclusionTo re-use the IPs blocks:

- Time-saver and productivity in the design of System on Chip.

Validity of new Architecture:

- Allow to check the information processing applications on the desired architecture.


Questions?


Documents

Exploration and application deployment on a SoC: efficient application