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Experimentally reported sub-60mV/decswing in Tunnel FETsswing in Tunnel FETs
?
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• We considered InAs• We considered InAsconventional, lateral transistor architectures:transistor architectures: GAA nanowire,Fin‐FETs (Tri‐gate)Fin FETs (Tri gate)UTB,DG‐SOI
• Analysis is not directly applicable to vertical tunnel FETs embodiments with gate‐field aligned to tunnel direction: g g– G. Zhou et al., in IEDM, 2012, pp. 32.6.1;– L. Lattanzio et al., IEEE T‐ED, 2012, vol. 59, pp. 2932;
2STEEP Transistors Workshop, 2015
– M. Li et al., JAP 2014, p. 074508, 2014.David Esseni
C t d I A G t All A d i MOSFET d TFETCase study: InAs Gate‐All‐Around nanowire MOSFETs and TFETs
• Quasi 2D, semi‐analytical models forthe potential profile: from [R.‐H. Yan et al., TED 1992]to very recent contributions[F. Villani et al. ESSDERC 2014]
• Denoting with φc the potential at the center of the channel and assumingthat the free carrier density in the channel is negligible:
Natural length λ for a quadruple gate, square section nanowire:After C‐W. Lee, et al. , Solid State El t i 505 2006
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Electronics, pp.505, 2006
David Esseni
•At small LG/ the gatecontrol is deterioratedcontrol is deteriorated short channel effects
•MOSFETs in the plot have negligible source‐have negligible source‐drain tunneling effects Universal curve for
h b h
Universal curve forthermionic MOSFETs
After C‐W. Lee et al., Solid State Electronics, pp.505, 2006
What about MOSFETs withsignificant source‐drain
li d l ?4STEEP Transistors Workshop, 2015David Esseni
tunneling and Tunnel FETs ?
60 mV/dec
InAs Tunnel FETs
60 mV/dec
InAs MOSFETs5STEEP Transistors Workshop, 2015David Esseni
InAs MOSFETs
Known T(E) and the subband profile the IDS is given by the Landauer formula Single mode
iexpression
The trasmission coefficient T(E) for tunneling can be obtainedwith the WKB for both intra‐band (MOSFET) and band‐to‐b d t li (T l FET)
MOSFET, OFF stateband‐tunneling (Tunnel FET):
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TFET, OFF stateSTEEP Transistors Workshop, 2015David Esseni
Analytical kim(E) energy relation in the gap based ontwo band Flietner’s model [Flietner, PSSB 1972]:
Eg/2
Maximum KIM(E) results in i i iNumerical k·p a minimum in ITUNN vs. VGS
curves for both MOSFETsd l
Numerical k·pcalculations
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and Tunnel FETs
MOSFET:Vds= 0.3V, Lg = 20nmgSdeg = 0.2eVtsc = 5nm, Nd = 5e19 cm-3
Analysis at 3 bias points:
• Thermionic emission• Minimum IDS• Ambipolar region
8STEEP Transistors Workshop, 2015David Esseni
TFET:Vds= 0.3V, Lg = 20nmds gSdeg = 0.05eV, tsc = 5nm
Analysis at 3 bias points:
• Sub‐threshold region• Minimum IDS• Ambipolar regionAmbipolar region
9STEEP Transistors Workshop, 2015David Esseni
Three‐dimens. NEGF based
d i li d d h
NEGF basednumericalsimulations
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•Source‐drain tunneling degrades SS w.r.t. to the universal curve of thermionic MOSFETs
Three‐dimens. NEGF based
l h /d d b h
NEGF basednumericalsimulations
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•Tunnel FETs have SS<60mV/dec and better thanMOSFETs only for relatively large[LG/] values
Key points: Suppression of tunneling via gate bias is
inherently non monotonic ambipolarityinherently non monotonic ambipolarity For LG approaching 10nm: Tunnel FETs and MOSFETs have analogies in terms of
minimum off current and ambipolarityElectrostatic integrity will not be the only challenge to
achieve a good off-state behaviorIt is dfficult to compete with thermionic MOSFETs, that
is with MOSFETs with suppressed S-D tunneling
Still a lot of room for material and device design
STEEP Transistors Workshop, 2015 12David Esseni
Still a lot of room for material and device design