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EEE 441 LOGICAL DESIGN IILABORATORY

EXPERIMENT#4

COMBINATIONAL CIRCUIT DESIGN II

PRELIMINARY WORK

Mehmet BAYRAM 9610433

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I. Object

In this experiment you will desing, construct and test various combinational circuits, such as ful adders and suptracters, code converters, parity generators and checkers.

II. Preliminary Work

1.

BABBAABD

ABCBAABS

'

''

''

=

+=

=+=

Half Adder with NAND Gates

Half Subtractor with NAND Gates

x y S C D B0 0 0 0 0 00 1 1 0 1 11 0 1 0 1 01 1 0 1 0 0

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2. C S

YZXZXYCZYXS++=

⊕⊕=

3. A B C D W X Y Z W X Y Z A B C D 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 1 0 0 1 0 0 0 1 1 0 0 1 1 0 0 1 0 0 0 1 1 0 0 1 0 0 1 0 0 0 1 1 0 0 1 0 0 0 1 1 1 0 1 0 1 0 1 1 1 0 1 0 1 0 1 1 0 0 1 1 0 0 1 0 1 0 1 1 0 0 1 0 0 0 1 1 1 0 1 0 0 0 1 1 1 0 1 0 1 1 0 0 0 1 1 0 0 1 0 0 0 1 1 1 1 1 0 0 1 1 1 0 1 1 0 0 1 1 1 1 0 1 0 1 0 1 1 1 1 1 0 1 0 1 1 0 0 1 0 1 1 1 1 1 0 1 0 1 1 1 1 0 1 1 1 0 0 1 0 1 0 1 1 0 0 1 0 0 0 1 1 0 1 1 0 1 1 1 1 0 1 1 0 0 1 1 1 1 0 1 0 0 1 1 1 1 0 1 0 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 0 1 0

1 1 1 1

1 11 1

X Y Z S C0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1

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DCCDZCBBCYBAABX

AW

''

''

''

+=

+=

+=

=

ZYXWDWXYYXWXYWYXWC

XWWXBWA

⊕⊕⊕=+′++=

+=

=

'''''

''

4)

1⊕⊕⊕⊕=⊕⊕⊕=

DCBAFDCBAF

odd

even

A B C D F(odd) F(even)0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 1 0 0 1 1 1 0 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 0 1 0 0 1 1 1 0 1 1 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 0 1 1 1 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 1 1 1 1 1 1 0

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4 inputs Even party checker

4 inputs odd part checker