Exam2013 Answers Marking Scheme

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ANSWER SHEET CS2100 Semester 1 AY2013/14 Page 1 of 15

NATIONAL UNIVERSITY OF SINGAPORE

SCHOOL OF COMPUTING

EXAMINATION FORSemester 1 AY2013/14

CS2100 – COMPUTER ORGANISATION

ANSWER SCRIPT

Nov 2013 Time allowed: 2 hours

Your Matriculation Number:

DRAFT ANSWERS

You must write you answers to the questions in the appropriate spaceprovided. Any writing outside the given space will not be considered during

marking.

Begin on the next page.

Q1 Q2 Q3 Q4 Q5 Q6

Total Score /100

Caveat on the grading scheme:

I have given a sample grading scheme in the yellow boxes. However…

you will be surprise how varied the actual answers you guys give. It is not possible

for me to forsee all possible student answers. As such, the stated grading schemes for

each question are mere guidelines. I will need to exercise discretion on the actual

grading itself.



Matric No: ______________________


Answer for Question 1a:

Present State Next State Flip-Flop A Flip-Flop B Flip-Flop C

A B C A B C J A K A JB KB JC KC 0 0 0 0 1 0 0 X 1 X 0 X0 0 1 X X X X X X X X X

0 1 0 1 0 0 1 X X 1 0 X0 1 1 X X X X X X X X X1 0 0 1 1 0 X 0 X 1 0 X1 0 1 X X X X X X X X X1 1 0 0 0 0 X 1 1 X 0 X1 1 1 X X X X X X X X X

J A = B

B

0 X X 1

A X X X X

K A = B

B

X X X X

A 0 X X 1

JB= 1

B

1 X X X

A X X X 1

KB = 1

B

X X X 1

A 1 X X X

JC = 0

B

0 X X 0

A 0 X X 0

KC = 0

B

X X X X

A 0 X X X

Full marks: 10

Grading scheme:

Filling in the table correctly: 3 mark

Six K-maps: 1 mark each

Getting circuit correct: 1 marksAfternote: Some of you has Jc = C by assuming that

the don’t cares are 1. I took away a mark for this

because I feel it is not as simple as 0.





Matric No: ______________________



0x44e13800

Answer for Question 2b:

This is a bad idea because there is only 23 bits of significance in the IEEE singleprecision floating point numbers. So, for example, while the integer 0x01000000 +0x1 is 0x01000001 in integer, in floating point, 0x010000000 is represented by theIEEE single precision number 0x4b800000. When we add 1 (or 1.0) to this number,we still get 0x4b800000.

Afternote: Liu Longyin Eric emailed me to highlight that the question did not say“single precision”. Point noted and I will take this into consideration during marking

but using double-precision (64 bit) to do 32-bit arithmetic is in itself a bad idea.

Answer for Question 2c:

0x47a8cabf is 0100 0111 1010 1000 1100 1010 1011 11112

This is 1.010 1000 1100 1010 1011 11112 x 2(143-127) or 1.010 1000 1100 1010 1011 11112 x 216

0x3f86b723 is 0011 1111 1000 0110 1011 0111 0010 00112

This is 1.000 0110 1011 0111 0010 00112 x 2(127-127) or 1.000 0110 1011 0111 0010 00112

Shifting the smaller number to align the binary point, we have

1. 01010001100101010111111 + 0. 000000000000000100001101011011100100011

Guard bit = 1

Round bit = 0

Sticky bit = 1

Full marks: 3

Grading scheme:

Final answer correct: 2 marks

Working: 1 mark

Full marks: 3

Grading scheme:

Hitting the nail on the precision issue: 2 marks

A good example: 1 mark

Full marks: 3

Grading scheme:

1 mark for each bit (subject to correctness of working)

No working provided or working wrong: ̶ ‒ 1 mark



Matric No: ______________________


Answer for Question 2d:

Performing the addition, we get

1. 01010001100101010111111

+ 0. 00000000000000010000110101----------------------------1. 01010001100101101000101101

Rounding to nearest, we get the result of:

1. 010100011001011010001102 x 216

0100 0111 1010 1000 1100 1011 0100 0110

or 0x47A8CB46

Full marks: 6

Grading scheme:

Performing the addition correctly: 3 marks

(Partial marks for partially correct answer – all will

depend on my estimation of how many percent is the

answer correct.)

Rounding correctly done: 1 mark

Final answer in hex correct: 2 marks

Final answer not presented in hex: ‒ 1 marks



Matric No: ______________________



ori $a2, $s3, -275


xor $t2, $s1, $a1 is equivalent to and $at, $s1, $a1 # s1 AND a1or $t2, $s1, $a1 # s1 OR a1nor $at, $at, $at # NOT(s1 AND a1)and $t2, $t2, $at

(s1 + a1) · (s1 · a1)’ = (s1 + a1) · (s1’ + a1’)

= s1(s1’ + a1’) + a1(s1’ + a1’)

= s1s1’ + s1 a1’ + a1s1’ + a1a1’= 0 + s1 a1’ + a1s1’ + 0= s1 a1’ + a1s1’

= s1 ⊕ a1

Full marks: 3

Grading scheme:

Partial marks for partially correct answer – all will

depend on my estimation of how many percent is the

answer correct.Afternote: in the first version, I had the constant as

“0xFEED”. I will be lenient on this.

Full marks: 5

Grading scheme:


depend on my estimation of how badly wrong is your

answer.



Matric No: ______________________



FINDMIN:

slt $t0, $a1, $0 # Make sure N > 0

bne $t0, $0, OUT # if not, get out

sll $t1, $a1, 2 # Multiply index by 4

add $t0, $a0, $t1 # Address of ARR[N]

lw $v0, -4($t0) # Get ARR[N-1] - make it the current min

addi $t0, $t0, -4 # Advance index to ARR[N-1]

LOOP:

beq $t0, $a0, OUT # Will terminate when we reached ARR[0]

lw $t1, -4($t0) # Get ARR[i-1]

slt $t0, $v0, $t1 # current min < ARR[i-1]?

bne $t0, $0, NEXT # if so, go to next element

addi $v0, $t1, 0 # otherwise, update current min

NEXT:

addi $t0, $t0, -4 # decrement address

j LOOP

OUT:

jr $ra # Current min already in return value $v0

Full marks: 12

Grading scheme:


depend on my estimation of how badly wrong is your

answer.



Matric No: ______________________



The instruction is

beq $t5, $a1, 0x1481

Signal Value

Read reg 1 0xD

Read reg 2 0x5

Write reg X / 0x2

RegDst X

RegWrite 0

ALUSrc 0Branch 1

Address 0

ALUOp 0x2

MemWrite 0

MemRead 0

MemtoReg X

❶ 0x6945204❷ 0x6208

Full marks: 5

Grading scheme:

For each incorrect entry that is not a don’t-care in the answer,

‒ 0.5 marks, subjected to a minimum total mark of 0.



Matric No: ______________________



The shift instructions are R-format instructions. However, in the existing datapath,

the shift amount is not extracted. In order to support the shift instructions, we will

need:

1. The shift amount field to be extracted and passed directly into the ALU.2. Shifters have to be added to the ALU.

3. ALU control must decode shift instructions and issue the appropriate

instructions to the ALU to perform shifting.

4. All other data path is as per R-format instructions.


lui is a I-format instructions. Under the current datapath, RS and the immediate is

passed into the ALU. RT is also handled correctly for writing. So in order to support

the lui instructions:

1. Shifters have to be added to the ALU.

2. ALU control should be modified to instruct the ALU’s shifter to shift the

immediate by 16 bits.

3. The rest of the processing is handled as per I-format instructions.

Full marks: 5

Grading scheme:

Each of these 4 points: 1 mark each

How well the answer is written up: 1 mark

Full marks: 5

Grading scheme:

Points 1 and 3: 1 mark each

Point 2: 2 marks

How well the answer is written up: 1 mark



Matric No: ______________________



Clock Cycle ❶ ❷ ❸ ❹ ❺

i-1 1 1 1 0 0

i 0 0 0 0 1i+1 0 0 0 0 0

No. The situation is not correctly handled. While a NOP was inserted as theload-use hazard was detected, when the load finishes accessing memory, thecurrent hardware only forwards into the ALU as RT. But for a sw instruction, the ALU uses RS and the immediate to compute the address and discards the RT.Instead the incorrect RT read from the register file by the sw instruction iswritten into memory.

Full marks: 4

Grading scheme:Filling up the table correctly: 2 marks

Identifying the issue in the handling: 2 marks



Matric No: ______________________


Answer for Question 5b(i):

The existing load-use hazard mechanism will insert a NOP, and the forwardingneeds to be done as above.

Full marks: 4

Grading scheme:

Identifying the forwarding path correctly: 2 marks

Explaining the solution: 2 marks



Matric No: ______________________


Answer for Question 5b(ii):

The changes are:1. A multiplexor must be added at point 1. This over-rides the value read by the

sw from the register file.2. A new forwarding rule must be added:

if (ID/EX.MemWrite = 1) # i.e., a sw in EXand (MEM/WB.MemRead = 1) # i.e., a lw in WBand (ID/EX.RegisterRt = MEM/WB.RegisterRt)then forward via point 1.

Note that this will require the MemRead command to be passed along to theWB stage.

Note that the NOP insertion is unavoidable even though it seems like it is possible toforward from the WB stage back to the MEM stage. When the lw is in the EX stage,the sw is still being decoded and hence there is no way of telling if it is a lw-swsituation or any other load-use situation.

Answer for Question 5c:0 = “Not taken”, 1 = “Taken”

Initial StateLoop 00BR 00

Iteration 0 (PC at CONT) Loop 00BR 01

Iteration 1 (PC at CONT)

Loop 00BR 00


Full marks: 4Grading scheme:

Identifying the multiplexor to be added and where it is to be

added: 1 mark

The forwarding rule: 2 marks

Detail of description: 1 mark



Matric No: ______________________



•

••



PC at OUT Loop 01BR 00

Full marks: 8

Grading scheme:

Each of the entries before the last two: 0.5 mark each

Last two entries: 1 mark each



Matric No: ______________________



Byte offset = 4 bitsIndex = 10 bitsTag = 18 bits

Each way will need 1 valid bit, 1 dirty bit, 18 bits tag, 4x32 = 128 bits data.Total = 148 bits of storage.

Each set has 4 ways, totaling 4 * 148 = 592 bits.

There are 1024 sets. So the total storage needed to implement the cacheis 1024 *592 bits = 606,208 bits.


Afternote: There is a bug in the ordering of the words in the first version ofthe answers I published. Below is the corrected one.

M[0x80104A3B]

Index Valid Tag Word1 Word0

0 1 0x10020947 0x80104A3C 0x80104A381

2

3

Hit Miss

M[0x04008112]


0 1 0x10020947 0x80104A3C 0x80104A381 1 0x801022 0x04008114 0x040081102

3

Hit Miss

Full marks: 3

Grading scheme:

Getting the number of bits for each field correct: 1 mark

Getting the total for each set correct: 1 mark

Getting the total correct: 1 mark



Matric No: ______________________


M[0x80104A9B]


0 1 0x10020947 0x80104A3C 0x80104A381 1 0x801022 0x04008114 0x04008110

2 1 0x10020953 0x80104A9C 0x80104A983

Hit Miss

M[0x04008118]


0 1 0x10020947 0x80104A3C 0x80104A381 1 0x801022 0x04008114 0x040081102 1 0x10020953 0x80104A9C 0x80104A98

3 1 0x801023 0x0400811C 0x04008118Hit Miss

M[0x80104A38]


0 1 0x10020947 0x80104A3C 0x80104A381 1 0x801022 0x04008114 0x040081102 1 0x10020953 0x80104A9C 0x80104A983 1 0x801023 0x0400811C 0x04008118

Hit Miss

M[0x0071881A]


0 1 0x10020947 0x80104A3C 0x80104A381 1 0xE3103 0x0071881C 0x007188182 1 0x10020953 0x80104A9C 0x80104A983 1 0x801023 0x0400811C 0x04008118

Hit Miss

‒‒‒ End of Answer Sheet ‒‒‒

Full marks: 12Grading scheme:

Two marks for each reference.

For each reference, correctly identifying hit or miss is 0.5

mark, the rest is for getting the hexadecimal entry correct.

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Exam2013 Answers Marking Scheme