Evaluates: MAX11150/MAX11152/MAX11158/ Evaluation Kit ... · Evaluates: MAX11150/MAX11152/MAX11158/ MAX11160/MAX11161/MAX11162/MAX11163/ MAX11168/MAX11169 MAX1115X/MAX1116X Family

Evaluates: MAX11150/MAX11152/MAX11158/MAX11160/MAX11161/MAX11162/MAX11163/

MAX11168/MAX11169

MAX1115X/MAX1116X Family Evaluation Kit

General DescriptionThe evaluation kit (EV kit) demonstrates the MAX1115X/MAX1116X family of 18-/16-bit SAR ADCs. The EV kit includes a graphical user interface (GUI) that provides communication from the target device to the PC. The EV kit can operate in multiple modes:1) Standalone Mode: In “standalone” mode, the EV kit

is connected to the PC via a USB cable and performs a subset of the complete EV kit functions with limita-tion for sample rate, sample size, and no support for coherent sampling.

2) FPGA Mode: In “FPGA” mode, the EV kit is connect-ed to an Avnet ZedBoard™ through a low-pin-count FMC connector. The ZedBoard features a Xilinx® Zynq® -7000 SoC, that connects to the PC through an Ethernet port, which allows the GUI to perform different operations with full control over mezzanine card functions. The EV kit with FPGA platform per-forms the complete suite of evaluation tests for the target IC.

3) User-Supplied SPI Mode: In addition to the USB and FMC interfaces, the EV kit provides a 12-pin PMOD-style header for user-supplied SPI interface to connect the signals for SCLKx, DINx, DOUTx, and CNVSTx.

The EV kit includes Windows XP®-, Windows® 7, and Windows 8.1-compatible software for exercising the fea-tures of the IC. The EV kit GUI allows different sample sizes, adjustable sampling rates, internal or external ref-erence options (depending upon target device selected), and graphing software that includes the FFT and histo-gram of the sampled signals. The ZedBoard board accepts a +12V AC-DC wall adapter. The EV kit can be powered by a local +20V supply. The EV kit has on-board transformers and digital isolators to separate the IC from the ZedBoard/on-board processor.The MAX1115X/MAX1116X EV kit comes installed with a MAX1115XEUB+/MAX1116XEUB+ in a 10-pin µMAX® package, but can also evaluate other pin-compatible parts in the family. For a full list of products supported by this EV kit, see Table 4.

Features ● High-Speed USB Connector, FMC Connector, and

PMOD-Style Connector ● 75MHz SPI Clock Capability through FMC Connector ● 10MHz SPI Clock Capability in Standalone Mode ● Various Sample Sizes and Sample Rates (Up to

500ksps) ● Collects Up to 1 Million samples (with FPGA

Platform) ● Time Domain, Frequency Domain, and Histogram

Plotting ● Sync In/Out for Coherent Sampling (with FPGA plat-

form) ● On-Board Input Buffers (MAX9632 and MAX44242) ● On-Board Voltage References (MAX6126 and

MAX6070) ● Proven PCB Layout ● Fully Assembled and Tested ● Windows XP-, Windows 7-, and Windows

8.1-Compatible Software

19-7582; Rev 0; 5/15

Ordering Information appears at end of data sheet.

ZedBoard is a trademark of Avnet, Inc.Xilinx and Zynq are registered trademarks of Xilinx, Inc.Windows XP and Windows are registered trademarks and reg-istered service marks of Microsoft Corporation. µMAX is a registered trademark of Maxim Integrated Products, Inc.

EV Kit Photo

Maxim Integrated │ 2www.maximintegrated.com

Evaluates: MAX11150/MAX11152/MAX11158/MAX11160/MAX11161/MAX11162/

MAX11163/MAX11168/MAX11169


Quick StartRequired Equipment

● MAX1115X/MAX1116X EV kit ● +20V (500mA) power supply ● Micro-USB cable ● ZedBoard development board ● Function generator (optional) ● DMM (for calibration – optional) ● Windows XP, Windows 7, or Windows 8.1 PC with a

spare USB portNote: In the following section(s), software-related items are identified by bolding. Text in bold refers to items direct-ly from the EV system software. Text in bold and under-line refers to items from the Windows operating system.

ProcedureThe EV kit is fully assembled and tested. Follow the steps below to verify board operation:1) Visit http://www.maxim-ic.com/evkitsoftware to

download the latest version of the EV kit software, MAX1115X_6XEVK.ZIP. Save the EV kit software to a temporary folder and uncompress the ZIP file.

2) Install the EV kit software and USB driver on your com-puter by running the MAX1115X_6XEVKitSetupV1.0.exe program inside the temporary folder. The program files are copied to your PC and icons are created in the Windows Start | Programs menu. At the end of the installation process, the installer will launch the installer for the FTDIChip CDM drivers.

-+MAX9632 U10

ADC # 1-+

MAX44242-+

MAX44242

SCLK1CNVST1

DIN1DOUT1

-+

MAX9632-+

MAX9632 U14ADC # 2

-+

MAX44242-+

MAX44242

SCLKCNVSTDIN

DOUT

SCLK1CNVST1SCLK2CNVST2

DOUT2

FMC

HEADER

USB

FPGA - ZedBoard

USER-SUPPLIED SPI

PC - USB

SYNC IN, SYNC OUT

MAX6126

MAX6070

ADC_EXT_REFVREF1_ADC

VREF2_ADC

DOUT_DAISY

+3.3V/+2.5V

+3.3V/+2.5VGND

-+

MAX9632ISOLATED

DC-DC

ISOLATION

FTDI

FILE DESCRIPTIONMAX1115X_6XEVKitSetupV1.0.exe Application Program (GUI)

Boot.bin ZedBoard firmware (SD card to boot Zynq)

System Block Diagram

MAX1115X/MAX1116X EV Kit Files



MAX11163/MAX11168/MAX11169


For Standalone Mode:1) Verify that all jumpers are in their default positions for

the EV kit board (Table 2).2) Connect the PC to the EV kit using a micro USB cable.3) Connect the +20V adapter to the EV kit.4) Start the EV kit software by opening its icon in the

Start | Programs menu. The EV kit software appears in Figure 1.

5) The software should automatically connect to the hardware and display EV kit Hardware Connected in the Status bar. If it does not connect, then from the Device menu, select Standalone and click Search for USB Device. Then select Standalone again and select a device in the list. Verify that the lower right status bar indicates the EV kit hardware is Connect-ed.

For FPGA Mode (When Connected to a Zedboard):1) Connect the Ethernet cable from the PC to the Zed-

Board and configure the Internet Protocol Version 4 (TCP/Ipv4) properties in the local area connec-tion to IP address 192.168.1.2 and subnet mask to 255.255.255.0.

2) Verify that the ZedBoard SD card contains the Boot.bin file for the MAX1115X/MAX1116X EV kit.

3) Connect the EV kit FMC connector to the ZedBoard FMC connector. Gently press them together.

4) Verify that all jumpers are in their default positions for the ZedBoard (Table 1) and EV kit board (Table 2).

5) Connect the 12V power supply to the ZedBoard. Leave the Zedboard powered off.

6) Enable the ZedBoard power supply by sliding SW8 to ON and connect the +20V adapter to the EV kit.

7) Start the EV kit software by opening its icon in the Start | Programs menu. The EV kit software appears as shown in Figure 1. From the Device menu select FPGA. Verify that the lower right status bar indicates the EV Kit hardware is Connected.

For Either Standalone or FPGA Mode:1) Connect the positive terminal of the function genera-

tor to the AIN0+ (TP2) test point on the EV kit. Con-nect the negative terminal of the function generator to the AIN0- (TP1) test point on the EV kit.

2) Configure the signal source to generate a 1kHz, 1VP-P sinusoidal wave with +500mV offset.

3) Turn on the function generator.4) In the Configuration group, select Device to match

IC type, select Channel 1 and then click Capture. 5) Click on the Scope tab.6) Check the Remove DC Offset checkbox to remove

the DC component of the sampled data.7) Click the Capture button to start the data analysis.

The default sample size is 8192.8) The EV kit software appears as shown in Figure 1.9) Verify the frequency is approximately 1kHz is dis-

played on the right. The scope image has buttons in the upper right corner that allow zooming in to detail.

Table 1. ZedBoard Jumper Settings JUMPER SHUNT POSITION DESCRIPTION

J18 1-2 VDDIO set for 3.3V.

JP11 JP10JP9JP8JP7

JP10

2-31-21-22-32-3

Boot from SD card

J12 — SD card installed

J20 — Connected to 12V wall adapter

SW8 OFF ZedBoard power switch, OFF while connecting boards



MAX11163/MAX11168/MAX11169


Table 2. EV kit Jumper Settings†

JUMPER JUMPER POSITION DESCRIPTION

J3 (Red)OPEN* Set output of U5 to 3.3V

1-2 Set output of U5 to 2.5V

J4 (Red)1-2 Power U23 with 12V for 5V FPGA power (Do not populate 1-2 and 3-4 at same time)

3-4* Power U23 with 20V for 5V FPGA power (Do not populate 1-2 and 3-4 at same time)

J5 (Black)1-2* Connect BIN0- to AGND

3-4 Connect BIN0+ to AGND





J8 (Red)1-2 Power U20 with +12V from FPGA

3-4* Power U20 with 5V from USB



J10 (Black)

1-2 Connects output of U27 (BIN0) to inverting input of U28

3-4* Connects BIN1- to inverting input of U28

5-6* Connects output of U27 (BIN0) to noninverting input of U28

7-8 Connects BIN1+ to noninverting input of U28

J11 (Black)

1-2 Connects output of U26A (BIN2) to inverting input of U26B

3-4* Connects BIN3- to inverting input of U26B

5-6* Connects output of U26A (BIN2) to noninverting input of U28

7-8 Connects BIN3+ to noninverting input of U28

J12 (Black)OPEN Disable on-board power supplies

1-2* Enable on-board power supplies

J13 (Black)

OPEN* User connect external reference to TP12 – ADC_EXT_REF (If the target device has an internal reference J13 should be left open)

1-2 MAX6070 is VREF source

2-3** MAX6126 is VREF source

J14 (Red)OPEN Disable +3V3_USB power for FTDI chip

1-2* Enable +3V3_USB power for FTDI chip

J15 (Red)1-2 Power U2 from EXTERNAL +18V source

3-4* Power U2 from T1 +18V output

J16 (Red)1-2 Power U3 from EXTERNAL -18V source

3-4* Power U3 from T2 -18V output

J17 (Red)1-2 Use external +10V applied at TP9

3-4* Use U2 output for +10V, 100mA supply

J19 (Black)1-2* Connect U10 SDI to DVDD (CS mode)

3-4 Connect U10 SDI to U14 SDO (daisy-chain mode)



MAX11163/MAX11168/MAX11169


Table 2. EV kit Jumper Settings† (continued)


J20 (Black)1-2 Connects U10 SDO to DVDD (enable busy bit)

OPEN* No pullup on U10 SDO

J21 — ADC2 SPI Port Test Points (header – no jumpers)

J22 — ADC1 SPI Port Test Points (header – no jumpers)

J23 — Serial EEPROM Test Points (header – no jumpers)

J24 (Red)

1-2 Changes the -10V supply to ground

3-4 -10V supplied by external test point (TP23)

5-6* -10V supplied by U3

J25 — PMOD-style connector. Connects to ADC1 and ADC2 SPI ports, 12 pins (no jumpers).

J26 (Red)1-2 +15V supplied from external test point (TP38)

3-4* +15V supplied by U6

J27 (Red)

1-2 Changes the -15V supply to ground

3-4 -15V supplied by external test point (TP37)

5-6* -15V supplied by U13

J28 (Black)1-2* Connect AIN0- to AGND

3-4 Connect AIN0+ to AGND





J32 (Black)

1-2 Connect U7 output (AIN0) to U8 inverting input

3-4* Connect AIN1- to U8 inverting input

5-6* Connect U7 output (AIN0) to U8 noninverting input

7-8 Connect AIN1+ to U8 noninverting input



J34 (Black)

1-2* Connect U8 output to U10 AIN+

3-4 Connect U9B output to U10 AIN+

5-6 Connect GND_SENSE (TP26) to U10 AIN-

7-8* Connect U10 AIN- to AGND

J35 (Black)

1-2 Connect U14 CVNST to CNVST1_ADC

3-4* Connect U14 CVNST to CNVST2_ADC

5-6 Connect U14 SCLK to SCLK1_ADC

7-8* Connect U14 SCLK to SCLK2_ADC

9-10 Connect U14 SDI to AGND

11-12* Connect U14 SDI to DVDD



MAX11163/MAX11168/MAX11169


Table 2. EV kit Jumper Settings† (continued)


J36 (Black)

1-2 Connect U9A output (AIN2) to U9B inverting input

3-4* Connect AIN3- to U9B inverting input

5-6* Connect U9A output (AIN2) to U9B noninverting input

7-8 Connect AIN3+ to U9B noninverting input

J37 (Black)

1-2** Connect ADC_EXT_REF to U10 REF (ADC1)

3-4 Connect ADC_EXT_REF to U9 VREF2




11-12** Connect ADC_EXT_REF to U14 REF (ADC2)

J38 (Bue)1-2* Connect U14 SDO to DOUT2_ADC

3-4 Connect U14 SDO to DOUT_DAISY

J39 (Black)

1-2* Connect U28 output to U14 AIN+

3-4 Connect U26B output to U14 AIN+

5-6 Connect GND_SENSE to U14 AIN-

7-8* Connect AGND to U14 AIN-

†Red test points and red jumpers are used for power settings. Black test points are used for ground points, white test points are used for all signal points, black jumper for I/O settings.*Default positions**If the target ADC requires an external reference this should be populated (MAX11152 and MAX11162)



MAX11163/MAX11168/MAX11169


General Description of SoftwareThe main window of the EV kit software contains five tabs: Configuration, Scope, DMM, Histogram, and FFT. The Configuration tab provides control for the two ADCs configuration during data capture. The other four tabs are used for evaluating the data captured by the ADCs. In addition, the sample data can be saved to a file.

Configuration TabThe Configuration tab provides an interface for selecting and configuring the ADC from a functional perspective. Select the desired Device in the drop-down list and the corresponding properties of the device are displayed including Resolution, Input Range, Reference Voltage, and Max Sample Rate. If the selected ADC uses an external reference, then use the Reference Voltage numeric box to enter the measured reference value. The on-board reference is 5V. The sampling settings are available on the left, which allow the user to select the Channel, Sample Rate, Number of Samples, and SCLK Frequency. The SCLK Frequency selection is required prior to adjusting to the desired sampling rate.The two ADCs on the EV kit have a variety of interface modes to the master. The modes include CS mode and daisy-chain mode.

CS Mode (Single ADC Mode) The factory-default jumper settings have the ADCs on the EV kit configured for CS mode, using the Channel 1 device (U10) and Channel 2 device (U14). In the Configuration tab the correct selection must be made for CS Mode. If the busy bit is desired, select CS Mode with Busy and populate J20.

Daisy-Chain Mode To use the ADCs in daisy-chain mode, move the shunts described in Table 3 for J19 and J38 so the SDO of U14 (DOUT2_DAISY) connects to the SDI of U10. The SDO of U10 connects to the SPI MISO for the GUI to read the data. In the Configuration tab, the correct selection must be made for Interface Mode set as Daisy-chain. The channel selection automatically changes to Both Channels in daisy-chain mode.

Dual ADC Mode (Sequential or Simultaneous)There are two ADCs on the EV kit. In standalone mode, the two ADCs are read sequentially, while in FPGA mode they can be read simultaneously. To use the ADCs in multichannel mode, move the shunts described in Table 3 for CS Mode. In the Configuration tab, the correct selec-tion must be made for Both Channels and the Interface Mode must be in CS mode.

Table 3. Interface Mode Jumper SettingsINTERFACE MODE J35 J38 J19 J20

CS Mode, No Busy CNVST2 (3-4), SCLK2 (7-8), DVDD (11-12) DOUT2 (1-2) DVDD (1-2) OPEN

CS Mode, With Busy CNVST2 (3-4), SCLK2 (7-8), DVDD (11-12) DOUT2 (1-2) DVDD (1-2) SHORT

Daisy Chain CNVST1 (1-2), SCLK1 (5-6), AGND (9-10) DOUT_DAISY (3-4) DOUT_DAISY (3-4) OPEN



MAX11163/MAX11168/MAX11169


System CalibrationThe purpose of this procedure is to calculate coefficients to compensate gain and offset error. This procedure allows the calibration using any two points that fit the input voltage range. A DC supply and DMM is required for this procedure.1) Measure the zero-scale and full-scale signal applied

at the input of the EV kit.2) Enter the voltage values into the Input Measured

(V) Min and Max numeric boxes (±5V or ±10V de-pending upon the ADC device on the EV kit).

3) Apply a zero-scale signal (-5V or -10V depending upon ADC device on the EV kit) to the ADC inputs and click Read Data.

4) Enter the Data (V) value into the ADC Data Read (V) Min numeric box.

5) Apply a full-scale signal (+5V or +10V depending upon ADC device on the EV kit) to the ADC inputs and click Read Data.

6) Enter the Data (V) value into the ADC Data Read (V) Max numeric box.

7) Click Calculate.8) The GUI will adjust the Gain Coefficient value and

Offset (mV) value. 9) Software calibration is enabled by checking the En-

able Calibration checkbox. This calibration is used for measurements taken with the Scope, DMM, Histogram, and FFT tabs.

Figure 1. EV Kit Software (Configuration Tab)



MAX11163/MAX11168/MAX11169


Scope TabThe Scope tab sheet is used to capture data and display it in the time domain. Sampling rate and number of samples can also be set in this tab if they were not appropriately adjusted in other tabs. The Display Unit drop-down list

allows counts and voltages. Once the desired configuration is set, click on the Capture button. The right side of the tab sheet displays details of the waveform, such as average, standard deviation, maximum, minimum, and fundamental frequency. Figure 2 displays the ADC data when a sinusoidal signal is applied to the inputs on the EV kit.

Figure 2. EV Kit Software (Scope Tab)



MAX11163/MAX11168/MAX11169


DMM TabThe DMM tab sheet provides the typical information as a digital multimeter. Once the desired configuration is set, click on the Capture button.

Figure 3. EV Kit Software (DMM Tab)



MAX11163/MAX11168/MAX11169


Histogram TabThe Histogram tab sheet is used to capture the histogram of the data. Sampling rate and number of samples can also be set in this tab if they were not appropriately adjusted in other tabs. Once the desired configuration is set, click on the Capture button. The right side of the tab

sheet displays details of the histogram such as average, standard deviation, maximum, minimum, peak-to-peak noise, effective resolution, and noise-free resolution. Figure 4 shows data when inputs AIN0+ and AIN0- are connected to GND.

Figure 4. EV Kit Software (Histogram Tab)



MAX11163/MAX11168/MAX11169


FFT TabThe FFT tab sheet is used to display the FFT of the data. Sampling rate and number of samples can also be set in this tab if they were not appropriately adjusted in other tabs. Once the desired configuration is set, click on the Capture button. The right side of the tab displays the performance based on the FFT, such as fundamental frequency, SNR, SINAD, THD, SFDR, ENOB, and noise floor.

When coherent sampling is needed, this tab allows the user to calculate the input frequency or the master clock coming into the board. Either adjust the input frequency applied to the signal generator or adjust the master applied to the SYNC_IN SMA connector. See the Sync Input and Sync Output section before using this feature. Figure 13 shows the setup Maxim Integrated uses to cap-ture data for coherent sampling.

Figure 5. EV Kit Software (FFT Tab)



MAX11163/MAX11168/MAX11169


Detailed Description of Hardware The MAX1115X/MAX1116X EV kit provides a proven signal path to demonstrate the performance of the MAX1115X/MAX1116X 18-/16-bit SAR ADCs. Included in the EV kit are digital isolators, isolated DC-DC converters, ultra-low-noise LDOs to all supply pins of the IC, on-board references (MAX6126 and MAX6070), precision ampli-fiers (MAX9632 for bipolar and MAX44242 for unipolar) for analog inputs, and sync-in and sync-out signals for coherent sampling. Two ADCs are on the board to allow daisy-chain mode operation if desired.An on-board FTDI controller is provided to allow for evaluation in standalone mode, which has limitations on maximum sample speed and on sample depth. The EV

kit can be used with a FPGA to achieve full speed and a larger sample depth.The EV kit supports a number of different devices with a 10-pin µMAX package as listed in Table 4.For the MAX11156 and MAX11154 in a 12-pin TDFN package, please refer to the MAX11156EVSYS# and for the MAX11166, MAX11167, MAX11164, and MAX11165 in a 12-pin TDFN package, please refer to the MAX11166EVSYS#. A full 18-bit data acquisition system featuring the MAX11156 ADC and the MAX5318 DAC is available as the MAXREFDES74# reference design, which includes an FMC interface to the FPGA and stand-alone USB.

Table 4. Products Supported with MAX1115X/MAX1116X EV Kit

PART NO. RESOLUTION (BITS)

MAX. SAMPLE RATE (ksps)

INPUT RANGE (V)

VOLTAGE REFERENCE

MAX11150 18 500 0 to +5 Internal REF

MAX11152 18 500 0 to +5 External REF

MAX11158 18 500 ±5 Internal REF

MAX11160 (MAX11161) 16 500 (250) 0 to +5 Internal REF

MAX11162 (MAX11163) 16 500 (250) 0 to +5 External REF

MAX11168 (MAX11169) 16 500 (250) ±5 Internal REF



MAX11163/MAX11168/MAX11169


USB InterfaceThe maximum sample rate is 250ksps and the maximum sample size is 16384.

FMC InterfaceThe user should confirm compatibility of pin usage between their own FMC implementation and that of the MAX1115X/MAX1116X EV kit before connecting the MAX1115X/MAX1116X EV kit to a different system with FMC connectors.

User-Supplied SPI InterfaceIn addition to the USB and FMC interfaces, the EV kit pro-vides a 12-pin PMOD-style header (J25) for user-supplied SPI interface. To evaluate the EV kit with a user-supplied SPI bus, disconnect from the FMC bus and remove jumper J14. Apply the user-supplied SPI signals to SCLK, CNVST, DIN, and DOUT at the PMOD header. Make sure the return ground is connected to the PMOD ground. The on-board FTDI chip used for standalone mode does not conflict with the user-supplied SPI if it is powered off by removing jumper J14.WARNING: DO NOT PLUG THIS HEADER INTO A STANDARD PMOD INTERFACE FOUND ON OTHER FPGA OR MICROCONTROLLER PRODUCTS. THE SIGNAL DEFINITION IS UNIQUE TO THIS EV KIT.

Reference Depending upon the target IC on the EV kit, there are different sources for the voltage reference. As listed in Table 4, some ADCs have the option to use an internal reference. In addition, there are two voltage references on the board and the option to provide a user-supplied external reference signal.For ADCs that require an external reference, the EV kit includes two on-board references plus the option for a user-supplied reference. The MAX6126 (U11) is an ultra-high-precision, ultra-low-noise, series voltage reference with 3ppm/°C maximum temperature coefficient and the MAX6070 (U12) low-noise, high-precision series voltage reference offers the highest performance SOT23 voltage references with 6ppm/°C maximum temperature coefficient. To use these voltage reference sources, populate jump-ers J13 and J37. See Table 5 for jumper settings.For a user-supplied external reference, remove the jumper on J13 and connect a reference voltage to ADC_EXT_REF at TP12. Measure and enter the value of the external reference voltage into the Reference Voltage edit box on the Configuration tab of the GUI. When using devices with an internal reference, remove all jumpers from J13 and J37.

Table 5. Reference Source OptionsREF SOURCE JUMPER CONNECTION FUNCTION

MAX6070J13 1-2 Select U12 MAX6070

J37 1-2 and 11-12 VREF1_ADC, VREF2_ADC

MAX6126J13 2-3 Select U11 MAX6126


EXT_REF (TP12)J13 OPEN Select ADC_EXT_REF


INT_REFJ13 OPEN —

J37 OPEN MAX11150/MAX11158/MAX11160/MAX11168 only



MAX11163/MAX11168/MAX11169


User-Supplied Power Supply The EV kit receives power from a single DC source of 20V, 500mA through a J1 power jack. The MAX13256, H-bridge driver and transformer create an additional negative rail for +18V and -18V. The power is then recti-fied and regulated down to a +15V and -15V supplies

for the MAX9632 op amps, as well +10V and -10V sup-plies for the MAX44242 op amps. Additional supplies are generated for +5V, +5.33V, and +3.3V/+2.5 for the ADCs and VREF. See the EV kit schematics for details. Specific voltages can be connected to the board for each rail, see Table 6 for corresponding jumper positions.

Table 6. Power Supply to the BoardPOWER INPUT CONNECTORS JUMPERS

Single +20V input from a wall adapter (default) J1

J12: 1-2J15: 3-4J16: 3-4J26: 3-4J27: 5-6J17: 3-4J24: 5-6

An external ±18V TP35 (+18V)TP30 (-18V)

J12: OpenJ15: 1-2J16: 1-2J26: 3-4J27: 5-6J17: 3-4J24: 5-6


J12: OpenJ15: OpenJ16: OpenJ26: 1-2J27: 3-4J17: 3-4J24: 5-6


J12: OpenJ15: OpenJ16: OpenJ26: 3-4J27: 5-6J17: 1-2J24: 3-4



MAX11163/MAX11168/MAX11169


Analog Input Voltage RangesThe MAX1115X/MAX1116X are 18-/16-bit, single-chan-nel, pseudo-differential ADCs. The ADCs convert input signals on the ADC pin AIN+ (ADx_INP) in the range of (±5V + AIN-) for bipolar or (5V + AIN-) to AIN- for unipolar. For accurate conversions, the ADC pin AIN+ should also be limited to ±(VDD + 0.1V) for bipolar and (VDD + 0.1V) to -0.1V for unipolar. The ADC pin AIN- (ADx_INM) has an input range of -0.1V to +0.1V and is typically connected to the analog ground plane (AGND) of the EV kit. The MAX1115X/MAX1116X perform a true differential sample on inputs between AIN+ and AIN- with good common-mode rejection and by connecting the EV kit input signal GND_SENSE to the ground reference of the input signal source. This allows for improved sampling of remote transducer inputs. See the jumper settings in Table 2 for J34 and J39.

ADC Input AmplifiersThe input amplifiers allow for significant flexibility, support-ing bipolar or unipolar input paths, as well as the option

for gain control. Each ADC channel can be configured as single-ended bipolar, differential bipolar, single-ended unipolar, and differential unipolar. See Tables 8 and 9 for these analog input configurations for channels A and B, respectively.The analog front-end consists of two channels (A and B, one for each ADC) and for each channel there are four user-selectable input pairs (for example AINx+ and AINx- where x is 0, 1, 2, or 3) allowing selection between one of two op amp solutions. The MAX9632, which is a 36V, pre-cision, low-noise, wide-band amplifier or the MAX44242, which is a 20V, low input-bias-current, low-noise, dual op amp. The op amps can be configured as inverting or noninverting amplifiers by jumper selectors. Both op amps work as anti-aliasing lowpass filters (LPF) and can be daisy-chained to create a second-order LPF. The range of possible configurations for Channels A and B are listed in Tables 8 and 9, and the jumper connections are shown in Figures 6 to 12.

Table 7. Analog Input Voltage Ranges

ADC ADC INPUT RANGE

MAX9632 INPUT RANGE

MAX44242 INPUT RANGE COMMENTS

MAX11158, MAX11168 ±5V ±10V ±10V Beyond-the-Rail ADCs work from

unipolar supply

MAX11150,MAX11152,MAX11160,MAX11162

0 to +5V

±5V VREF1 bias’s common mode for U8 (MAX9632) at 2.5V.VREF3 bias’s common mode for U28 (MAX9632) at 2.5V

±5V VREF2 bias’s common mode for U9 (MAX44242) at 2.5V.VREF4 bias’s common mode for U26 (MAX44242) at 2.5V

VREF is used to bias the op amp common mode to support 0 to +5V input to the ADC.The first ADC (U10) Common Mode (CM) bias is set with VREF1 and VREF2 depending upon the op amp selected, and the second ADC (U14) CM bias is set with VREF3 and VREF4 depending upon the op amp selected.



MAX11163/MAX11168/MAX11169


Table 8. Analog Input Configurations (Channel A0–A3)CONFIGURATION SIGNAL-PATH INPUT

CONFIGURATION INPUT CONNECTORS JUMPER POSITIONSNO. DESCRIPTION

1 MAX9632, Channel A0 Noninverting, single-ended, second-order LPF (default)

CON3: AIN0+ (or TP2) and AGND (or TP8)

J28: 1-2 J29: 1-2 J32: 5-6 and 3-4 J34: 1-2 and 7-8

2 MAX9632, Channel A0 Noninverting, differential, second-order LPF

CON3 (TP2): AIN0+ CON2 (TP1): AIN0-

J28: Open J29: 1-2 J32: 5-6 and 3-4 J34: 1-2 and 7-8

3 MAX9632, Channel A0 Inverting, single-ended, second-order LPF

CON3: AIN0+ or (TP2) and AGND (or TP8)

J28: 1-2 J29: 3-4 J32: 1-2 and 7-8 J34: 1-2 and 7-8

4 MAX9632, Channel A0 Inverting, differential, second-order LPF

CON2 (TP1): AIN0- CON3 (TP2): AIN0+

J28: Open J29: 3-4 J32: 1-2 and 7-8 J34: 1-2 and 7-8

5 MAX9632, Channel A1 Noninverting, single-ended, first-order LPF

CON5: AIN1+ (or TP7) and AGND (or TP15)

J28: OpenJ29: 1-2 J32: 3-4 and 7-8 J34: 1-2 and 7-8

6 MAX9632, Channel A1 Differential, first-order LPF CON5 (TP7): AIN1+ CON4 (TP10): AIN1-

J28: OpenJ29: Open J32: 3-4 and 7-8 J34: 1-2 and 7-8

7 MAX9632, Channel A1 Inverting, single-ended, first-order LPF

CON4: AIN1- (or TP10) and AGND (or TP15)

J28: OpenJ29: 3-4 J32: 3-4 and 7-8 J34: 1-2 and 7-8

8 MAX44242, Channel A2 Noninverting, single-ended, second-order LPF (default)

TP19: AIN2+ and AGND (or TP11)

J33: 1-2 J31: 1-2 J36: 5-6 and 3-4 J34: 3-4 and 7-8

9 MAX44242, Channel A2 Noninverting, differential, second-order LPF

TP19: AIN2+ TP18: AIN2-

J33: Open J31: 1-2 J36: 5-6 and 3-4 J34: 3-4 and 7-8

10 MAX44242, Channel A2 Inverting, single-ended, second-order LPF


J33: 1-2 J31: 3-4 J36: 1-2 and 7-8 J34: 3-4 and 7-8



MAX11163/MAX11168/MAX11169


Table 8. Analog Input Configurations (Channel A0–A3) (continued)CONFIGURATION SIGNAL-PATH INPUT

CONFIGURATION INPUT CONNECTORS JUMPER POSITIONSNO. DESCRIPTION

11 MAX44242, Channel A2 Inverting, differential, second-order LPF

TP18: AIN2- TP19: AIN2+

J33: Open J31: 3-4 J36: 1-2 and 7-8 J34: 3-4 and 7-8

12 MAX44242, Channel A3 Noninverting, single-ended, first-order LPF


J31: 1-2 J36: 3-4 and 7-8 J34: 3-4 and 7-8

13 MAX44242, Channel A3 Differential, first-order LPF TP14: AIN3+ TP16: AIN3-

J31: Open J36: 3-4 and 7-8 J34: 3-4 and 7-8

14 MAX44242, Channel A3 Inverting, single-ended, first-order LPF

TP16: AIN3- and AGND (or TP17)

J31: 3-4 J36: 3-4 and 7-8 J34: 3-4 and 7-8

Figure 6. Noninverting, Single-Ended, Second-Order LPF

MAX9632

INPUT FROM MAX44242 AMPS

MAX9632

GND_SENSE

ADC_INP

ADC_INMVREF

J28

J29

J32

J34

1 12 23 4

1 23 4

3 45 67 8

1 2

3 45 67 8

VIN

AIN0-

AIN0+

AIN1-

AIN1+

MAX1115X/MAX1116XSAR ADC

-

+

-

+



MAX11163/MAX11168/MAX11169


Figure 7. Noninverting, Differential, Second-Order LPF

Figure 8. Inverting, Single-Ended, Second-Order LPF


MAX9632


MAX9632

GND_SENSE

ADC_INP

ADC_INMVREF

J28

J29

J32

J34

11

223 4

1 23 4

3 45 67 8

1 2

3 45 67 8

VIN

AIN0-

AIN0+

AIN1-

AIN1+

-

+

-

+

MAX9632


MAX9632

GND_SENSE

ADC_INP

ADC_INM

VREF

J28

J29

J32

J34

11

223 4

1 23 4

3 45 67 8

1 2

3 45 67 8

VIN

AIN0-

AIN0+

AIN1-

AIN1+


-

+

-

+



MAX11163/MAX11168/MAX11169


Figure 9. Inverting, Differential, Second-Order LPF

Figure 10. Noninverting, Single-Ended, First-Order LPF

VIN

AIN0-

AIN0+

AIN1-

AIN1+

MAX9632


MAX9632

GND_SENSE

ADC_INP

ADC_INM

VREF

J28

J29

J32

J34

11

223 4

1 23 4

3 45 67 8

1 2

3 45 67 8


-

+

-

+

MAX9632


MAX9632

GND_SENSE

ADC_INP

ADC_INMVREF

J28

J29

J32

J34

11

223 4

1 23 4

3 45 67 8

1 23 45 67 8

AIN0-

AIN0+

AIN1-

AIN1+VIN

-

+


-

+



MAX11163/MAX11168/MAX11169


Figure 11. Differential, First-Order LPF

Figure 12. Inverting, Single-Ended, First-Order LPF

MAX9632

INPUT FROM MAX44242 Amps

MAX9632

GND_SENSE

ADC_INP

ADC_INM

VREF

J28

J29

J32

J34

11

223 4

1 23 4

3 45 67 8

1 2

3 45 67 8

VIN

AIN0-

AIN0+

AIN1-

AIN1+


-

+

-

+


-

+ -

+

MAX9632


MAX9632

GND_SENSE

ADC_INP

ADC_INM

VREF

J28

J29

J32

J34

11

223 4

1 23 4

3 4

5 6

7 8

1 2

3 4

5 6

7 8

AIN0-

AIN0+

AIN1-

AIN1+

VIN



MAX11163/MAX11168/MAX11169


Table 9. Analog Input Configurations (Channel B0–B3)CONFIGURATION SIGNAL-PATH INPUT

CONFIGURATION INPUT CONNECTORS JUMPER POSITIONSNo. DESCRIPTION

1 MAX9632, Channel B0 Noninverting, single-ended, second-order LPF (default)

CON11: BIN0+ (or TP54): and AGND (or TP39)

J5: 1-2 J9: 1-2 J10: 5-6 and 3-4 J39: 1-2 and 7-8

2 MAX9632, Channel B0 Noninverting, differential, second-order LPF

CON11 (TP54): BIN0+ CON10 (TP53): BIN0-

J5: Open J9: 1-2 J10: 5-6 and 3-4 J39: 1-2 and 7-8

3 MAX9632, Channel B0 Inverting, single-ended, second-order LPF

CON11: BIN0+ or (TP54): and AGND (or TP39)

J5: 1-2 J9: 3-4 J10: 1-2 and 7-8 J39: 1-2 and 7-8

4 MAX9632, Channel B0 Inverting, differential, second-order LPF

CON10 (TP53): BIN0- CON11 (TP54): BIN0+

J5: Open J9: 3-4 J10: 1-2 and 7-8 J39: 1-2 and 7-8

5 MAX9632, Channel B1 Noninverting, single-ended, first-order LPF

CON13: BIN1+ or (TP56): and AGND (or TP41)

J9: 1-2 J10: 3-4 and 7-8 J39: 1-2 and 7-8

6 MAX9632, Channel B1 Differential, first-order LPF CON13 (TP56): BIN1+ CON12 (TP55): BIN1-

J9: Open J10: 3-4 and 7-8 J39: 1-2 and 7-8

7 MAX9632, Channel B1 Inverting, single-ended, first-order LPF

CON12: BIN1- or (TP55): and AGND (or TP41)

J9: 3-4 J10: 3-4 and 7-8 J39: 1-2 and 7-8

8 MAX44242, Channel B2 Noninverting, single-ended, second-order LPF (default)

TP58: BIN2+ and AGND (or TP40)

J6: 1-2 J7: 1-2 J11: 5-6 and 3-4 J39: 3-4 and 7-8

9 MAX44242, Channel B2 Noninverting, differential, second-order LPF

TP58: BIN2+ TP57: BIN2-

J6: Open J7: 1-2 J11: 5-6 and 3-4 J39: 3-4 and 7-8

10 MAX44242, Channel B2 Inverting, single-ended, second-order LPF


J5: 1-2 J7: 3-4 J11: 1-2 and 7-8 J39: 3-4 and 7-8



MAX11163/MAX11168/MAX11169


Sync Input and Sync OutputSync input and sync output is applicable to the FPGA (ZedBoard) and is not used in standalone mode. The SYNC_IN SMA accepts an approximate 100MHz wave-form signal to generate the system clock of the ZedBoard. For maximum performance, use a low-jitter clock that syncs to the user’s analog function generator. The SYNC_OUT SMA outputs a 10MHz square waveform that syncs to the user’s analog function generator. Both options are used for coherent sampling of the IC. Only

one option should be used at a time. The relationship between fIN, fS, NCYCLES, and MSAMPLES is given as follows:

fIN/fS = NCYCLES/MSAMPLESwhere: fIN = Input frequency fS = Sampling frequency NCYCLES = Prime number of cycles in the sampled set MSAMPLES = Total number of samples

Table 9. Analog Input Configurations (Channel B0–B3) (continued)CONFIGURATION SIGNAL-PATH INPUT

CONFIGURATION INPUT CONNECTORS JUMPER POSITIONSNo. DESCRIPTION

11 MAX44242, Channel B2 Inverting, differential, second-order LPF

TP57: BIN2- TP58: BIN2+

J6: Open J7: 3-4 J11: 1-2 and 7-8 J39: 3-4 and 7-8

12 MAX44242, Channel B3 Noninverting, single-ended, first-order LPF


J7: 1-2 J11: 3-4 and 7-8 J39: 3-4 and 7-8

13 MAX44242, Channel B3 Differential, first-order LPF TP60: BIN3+ TP59: BIN3-

J7: Open J11: 3-4 and 7-8 J39: 3-4 and 7-8

14 MAX44242, Channel B3 Inverting, single-ended, first-order LPF

TP59: BIN3- and AGND (or TP42)

J7: 3-4 J11: 3-4 and 7-8 J39: 3-4 and 7-8

Note: Alternate connections are shown in parentheses.

Figure 13. EV Kit Coherent Sampling Setup

LOW-JITTER CLOCK

SIGNAL GENERATOR

MAX1115X/MAX1116X EV KIT

ZedBoard/FPGA Board

PC

ETHERNET CABLE

SYNC _IN

+

_ INV-

INV+

10MHz

OUT ~100MHzREF_OUT

REF_IN

10kHzFPGA

MASTER_CLOCK



MAX11163/MAX11168/MAX11169


Figure 14. MAX1115X/MAX1116X EV Kit Component Placement Guide—Top Side



MAX11163/MAX11168/MAX11169


Figure 15. MAX1115X/MAX1116X EV Kit PCB Layout—Layer 1



MAX11163/MAX11168/MAX11169





MAX11163/MAX11168/MAX11169





MAX11163/MAX11168/MAX11169





MAX11163/MAX11168/MAX11169





MAX11163/MAX11168/MAX11169





MAX11163/MAX11168/MAX11169


Figure 21. MAX1115X/MAX1116X EV Kit Component Placement Guide—Bottom Side



MAX11163/MAX11168/MAX11169


Refer to files “evkit_bom_max1115x6x_evkit_revA.csv” and “MAX1115X6X_EVKIT_Reva.SCH.pdf” attached to this data sheet for component information and schematics diagrams.Contact Avnet to purchase a ZedBoard (AES-Z7EV-7Z020-G) to communicate with the MAX1115X/MAX1116X EV kit.

#Denotes RoHS compliant.

PART TYPEMAX11150EVKIT# EVKIT

MAX11152EVKIT# EVKIT





Component List and Schematic Diagrams

Ordering Information

Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. © 2015 Maxim Integrated Products, Inc. │ 33


MAX11163/MAX11168/MAX11169


REVISIONNUMBER

REVISIONDATE DESCRIPTION PAGES

CHANGED

0 5/15 Initial release —

Revision History

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.

MAX1115X/6X EVKIT

71

ENGINEER:

TEMPLATE REV:

AUTHORDATEDESCRIPTION

REVISIONS

REV:

DRAWN BY:

LTRZONE

SIZE

PROJECT TITLE:

DRAWING TITLE:

DRAWING NO:

DATE:

2

D

1

C

B

A

1

2345

345

678

D

67

C

B

A

8

PAGE OF

BB

AINO-

AIN1-

AIN0+

AGND

AIN3+

AIN3-

AIN2+

AIN2-

GND_SENSE

CHANNEL 1 INPUT SIGNALS

AIN1+

AGND

AGND

SHEET 2 OF 7

<HARDWARE_NUMBER>

MAX1115x6x_AC91_EVKIT_REV0

02-06-2015

GONZALES / S. SCULLYW. Scott REV_A

<TEMPLATE_REVISION>

7.5K0.1%10PPM

-15V

MAX9632AUA+

1000PF

.1%

AIN1+

AIN1-

.1%

AGND

15K

.1%

AGND

1000PF

AGND

.1%

5K

.1%

.1%

2.5K

1000PF

.1%

.1%

5.1K

5.1K

AGND

10.2K

10.2K

1M

.1%

AGND AGND

+10V

AGND

AGND

AGND

1M

1UF 0.1UF1UF

0.1UF0.1UF1UF

+15V -15V

AGND

AGND

AGND

10K

.1%

.1%

0

AGND

ADC1_INP

AGND

ADC1_INM

0.1UF

.1%

25PPM

20

10K

1UF

VREF2 AGND

0.022UF

50VCOG

1010PPM

10

0.1%

0.1%

-15V+15V

1UF

-10V

1000PF

0

AGND

1M

AGND

1M

AGND

AGND

1M

1M

AGND

AIN3-

AIN3+

AGND

AGNDI712

I706

I708

I710

AGND

AGND

AGND

AGND

AGND

VREF1

1UF0.1UF

-15V

0AGND

+15V

0.1UF

10PPM

AGND AGND

AGND

5K

0.1%MAX44242AUA+

10K

1000PF

AGND

MAX9632AUA+

0

+15V

AGND

1M 2.5K .1%

1000PF

5K5K

.1%

5K

AGND

MAX44242AUA+AGND

AGND

-10V

.1%

1M

10K

+10V

1000PF.1%

5K

1000PF

J32

5 4 3 2

1

5 4 3 2

1

5 4 3 2

1

5 4 3 2

1

87

65

1

3 4

2

87

65

1

3 4

243

21

4 3

2 1

4 3

2 1

87

65

1

3 4

2

43

21

R78

VSS

VDDINA-

INA+OUTA

OUTB

INB-

INB+

N.C.

N.C.

SHDN

VCC

VEE

OUT

IN+

IN-

N.C.

N.C.

SHDN

VCC

VEE

OUT

IN+

IN-

FORBIDDEN.

TO MAXIM USE OR DICLOSURE WITHOUT THE WRITTENPERMISSION OF AN OFFICER OF MAXIM IS EXPRESSLY

THIS DOCUMENT CONTAINS INFORMATION PROPRIETARY

R62

1

1

1

1

87654321

8765432143

21

4 3

2 1

4 3

2 1

87654321

43

21

12

3 76

5

6

2

3

6

2

3

R54

R53

R52

R58

R51

PROJECT TITLE:

ENGINEER:

TEMPLATE REV.:

SIZE:

DRAWING TITLE:

HARDWARE NUMBER:

DRAWN BY: REV.:

8

F F

8

A

B

C

D

E

ZONE LTR DESCRIPTION DATE

DATE:

APPR.

1234567

1234567

A

B

C

D

E

OUT

OUT

IN

IN

CON5

CON4

CON3

CON2

TP14

TP16

TP19

TP18

TP7

TP10

J34

J36

C60 C63

J33

J31

J29

J28

C36

TP20

TP25

TP21

C38C39 C40

TP5

TP4

TP3

C32 C33 C31 C37

C27C28 C26C29

5 4 3 2

5 4 3 2

5 4 3 2

5 4 3 2

48

47

85

147

85

1

R59

R61 R88

R85

R60

R81

R64

R90

R109

U9

R107

R83

R57

R56

R50

R49

R63

R55

R14

R17

R16

R15

R13

R12

R10

R11

TP17

C133

TP2

TP1

TP11

TP15

TP8

TP50

U9

C41

C42

TP26

C30

C35

C25

C3

U7

R8

9

U8

REVISIONS

CCCC

BIN3+

BIN3-

AGND

GND_SENSE

AGND

BIN0+

CHANNEL 2 INPUT SIGNALS

BIN1+

AGND

BIN2-

BIN2+

BIN1-

BINO-

SHEET 3 OF 7

<HARDWARE_NUMBER>


02-06-2015


<TEMPLATE_REVISION>

MAX44242AUA+

7.5K

5K

1000PF.1%

.1%

-15V.1%

0.1UF

AGND

.1%

MAX9632AUA+

AGND

AGND

1M

1M

AGND

AGND

BIN3+

AGND

1M

AGND

1M

AGND

AGND

AGND

BIN1+

BIN1-

1M

AGND

AGND

I199

I202

AGND

AGND

AGND

1M

AGNDAGND

1M

AGND

AGND

AGND

AGND

50V

0.022UF25PPMCOG

200.1%

AGND

1010PPM

0.1%

10

0.1UF 1UF

0

0

0.1UF1UF0.1UF1UF

0

0.1UF1UF1UF

0.1UF

+10V

-15V

AGND

+15V

-15V

AGND

+15V

AGND

AGND

AGND

AGND

10K

AGND

1000PF

.1%

.1%

10K

VREF4

AGND

MAX44242AUA+

0

AGND

1M

AGND

ADC2_INP

ADC2_INM

1UF

-10V

+15V

10PPM

AGND

.1%

5K

+15V

MAX9632AUA+

0.1%

-10V

.1%

5K

+10V

1000PF

5K

10K

.1%10K

1000PF

.1%

1000PF

1000PF

15K

AGND

AGND

1000PF

AGND

BIN3-

.1%

.1%

5.1K

2.5K

1000PF

2.5K

5K5K

.1%

10.2K

10.2K

.1%

.1%

.1%

5.1K

VREF3

-15V10PPM0.1%

C112

87

65

1

3 4

2

87

65

1

3 4

2

4 3

2 1

43

21

43

21

5 4 3 2

1

5 4 3 2

1

5 4 3 2

1

5 4 3 2

1

4 3

2 1

87

65

1

3 4

2

R150

N.C.

N.C.

SHDN

VCC

VEE

OUT

IN+

IN-

VSS

VDDINA-

INA+OUTA

OUTB

INB-

INB+

N.C.

N.C.

SHDN

VCC

VEE

OUT

IN+

IN-

C71

FORBIDDEN.



R135

R147

R136

1

1

1

1

876543216

2

387654321

87654321

6

2

3

4 3

2 1

12

3

43

21

43

21

76

5

4 3

2 1

R129

R130

R122

R127

R128

PROJECT TITLE:

ENGINEER:

TEMPLATE REV.:

SIZE:

DRAWING TITLE:

HARDWARE NUMBER:

DRAWN BY: REV.:

8

F F

8

A

B

C

D

E


DATE:

APPR.

1234567

1234567

A

B

C

D

EIN

IN

OUT

OUT

C110

TP58

CON10

TP55

CON11

CON12

TP56

CON13

TP60

TP59

TP57

C123C122C121C120

C99C97

TP45

C77C75

TP44

TP49

J10

TP46

C100C98C78

TP47

J11

C76

TP43

C74

J9

C73

J5

J6

TP48C72

J7

5 4 3 2

5 4 3 2

5 4 3 2

5 4 3 2

47

85

147

85

1

48

R1

48

R146

R154

R155

R153

R152

R151

R142

R143

R144

R145

R137

R139

R131

R32

R140

R141

R138

R132

R126

R134

R133

U26

R149

R123

TP53

TP54

C134

C113

J39

TP61

U27

U26

TP39

TP41

TP40

C111

TP42

U28

REVISIONS

CCCC

MAX1115X/6X

MAX1115X/6X

ADC AND VREF

REF_U12EXT_REFREF_U11

ADC_EXT_REF

SHEET 4 OF 7

<HARDWARE_NUMBER>


02-06-2015


<TEMPLATE_REVISION>

VREF1_ADC

VREF2_ADC

AGND

VREF4VREF1VREF2

VREF3

AGND

0.1UF

1UF4700PF

0.1UF

CNVST2_ADC

SCLK2_ADC

CNVST1_ADC

SCLK1_ADC

ADC2_INP

ADC2_INM

DOUT_DAISY

ADC1_INM

ADC1_INP

VREF2_ADC

DIN2_ADC

VREF1_ADC

CNVST1_ADCSCLK1_ADC

DOUT_DAISYDOUT2_ADC

DOUT1_ADCDIN1_ADC

AGND

+3.3V/+2.5V

0

0

AGND

4700PF50V

COG

AGND

COG

50V

+3.3V/+2.5V

0

AGND

COG50V

4700PF

0

AGND

4700PF50V

COG

10UF

AGND

10UF

AGND

MAX11152EUB+

+5V

AGND

10UF

AGND

1UF 0.1UF

+3.3V/+2.5V

10UF

AGND

AGND

28

28

1UF

+5V

AGND

0.1UF

MAX11152EUB+

1UF 0.1UF

+3.3V/+2.5V

AGND10K

AGND

MAX6070AAUT50+

0.1UF

1UF

AGND

MAX6126AASA50

0.1UF

+5.33V

0.1UF

AGND

AGND

0.1UF

1UF 0.1UF

+5.33V

C59

J37

C58

C57C34

C50

C24C48C49

1211

109

87

65

1

3 4

2

12 11

10 9

8 7

6 5

1

34

2

43

21

43

21

IN

OUTF

OUTS

NR

OVDD

SDI

SCLK

SDO

CNVST

GND

AIN-

AIN+

VDD

REF

OVDD

SDI

SCLK

SDO

CNVST

GND

AIN-

AIN+

VDD

REF

OUTF

OUTSIN

EN

GND

FILTER

I.C

.

I.C

.

GN

DS

GN

D

JU

MP

ER

FORBIDDEN.



J13

U12

U11

121110987654321

12 1110 98 76 54 32 1

43

2179

8

1

6

4

3

43

21 79

8

1

6

4

3

321

5

6

4

2

1

3

6

71

2

PROJECT TITLE:

ENGINEER:

TEMPLATE REV.:

SIZE:

DRAWING TITLE:

HARDWARE NUMBER:

DRAWN BY: REV.:

8

F F

8

A

B

C

D

E


DATE:

APPR.

1234567

1234567

A

B

C

D

E

IN

OUTOUT

IN

INOUT

ININ

IN

OUT

OUTOUTOUTOUT

OUT

IN

IN

IN

IN

IN

IN

IN

TP62

TP63

TP51

TP52

C47

C46

J35

U14

C68 C69 C70

J19

J20

U10

TP12

TP13

2 10

5

21

2 10

5

8543

R156

R157

R82

R84

R31

R111

R110

C131

C132

C125

C124

J38

C67

C66

C61C62C44C43

C45

REVISIONS

CCCC

DNI

DNI

DNI

ISOLATED

SYNC_CLK_OUTSYNC_CLK_OUT

MAX14934FAWE

FMC AND ISOLATION

SYNC_CLK_IN

SYNC_CLK_IN_SPLIT

GND

SYNC_CLK_OUT

SYNC_CLK_IN

MAX14934FAWE

MAX14934FAWE

PMOD HEADER

SHEET 5 OF 7

<HARDWARE_NUMBER>


02-06-2015


<TEMPLATE_REVISION>

CNVST1_ADC

28

28

AGND

28

+3.3V/+2.5V

VADJ

DNI

DNI

28

SYNC_CLK_OUT

DOUT1_ADC_FPGA

DIN1_ADC_FPGADIN2_ADC_FPGA

VDDIO

SO_EEPROM_FPGA

93LC66BT-I/OT

1UF

CNVST2_ADC_FPGA

CNVST1_ADC_FPGA

SCLK1B_ADC_FPGA

SCLK2B_ADC_FPGA

VDDIO

CNVST2_ADC_FPGA

DIN2_ADC_FPGA

+3.3V/+2.5V

28

AGND

68021-212HLF

CNVST1_ADCDOUT1_ADC

DIN2_ADC_FPGA

DOUT2_ADC_FPGA

SCLK2_ADC_FPGA

+12V_FPGA

DNICNVST2_ADC_FPGA

DOUT2_ADC_FPGA

28

DOUT2_ADC_FPGA

SYNC_CLK_OUT

SO_EEPROM_FPGA

SCLK1_ADC

DIN1_ADC

CNVST1_ADC_FPGASCLK1_ADC_FPGADIN1_ADC_FPGA

1UF 0.1UF

+3.3V/+2.5V

1UF0.1UF

SCLK2_ADCDOUT2_ADCSCLK1_ADCDOUT1_ADC

SCLK2B_ADC_FPGA

SCLK1B_ADC_FPGA

DOUT1_ADC_FPGA

AGND

1UF 0.1UF

AGND

28

28

28

1UF0.1UF

VDDIO

SYNC_CLK_IN

ASP-134604-01

SCLK1_ADC_FPGA

0

SCLK2_ADC

CNVST1_ADC_FPGA

DIN1_ADC_FPGA

DOUT1_ADC_FPGA

DNI0

DNI

1UF

SCLK1_ADCDIN1_ADC

3V3_FPGA

MBR0520L

28

28

1UF

0.1UF

CNVST2_ADCDOUT2_ADC

DIN2_ADCSCLK2_ADC

AGND

49.9

28

28

28

28

SCLK1_ADC_FPGASCLK2_ADC_FPGA

28

49.9

49.9

49.9

0.1UF1000PF

74LVC2G125DP

VDDIO

0.1UF1000PF

5V_FPGA

74LVC2G125DP

49.9

49.9

0.1UF1UF

ASP-134604-01

28

28

28

28

28

ASP-134604-01ASP-134604-01

28

28

SYNC_CLK_IN

28

28

PBC06SAAN

28

28

VADJ

28

VDDIO

28

28

SCLK2_ADC_FPGACNVST2_ADC

28

28

28DIN2_ADC

AGND

AGND

AGND

0.1UF

VDDIO

D8

J23

1211

109

87

65

1

3 4

2

5432

1

5 4 3 2

1

5432

1

5432

1

R18

R77

R79

R163

R162

R101

U18

U24

R164

R86

R102

R161

R160R159

R33

CON1 CON1

CON1 CON1

GND2

GND2

EN NC

VCC2

OUTA

OUTB

OUTC

OUTD

GND1

IND

INC

INB

INA

GND1

VCC1

GND2

GND2

ENNC

VCC2

OUTA

OUTB

OUTC

OUTD

GND1

IND

INC

INB

INA

GND1

VCC1

GND2

GND2

EN NC

VCC2

OUTA

OUTB

OUTC

OUTD

GND1

IND

INC

INB

INA

GND1

VCC1

2A

2OE

2Y

VCC

1Y

GND

1A

1OE

2A

2OE

2Y

VCC

1Y

GND

1A

1OE

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

VCC

VSS

DO

DI

CLK

CS

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

FORBIDDEN.



C A

16 1

11

12

13

14

7

6

5

4

3

15

9 8

2

10

161

11

12

13

14

7

6

5

4

3

15

98

2

10

16 1

11

12

13

14

7

6

5

4

3

15

9 8

2

10

654321

654321

121110987654321

654321

1

35

62

7

1

1

1

1

35

62

7

1

C40

C39

C38

C37

C36

C35

C34

C33

C32

C31

C30

C29

C28

C27

C26

C25

C24

C23

C22

C21

C20

C19

C18

C17

C16

C15

C14

C13

C12

C11

C10

C9

C8

C7

C6

C5

C4

C3

C2

C1

D40

D39

D38

D37

D36

D35

D34

D33

D32

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

1

3

5

4

G40

G39

G38

G37

G36

G35

G34

G33

G32

G31

G30

G29

G28

G27

G26

G25

G24

G23

G22

G21

G20

G19

G18

G17

G16

G15

G14

G13

G12

G11

G10

G9

G8

G7

G6

G5

G4

G3

G2

G1

H40

H39

H38

H37

H36

H35

H34

H33

H32

H31

H30

H29

H28

H27

H26

H25

H24

H23

H22

H21

H20

H19

H18

H17

H16

H15

H14

H13

H12

H11

H10

H9

H8

H7

H6

H5

H4

H3

H2

H1

R121

R29

R30

U21

R34

R39

R105

U22

R106

R38

R36

R48

R35

R47

R46

R26

R45

R25

R44

R24

R43

R23

R42

R22

R41

R21

R40

R20

R37

R19

PROJECT TITLE:

ENGINEER:

TEMPLATE REV.:

SIZE:

DRAWING TITLE:

HARDWARE NUMBER:

DRAWN BY: REV.:

8

F F

8

A

B

C

D

E


DATE:

APPR.

1234567

1234567

A

B

C

D

E

IN

IN

IN

OUT

OUT

OUT

IN

IN

IN

OUT

OUT

OUT

IN

IN

IN

OUT

IN

IN

OUT

OUT

OUT

OUT

IN

IN

IN

OUT

OUT

ININ

IN

IN

OUT

OUT

IN

ININ

IN

IN

INININ

IN

ININ

ININ

IN

OUT

OUT

IN

OUT

OUT

C83 C84C95 C96

C135 C136C137 C138

C79 C80 C81 C82

J22J21

J25

C107

C105

C23

C104

CON8

CON7

C106

CON9

CON22

C94 C93

5432

84

5 4 3 2

5432

5432

84

26

TP32

TP34

TP33

U17

U25

REVISIONS

CCCC

USB AND FTDI CHIP

SHEET 6 OF 7

<HARDWARE_NUMBER>


02-06-2015


<TEMPLATE_REVISION>

MICRO-USB10118192-0001LF

USB+5V

28

SCLK2_ADC_FPGA28

DOUT2_ADC_FPGA28

DIN2_ADC_FPGADNI28

CNVST2_ADC_FPGA28

28

600

28

USB+5V

15K

10K

10K

+3V3_USB

+3V3_USB

10K

DNI

28

28

4.7UF 0.1UF

+3V3_USB

+3V3_USB

+1.8V+3V3_USB

+1.8V

10K

10K

10K

10K

10K

+3V3_USB

2.2K

93LC66BT-I/OT

18PF

12K

4.7UF 0.1UF

0.1UF0.1UF0.1UF0.1UF0.1UF

28

28SCLK1_ADC_FPGA

DOUT1_ADC_FPGA

DOUT1_ADC_FPGA

12MHZ18PF

4.7K

4.7UF

GREEN

CNVST1_ADC_FPGA

0.1UF0.1UF

DIN1_ADC_FPGA

10K

10K

FT2232HL

VCC

VSS

DO

DI

CLK

CS

BCBUS7

BCBUS6

BCBUS5

BCBUS4

BCBUS3

BCBUS2

BCBUS1

BCBUS0

ACBUS7

ACBUS6

ACBUS5

ACBUS4

ACBUS3

ACBUS2

ACBUS1

ACBUS0

BDBUS7

BDBUS6

BDBUS5

BDBUS4

BDBUS3

BDBUS2

BDBUS1

BDBUS0

ADBUS7

ADBUS6

ADBUS5

ADBUS4

ADBUS3

ADBUS2

ADBUS1

ADBUS0

OSCO

OSCI

EECS

EECLK

EEDATA

TEST

VREGOUT

VREGIN

RESET#

SUSPEND#

PWREN#

DP

DM

REF

5

4

3

2

1

FORBIDDEN.



VC

OR

E

GN

D

GN

DV

CC

IO

VC

OR

E

VC

OR

E

GN

D

GN

D

VC

CIO

GN

D

GN

D

VC

CIO

GN

D

GN

D

VC

CIO

VP

LL

AG

ND

VP

HY

11 10 9

8 7 6

5

4

3

2

1

1

3

5

4

49

50

13 36

14

6

603

2

61

63

62

8

7

46

45

44

43

41

40

39

38

59

58

57

55

54

53

52

48

24

23

22

21

19

18

17

16

34

33

32

30

29

28

27

26

R87

PROJECT TITLE:

ENGINEER:

TEMPLATE REV.:

SIZE:

DRAWING TITLE:

HARDWARE NUMBER:

DRAWN BY: REV.:

8

F F

8

A

B

C

D

E


DATE:

APPR.

1234567

1234567

A

B

C

D

E

OUT

IN

OUT

OUT

OUT

OUT

IN

IN

OUT

C119C118C117C116C90 C115C114

C85 C86

C88C87

Y1

C91

C92

2111

10 9

8 7 6

26

21

KA

94 64

37

12

56

42

31

20

51

47

35

25

15

1151

10

R1

16

R1

18

R1

17

R1

19

R1

15

R1

14

R1

13

R1

08

R158

CON6

R67

R68

R9

R124

R125 U16

R76R75

R74

R72

R70

R73

R71

R69

U15

FB

5

D6

C89

R65

R66

REVISIONS

CCCC

DC IN

ISOLATED

50MA+5.33V

AGND

+5V50MA

DGND

50MA

+15V

EXT_+18V

-10V

+10V 100MA

GND POWER SUPPLIES

AGND

100MA

-18V

50MA

AGND

50MA

-15V

100MA

DVDD

AGND

SHEET 7 OF 7

<HARDWARE_NUMBER>


02-06-2015


<TEMPLATE_REVISION>

25V50V

+20V

0.47UF

I201

AGND

MAX8719ETA+I202

AGND

AGND

AGND

10UF

MAX8719ETA+

TPS7A3001DGN

CAP:INTEGER

1.00E-08

+18V

27K

10UF

1K

KLDX-0202-B

LS L29K-G1J2-1-Z

MAX13256ATB+

20K1UF

AGND

MAX15006CATT+

50V

50V

1UF

50V

1UF

25V

1UF

50V

1UF

5V_FPGA

TERM_BLK

+3.3V/+2.5V

+3V3_USB

+20V

TGMR-501V6LF

33UH

100K

5V_FPGA

RED

20K

1K

MBR0520L

MBR0520L

50V

1UF

AGND

+10V

300K

MAX15006AATT+

+12V_FPGA261K

10UF

-18V

0.1UF

820K

0.01UF

GREEN

+10V

10UF

0.1UF

0.1%30K25PPM

5PPM0.05%

I186

AGND

25V1UF

+10V

AGND

0.1UF

MAX15006BATT+

10UF

+5V

0.1UF

25V

0.01UF0.01UF

TPS7A3001DGN

-18V

0.1UF

+18V

4.7UF

33UH

33UH

+15V

0.1UF

10UF

25V4.7UF

0.01UF

CAP:INTEGER

BAS4002A-RPP

-10V

+10V

10UF

VDDIO

33UH

470K

0.01UF 10UF

0.1UF

66.5K

180PF

AGND

-15V10UF

AGND

I177

AGND

25V

25V

0.01UF

10UF

91K

0.1UF

69.8K

+5.33V

100K

MAX15006CATT+

1.00E-08

680K

1.00E-08

CAP:INTEGER

4.7UF4.7UF

BAS4002A-RPP

MAX15006BATT+

169K

TGMR-501V6LF

0.47UF

1UF

USB+5V

+12V_FPGA

J8

C126

C65

C64

J3

U4

JUMPER

43

21

JUMPER

43

21

65

1

3 4

2

43

21

65

1

3 4

2

43

21

43

21

43

21

T2

T1

R120

R112

D1

R27

ST1

ST2

FAULT

ITH

EN

CLK

1

3

2

FB

OUT

NC

IN

IN

EPGND

IN

NR/SS

EN

FB

OUT

6

5

43

2

1

6

5

43

2

1

OUT

OUT

NC

IN

IN

EPGND

OUT

OUT

NC

IN

IN

EPGND

FB

OUT

NC

IN

IN

EPGND

OUT

OUT

NC

IN

IN

EPGND

OUT

GND

SHDN PGOOD

VCC

FBI.C.

IN

EP

IN

NR/SS

EN

FB

OUT

OUT

GND

SHDN PGOOD

VCC

FBI.C.

IN

EP

J12

JU

MP

ER

FORBIDDEN.



D7

C130

C129

C103

C102C101

C109

U23

C108C10

C51

C54

C53

C56

J16

J15

C22

C20 C19

C18C17C21

C15

C7C5C4

C12

L4

L3

L2

L1

C13

C6

C11

J2

D5

D3

D4

EP

GN

D2

GN

D1

VD

D2

VD

D1

~~- +

D4

D3

D2

D1

EP

DN

C

GN

D

NC

EP

DN

C

GN

D

NC

~~- +

D4

D3

D2

D1

43

21

CA

6

2

1

5

1

6

8

2

5

6

5

43

2

1

6

5

43

2

1

21

6

5

2

1

43

21

6

5

2

1

5

81

7 3

6

654321

43

21

654321

43

21

TP30

43

21

43

21

21

21

21

21

21

4

32

1

4

32

121

6

5

2

1

6

2

1

5

1

6

8

2

5

5

81

7 3

6

K A

KA

8

10

5

3

64

3

2

1

CA

U6

R104

R103

R6 R8

R7

R5

R4

R2

R3

D2

R28

U1

J1

PROJECT TITLE:

ENGINEER:

TEMPLATE REV.:

SIZE:

DRAWING TITLE:

HARDWARE NUMBER:

DRAWN BY: REV.:

8

F F

8

A

B

C

D

E


DATE:

APPR.

1234567

1234567

A

B

C

D

E

U19

TP64 U13

C14

J14

TP31

U20

J4

C52

C55

J27

J26

J24

J17

TP24

C16

C9C8

C2C1

U5

U3

U2

21

34 7

34 97

34 7

34 7

4

2 9

34 7

34 7

34 974

2 9

2197

11

5V_FPGA

TP37

TP27

TP38

TP23

TP29

TP28

TP6

TP22

TP9

TP36

TP35

+20V

GND

R80

R91

R1

21

C127C128

R92

REVISIONS

CCCC

Documents

Evaluates: MAX11150/MAX11152/MAX11158/ Evaluation Kit ... · Evaluates: MAX11150/MAX11152/MAX11158/ MAX11160/MAX11161/MAX11162/MAX11163/ MAX11168/MAX11169 MAX1115X/MAX1116X Family