EVAL-AD7134FMCZ User Guide - Analog Devices€¦ · Optional external connectors for driver, daughter board, Channel 0, and Channel 4 : 7-way, 2.54 mm vertical sockets . P6, P10 :

EVAL-AD7134FMCZ User Guide UG-1599

One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com

Evaluation Board for the AD7134 24-Bit, 4-Channel, Simultaneous Sampling,

1.5 MSPS Precision Alias Free ADC

PLEASE SEE THE LAST PAGE FOR AN IMPORTANT WARNING AND LEGAL TERMS AND CONDITIONS. Rev. 0 | Page 1 of 22

FEATURES Fully featured evaluation board for the AD7134 PC control in conjunction with the SDP-H1 board PC software control and data analysis Standalone hardware capability Two AD7134 ADCs to demonstrate multidevice simultaneous

sampling

EVALUATION KIT CONTENTS EVAL-AD7134FMCZ board AD7134

DOCUMENTS NEEDED AD7134 data sheet

EQUIPMENT NEEDED Evaluation kit SDP-H1 board DC or ac signal source (audio precision or a similar high

performance signal source) PC running Windows® with a USB 2.0 port and the evaluation

tool installed

SOFTWARE NEEDED AD7134 evaluation software

GENERAL DESCRIPTION The EVAL-AD7134FMCZ evaluation kit features the AD7134 24-bit, 4-channel, simultaneous sampling, 1.5 MSPS precision alias free analog-to-digital converter (ADC). Two on-board AD7134 ADCs are included to demonstrate multidevice simul-taneous sampling. The EVAL-AD7134FMCZ draws power from the system demonstration platform (SDP) EVAL-SDP-CH1Z (SDP-H1) board, and the on-board dc-to-dc regulators regulate an external supply of 8 V to 14 V down to 5 V, 1.8 V, and 1.2 V to supply the AD7134 and peripheral components. Both on-board ADCs have a separate reference of 4.096 V generated by the on-board ADR444. The ADCs have three clock input options and can be clocked by a crystal input, a microelectromechanical system (MEMS) oscillator, or a complementary metal-oxide semiconductor (CMOS) clock.

The EVAL-AD7134FMCZ connects to the PC USB port via the SDP-H1 board.

The AD7134 evaluation software running on a PC provides full accessibility to the AD7134 device register map, as well as a data analysis interface to display key parameters and graphics from the conversion result in both time and frequency domains.

For full details on the AD7134, see the AD7134 data sheet, which must be consulted in conjunction with this user guide when using the EVAL-AD7134FMCZ.

EVAL-AD7134FMCZ PHOTOGRAPH

2089

5-00

1

Figure 1.

https://www.analog.com/AD7134?doc=EVAL-AD7134FMCZ-UG-1599.pdf


https://www.analog.com/sdp-h1?doc=EVAL-AD7134FMCZ-UG-1599.pdf












https://www.analog.com/ADR444?doc=EVAL-AD7134FMCZ-UG-1599.pdf






https://www.analog.com

https://www.analog.com/EVAL-AD7134FMCZ?doc=EVAL-AD7134FMCZ-UG-1599.pdf

UG-1599 EVAL-AD7134FMCZ User Guide

Rev. 0 | Page 2 of 22

TABLE OF CONTENTS Features .............................................................................................. 1 Evaluation Kit Contents ................................................................... 1 Documents Needed .......................................................................... 1 Equipment Needed ........................................................................... 1 Software Needed ............................................................................... 1 General Description ......................................................................... 1 EVAL-AD7134FMCZ Photograph ................................................. 1 Revision History ............................................................................... 2 Evaluation Board Quick Start Procedure ...................................... 3

Known Limitations and Issues .................................................... 3 Evaluation Board Hardware ............................................................ 4

Analog Inputs and Front-End Circuit ....................................... 4 Power Supply Options ................................................................. 5 Connectors and Sockets .............................................................. 6

Serial Data Interface ..........................................................................7 8-Channel Data..............................................................................7 Daisy-Chaining and Minimal Input/Output Configuration ...7

Configuration Control Modes .........................................................8 Pin Control Mode .........................................................................8 SPI Control Mode .........................................................................8

Evaluation Board Software Quick Start Procedures .................. 10 Software Installation .................................................................. 10 Using the Software for Testing .................................................. 11

Evaluation Board Schematics and Artwork ................................ 13 Ordering Information .................................................................... 20

Bill of Materials ........................................................................... 20

REVISION HISTORY 4/2020—Revision 0: Initial Version




EVALUATION BOARD QUICK START PROCEDURE The EVAL-AD7134FMCZ default configuration can be modified according to the evaluation requirement.

The AD7134 evaluation software must be installed before setting up the EVAL-AD7134FMCZ. See the Software Installation section for more details.

To set up the EVAL-AD7134FMCZ, take the following steps:

1. Ensure that the SDP-H1 board is powered off and disconnected from the USB port of the PC, and then download and install the AD7134 evaluation software.

2. When the AD7134 evaluation software installation is complete, restart the PC. See the Software Installation section for more details on the AD7134 evaluation software installation.

3. Connect the J4 connector of the SDP-H1 board to the P8 connector of the powered down EVAL-AD7134FMCZ, as shown in Figure 2. Ensure that the boards are connected firmly together.

4. Connect the 12 V dc adaptor to the SDP-H1 board. The EVAL-AD7134FMCZ draws power from the SDP-H1 board and does not require any separate power connection.

5. Connect the SDP-H1 board to the PC using the USB cable provided with the SDP-H1 board. The PC can search for the SDP-H1 board drivers automatically. If prompted by

the operating system, choose to automatically search for the drivers for the SDP-H1 board.

6. Launch the AD7134 evaluation software from the shortcut on the desktop, as shown in Figure 13.

KNOWN LIMITATIONS AND ISSUES The known limitations and issues for the EVAL-AD7134FMCZ include the following:

• GPIO functionality cannot be exercised in SPI mode. The DCLKRATE1/GPIO1, DCLKRATE2/GPIO2, PWRMODE/ GPIO3, FILTER0/GPIO4, FILTER1/GPIO5, FRAME0/ GPIO6, and FRAME1/GPIO7 pins are only used for pin control mode configuration usage.

• The AD7134 evaluation software does not support free running DCLK mode, minimal input/output mode, daisy-chaining mode, 16-bit data mode, 16-bit data with CRC, or 24-bit data with CRC.

• Evaluation software only supports a fixed DCLK frequency value of 48 MHz.

• CLKSEL_1 and CLKSEL_2 in Figure 19 connect to 1V8CLKVDD using R133 and R135. It is recommended to wire CLKSEL_1 and CLKSEL_2 to IOVDD instead of 1V8CLKVDD.

2089

5-00

3

Figure 2. EVAL-AD7134FMCZ and SDP-H1 Board Connection



















EVALUATION BOARD HARDWARE ANALOG INPUTS AND FRONT-END CIRCUIT The EVAL-AD7134FMCZ features two AD7134 devices that have a total of eight ADC channels operating in parallel to each other. A differential input signal feeds to the front-end circuit via either the Subminiature Version B (SMB) connectors or the terminal blocks. The input signal for Channel 0 and Channel 4 can be fed either directly via the front end, or via an amplifier mezzanine card (AMC) by using the solder link options shown in Table 1 and Table 2. The signal is fed directly for all other channels.

Table 1. Input Connection Options for Channel 0 Input Mounted Not Mounted Comments Direct R150, R155 R147, R156 Default Front End

R147, R156 R150, R155 Mount R86, R87

AMC R150, R147, R155, R156

Open R86 and R87

Table 2. Input Connection Options for Channel 4 Input Mounted Not Mounted Comments Direct R158, R170 R157, R171 Default Front End

R157, R171 R158, R170 Mount R152 and R151

AMC R157, R158, R170, R171

Open R152 and R151

The amplifier inputs do not terminate for any particular source impedances. The on-board, common-mode voltage (VCM) source on the AD7134 biases the input signal. The default condition is VCM = VREF/2, where VREF is the reference voltage.

Another option available for the front-end circuit is using an AMC, which is available for Channel 0 and Channel 4. An AMC uses the P5 and P6 connectors for Channel 0, and the P9 and P10 connectors for Channel 4 to connect to the EVAL-AD7134FMCZ.

TERMINALBLOCKS

P1 AND P7

LINK OPTIONS TO ROUTE CHANNEL 0 ANDCHANNEL 4 ANALOG INPUTS TO ADC INPUTS

OPTION 1: DEFAULT DIRECT TO ADCOPTION 2: FRONT END, GAIN = 1

1

2

VREF1

CHANNEL 0

CHANNEL 1

CHANNEL 2

CHANNEL 3

CHANNEL 0

CHANNEL 1

CHANNEL 2

CHANNEL 3

DEVICE 1

160-PIN FMCCONNECTOR

TO SDP

P1

P7

P8

VREF2

DEVICE 2

FRONT ENDG = 1

1

2 CHANNEL 0

CHANNEL 1

CHANNEL 2

CHANNEL 3

CHANNEL 4

CHANNEL 5

CHANNEL 6

CHANNEL 7

FRONT ENDG = 1

2089

5-00

4

Figure 3. Analog Front-End Block






POWER SUPPLY OPTIONS Device Power Supply

The AD7134 can be powered with external supplies, or the integrated low dropout (LDO) regulators can generate the 1.8 V rails to supply the AVDD1V8, DVDD1V8, and CLKVDD supplies.

See Table 3 for setting the desired power rail option. The suffix _1 in the name of the power rail is for Device 1 and the suffix _2 is for Device 2. The IOVDD pin supplies the interface logic and is powered up by the SDP-H1 board via the field-programmable gate array (FPGA) mezzanine card (FMC) connector.

Front-End Circuit Power Supply

Options available to power the analog front-end circuit include the following:

• 5 V supply • ±15 V supply • P4 external connector

When using the P4 external connector, ensure that the L7, L8, R172, and R173 are not connected. These power supply options can be selected using the options in Table 4.

Clock

The AD7134 can either accept the master clock signal as a CMOS input or generate the master clock using the integrated oscillator with an external crystal.

See Table 5 for the different clock options to provide the master clock to the two AD7134 devices on the EVAL-AD7134FMCZ.

Reference

The AD7134 has a 4.096 V reference supply generated by the ADR444, which is a low noise reference.

LED

Status indicator LEDs display the state of the EVAL-AD7134FMCZ when illuminated, as described in Table 6.

Table 3. Power Rail Options Power Rail Link Internal LDO Regulator External Supply (Default) 1V8CLKVDD R226, R227 Not connected Mounted 1V8DVDD_1 R183 Not connected Mounted 1V8AVDD_1 R191 Not connected Mounted LDOIN_1 R187 Not connected Mounted 1V8DVDD_2 R199 Not connected Mounted 1V8AVDD_2 R197 Not connected Mounted LDOIN_2 R201 Not connected Mounted

Table 4. Front-End Circuit Power Options Power Rail Source (V) Mounted Not Mounted Default +PWRAFE 5 R172 L7 No

15 L7 R172 Yes −PWRAFE 0 R173 L8 No

−15 L8 R173 Yes

Table 5. Clock Options Clock Connection Mounted Not Mounted Comments Individual Crystals Not

applicable R143, R144, R145, R146

Default

MEMS Clock R144, R145 R143, R146 Remove Y2, Y3, C77, and C78; mount Y1 SDP CLK R144, R145 R143, R146 Remove Y2, Y3, C77, and C78; close R230 XCLKOUT Pin of Device 1 to XTAL2/CLKIN Pin of Device 2 R144, R146 R143, R145 Remove Y2, Y3, C77, and C78 XCLKOUT Pin of Device 2 to XTAL2/CLKIN Pin of Device 1 R143, R145 R144, R146 Remove Y2, Y3, C77, and C78

Table 6. LED Functions LED Description DS1 Power indication LED. When this LED is illuminated, it indicates that power is present on the EVAL-AD7134FMCZ. DS2 Power indication LED. When this LED is illuminated, it indicates a 5 V power to ADCs.










CONNECTORS AND SOCKETS The inputs and outputs can connect to the EVAL-AD7134FMCZ using the major connectors and sockets shown in Table 7.

Table 7. Connectors and Sockets Connector Function Connector Type J1 SMB connector for XTAL2_1 external clock input Straight printed circuit board (PCB) mount

SMB jack J2 to J17 Analog input SMB terminals for Channel 0 to Channel 7 Straight PCB mount SMB jacks P1, P7 8-pin connectors for the eight differential analog inputs Fixed terminal blocks, 8-pin, 3.81 mm, 90° P3 Benchtop power supply voltage input Fixed terminal blocks, 2-pin 2.54 mm, 90° P4 Benchtop power supply front-end voltage input and ground (0 V) to this

connector Fixed terminal blocks, 3-pin, 2.54 mm, 90°

P5, P9 Optional external connectors for driver, daughter board, Channel 0, and Channel 4

7-way, 2.54 mm vertical sockets

P6, P10 Optional external connectors for driver, daughter board, Channel 0, and Channel 4

7-way, 2.54 mm through-hole headers

P8 Connection to SDP-H1 board 160-pin, 10 mm, male, VITA 57 connector





SERIAL DATA INTERFACE 8-CHANNEL DATA The EVAL-AD7134FMCZ has two AD7134 devices with a total of eight ADC channels running in parallel. The conversion output data is sent to the SDP-H1 board using 10 interface lines, which consist of eight data lines (four from each device), a clock signal (DCLK), and a frame control signal (controlled by ODR). Table 8 lists the two mode connections, and Figure 4 shows the two data interfaces.

Take care when configuring the ADCs. The DCLK and ODR must only be driven by one ADC at a time.

Ensure that JP16 and JP17 are not kept open together. Also ensure that JP14 and JP15 are not kept open together.

DAISY-CHAINING AND MINIMAL INPUT/OUTPUT CONFIGURATION To configure the device in single-channel and two-channel daisy-chain configurations, use the R580 and R590 links. To set the device in minimal input/output mode, use the R600 and R610 links. The R580, R590, R600, and R610 links are not inserted on the board. Refer to the AD7134 data sheet for more details.

Table 8. Device Mode Options Device 1 Device 2 Mode Master Mode with DCLK Output Slave ODR and DCLK are generated by Device 1 and act as inputs for all other devices. Slave Mode with DCLK Input Slave ODR and DCLK are generated by the digital host.

ODR

MICROPROCESSOR/DSP/FPGA

MASTER

DOUT0DOUT1DOUT2DOUT3

DCLK

ODRDIN0DIN1DIN2DIN3DCLK

ODRSLAVE


DCLK

DIN4DIN5DIN6DIN7

ODR

MICROPROCESSOR/DSP/FPGA

SLAVE


DCLK

ODRDIN0DIN1DIN2DIN3DCLK

ODRSLAVE


DCLK

DIN4DIN5DIN6DIN7

2089

5-00

5

Figure 4. Data Interfaces







CONFIGURATION CONTROL MODES The AD7134 can be controlled either by configuring the pins or via the serial port interface (SPI), which is controlled using the PIN/SPI pin. The AD7134 is set either to SPI control mode or to pin control mode. The DEC0/DCLKIO, CLKSEL, MODE, and DEC1/DCLKMODE pins must be configured for pin control mode and SPI control mode. See Table 9 for the possible jumper configurations for these modes.

The configurations mentioned in Table 9 are mandatory for both pin control mode and SPI control mode. Use 10 kΩ resistors for the jumper links to set a specific pin.

PIN CONTROL MODE The R132 resistor mounted with 10 kΩ enables pin control mode. R131 is not connected. When in pin control mode, use the hardware pins shown in Table 9 and Table 10 to set the device configuration and to run the AD7134 in standalone mode. See Table 10 for the pin control mode configuration options. Use 10 kΩ resistors for the resistors to set a pin.

SPI CONTROL MODE The R131 resistor mounted with 10 kΩ enables SPI control mode. R132 is not connected. Use the SPI registers to set up the device for the desired configuration. The 4-wire or 3-wire SPI can be used to configure the device for all configurations except the PIN/SPI, DEC0/DCLKIO, CLKSEL, MODE, and DEC1/DCLKMODE pins.

Table 9. Jumper Configurations for Pin Control Mode and SPI Control Mode Device Pin Name Jumper High Low Default Device 1 and Device 2 PIN/SPI R131 Mounted Not connected Yes

R132 Not connected Mounted No Device 1 and Device 2 DEC1/DCLKMODE R125 Mounted Not connected No R126 Not connected Mounted Yes Device 1 MODE JP16 Open Closed High Device 1 CLKSEL R133 Mounted Not connected Yes R134 Not connected Mounted No Device 1 DEC0/DCLKIO JP14 Open Closed High Device 2 MODE JP17 Open Closed Low Device 2 CLKSEL R135 Mounted Not connected Yes R136 Not connected Mounted No Device 2 DEC0/DCLKIO JP15 Open Closed Low

Table 10. Pin Control Mode Configurations Device Pin Name Jumper High Low Default Device 1 and Device 2 DCLKRATE0/GPIO0 R91 Mounted Not connected No R92 Not connected Mounted Yes Device 1 and Device 2 DCLKRATE1/GPIO1 R93 Mounted Not connected No R102 Not connected Mounted Yes Device 1 and Device 2 DCLKRATE2/GPIO2 R103 Mounted Not connected No R104 Not connected Mounted Yes Device 1 and Device 2 PWRMODE/GPIO3 R105 Mounted Not connected Yes R106 Not connected Mounted No Device 1 and Device 2 FILTER0/GPIO4 R107 Mounted Not connected No R108 Not connected Mounted Yes Device 1 and Device 2 FILTER1/GPIO5 R109 Mounted Not connected No R112 Not connected Mounted Yes Device 1 and Device 2 FRAME0/GPIO6 R113 Mounted Not connected Yes R114 Not connected Mounted No Device 1 and Device 2 FRAME1/GPIO7 R115 Mounted Not connected Yes R116 Not connected Mounted No Device 1 and Device 2 FORMAT1/SCLK R137 Mounted Not connected Yes R138 Not connected Mounted No







Device Pin Name Jumper High Low Default Device 1 FORMAT0/CS R117 Mounted Not connected No

R118 Not connected Mounted Yes Device 2 FORMAT0/CS R119 Mounted Not connected No

R120 Not connected Mounted Yes Device 1 and Device 2 DEC3/SDO R121 Mounted Not connected Yes R122 Not connected Mounted No Device 1 and Device 2 DEC2/SDI R123 Mounted Not connected No R124 Not connected Mounted Yes Device 1 and Device 2 DEC1/DCLKMODE R125 Mounted Not connected No R126 Not connected Mounted Yes




EVALUATION BOARD SOFTWARE QUICK START PROCEDURES SOFTWARE INSTALLATION The AD7134 evaluation software installation package for the EVAL-AD7134FMCZ contains the evaluation application and the drivers for the SDP-H1 board.

Download the 32-bit National Instruments run-time engine Version 2019 SP1. Install this on the PC before installing the evaluation software.

Download the evaluation software from the AD7134 product page and install on a PC before using the EVAL-AD7134FMCZ.

Ensure that the SDP-H1 board is not connected to the PC during the installation process. To install the AD7134 evaluation software and SDP-H1 drivers, take the following steps:

1. Extract the zip file provided and double click the setup.exe file to begin the AD7134 evaluation software installation. Ensure that administrator access is available for the AD7134 evaluation software installation in the PC properties.

2. Click Yes in the User Account Control dialog box to permit the installer to create necessary directories and files (see Figure 5).

2089

5-00

6

Figure 5. User Account Control Dialog Box

3. When the installer initializes, the Destination Directory dialog box appears (see Figure 6). Enter the desired path for installation and then click Next. The default path is C:\Program Files (x86)\Analog Devices\.

2089

5-00

7

Figure 6. Setting Installation Destination Directories

4. The License Agreement dialog box appears, as shown in Figure 7. Read the agreement, select I accept the License Agreement, and then click Next.

2089

5-00

8

Figure 7. License Agreement

5. A summary of the installation appears, as shown in Figure 8. Click Next to continue.

2089

5-00

9

Figure 8. Installation Summary

6. A dialog box appears confirming a complete installation of the AD7134 evaluation software. Click Next to begin the SDP-H1 driver installation.

7. Ensure that the SDP-H1 board is disconnected from the PC and click Next when the SDP driver wizard appears (see Figure 9).















2089

5-01

0

Figure 9. SDP-H1 Driver Setup

8. Enter the desired path for the SDP-H1 drivers and click Install (see Figure 10).

2089

5-01

1

Figure 10. SDP-H1 Drivers Path

9. The Windows Security dialog box appears (see Figure 11). Click Install to allow the Windows Security dialog box to install the SDP-H1 drivers.

2089

5-01

2

Figure 11. Windows Security Dialog Box

10. When the driver installation is complete (see Figure 12), click Close to exit the installer and then restart the PC before using the EVAL-AD7134FMCZ.

2089

5-01

3

Figure 12. SDP-H1 Driver Installation Complete

USING THE SOFTWARE FOR TESTING When the AD7134 evaluation software and SDP-H1 driver installation is complete, double click the EVAL-AD7134FMCZ evaluation software shortcut on the desktop (see Figure 13). When the shortcut opens, the application is ready to accept commands from the user. The application has four tabs: Status, Registers, Waveform, and Analysis.

2089

5-00

2

Figure 13. EVAL-AD7134FMCZ Evaluation Software Shortcut

Status Tab

When the application opens and starts running, the Status tab shows the set configuration of Device 1 and Device 2 by default (see Figure 14). The application initializes the ADCs and loads the register map for a default configuration. This process takes a few seconds to complete.

2089

5-01

4

Figure 14. Status Tab











Registers Tab

All ADC register content appears as lists in the Registers tab (see Figure 15). The Device Select dropdown menu sets the device that corresponds to the register contents that appear in the Registers list. When a register is selected from the Registers list, the corresponding bit fields appear in the Bit Field Definition list. A description of the desired bit field is available in the Bit Field Description box. To update the contents of a register, click the individual bits in the Write Value box and then click the Update button to enter the contents. To update the contents of the Registers list with the current values contained in the ADC, click Read All Registers. Use the Save and Load buttons to write and read a register map file, respectively.

2089

5-01

5

Figure 15. Registers Tab

Waveform Tab

The Waveform tab displays the data captured (see Figure 16). Select the check box next to the desired channel to see that specific channel data. To obtain specific measurement parameters of a channel, select the desired measurement from the Analysis Channel dropdown menu. Click Sample to obtain a set of values. Click Continuous Sampling to view continuous data capture.

The user can enter an output data rate (ODR) value into the ODR Enter Value in Hz box. The DCLK (Hz) box value is set to 48 MHz when Device 1 is in master mode and Device 2 is in slave mode, as shown in Figure 16. When both devices are in slave mode, the DCLK value is fixed to 48 MHz. Enter values into the No. of Samples box to set the number of samples captured per channel.

2089

5-01

6

Figure 16. Waveform Tab

Analysis Tab

The Analysis tab shows the frequency spectrum and the required parameters pertaining to the channel selected in the Analysis Channel dropdown menu (see Figure 17).

To abort execution, click Exit in the top right corner of the window and close the application.

2089

5-01

7

Figure 17. Analysis Tab




EVALUATION BOARD SCHEMATICS AND ARTWORK

FOR

SIN

GLE

LD

O O

PE

RA

TIO

N, U

SE

VIN

OF

7V

1.8V

LD

O

5V L

DO

1000

MM

2 C

OP

PE

R T

O B

E P

LAC

ED

AN

D V

IN W

ILL

NO

T E

XC

EE

D 1

2V

1.2V

LD

O

10UF

66.5

K

AD

P23

11A

CP

Z-4-

R7

118K

NS

R02

40H

T1G

10UF

0.1U

F

DNI

0.1U

F1U

FDNI

1UF

DNI

DNI

10U

F

1UFDN

I

10U

F

DN

I

1UF

1UFD

NI

DN

I

10U

F

DNI

10U

F

10UF

RE

D

DN

I

DN

ID

NI

SM

BJ1

6CA

0

RE

D

100K

11.3

K

100K

22K

0

10B

Q03

0PB

F17

2565

649

9K

1000

PF

1725

669

3K

DN

I

0

3300

PF

0

0

DN

ID

NI

AD

P17

0AU

JZ-1

.2

10K

DNI

DN

I

DN

I 10K

5.9K

DN

I

10U

F

DN

I

DN

I10

UFDN

I

RE

D RE

D

RE

D

RE

D

RE

D

RE

D

RE

D

RE

D

RE

D

RE

DR

ED

0.39

UF

AD

M71

55A

RD

Z-04

-R7

499K

RE

D

249K

11.3

K

100K

0

DN

I

RE

D

0DN

I

AD

M71

50A

RD

Z-5.

0RE

D

0

2.2U

H

6.8U

H

47K

TLM

S10

00G

S08

10K

2.2U

H

100U

F

47UF

47UF

DN

I

RE

D

RE

D

0.1UF

2.32

ME

G

NS

R02

40H

T1G

DN

I

RE

D

RE

D

3K

47UF

100U

F

22U

H

10UF

22K

47UF

15U

H

10UF

3.57

K

AD

P50

70A

CP

Z-R

7

0

0.01

5UF

63.4

K

RE

D

1UF

0.1U

F

187K

61.9

K

1UF

0

60.4

K

1UF

10U

F

60.4

K

15U

H

10UF

10UF

R29

R31

C4

C30

C28

C34

C35

C33

C2

C9

C1

C6

C11

C23

R21

3R

17

D1

R18

U2

DS

1

U3

R24

R19

R4

D3

R30

C25

R16

R11

P3

D2

R9

D4

L6

R16

8C

3

U4

P4

R2

R8

R20

R14

C15

L1

R26

U5

R22

0

R21

9

C29

C24

TP8 TP

9

TP10

TP17

TP18

TP16

TP12

TP15

TP5

TP4

TP1

TP11

C17R

13

R6

R25

TP19

TP2

TP6

R1

U1

R16

7

C20

R15

L2

C8

R5

R7

TP3

C5

TP7

R16

9

R22

TP14

TP13

C12

C7

R12

L3

C22

C13

C10R

3

C31

R23

L4

C14

TP21

R32

L5

C16

R21

8

C18

C19

C27

R21

C21

C32C26

C36

TP20

EN

VFB

2

VR

EG

VE

N1

5V_S

MP

S

5V_S

MP

S

+PW

RA

FE

+15V

1V8_

LDO

VM

2

1V2

-15V

VE

N1

–PW

RA

FE

VC

OM

P2

PV

IN

PFI

5V_L

DO

PV

IN

VFB

2

VC

OM

P1

VC

OM

P2

VE

N2

VFB

1

5V_S

MP

S

5V_L

DO

1V8_

SM

PS

PFI

VC

OM

P1V

FB1

EN

VR

EG

VE

N2

PV

IN

VM

2

1V8_

SM

PS

RS

TO

PAD

FB1

VM

2

EN

PV

IN1

SW

1S

W1

PGND1PGND1

BS

T1B

ST2

PGND2PGND2

SW

2S

W2

PV

IN2

WD

IFB

2

PO

R

PFO

PFI

TIM

ER

VR

EG

GND

PA

D

VIN EN

RE

FR

EF_

SE

NS

EG

ND

BY

PV

OU

TV

RE

G

PAD

SW

2

PVIN2PVINSYS

PVIN1

VR

EG

AGND

VR

EF

FB2

CO

MP

2E

N2

SS

EN

1

CO

MP

1FB

1

SLE

WS

EQ

SY

NC

/FR

EQ

INB

K

SW

1

PGND

GN

DN

C

VO

UT

EN

VIN

EP

VIN

EN

RE

FR

EF_

SE

NS

E

GN

D

BY

PV

OU

TV

RE

G

20895-018

Figure 18. Power Supplies




FOR

MIN

IMA

L I/O

MO

DE

DE

MO

FOR

PH

AS

E M

ISM

ATC

H D

EM

O

DA

ISY

CH

AIN

OP

TIO

NS

RE

SIS

TOR

S

0

0D

NI0

DN

I 0

DN

I

DN

I00

DN

I0

2.2U

F2.

2UF

0.1UF

10U

F

10K

10UF

10UF

10K

10K

10K

DN

I

DN

I

10K

10K

10K

DN

I

10K

DN

I

10K

10K

DN

I

10K

10K

10K

DN

I

10K

10K

DN

I

10K

DN

I

10K 10K

10UF

10K

10K

10K

10K

DN

I

10K

DN

I

DN

I

10K

10K

10K

M20

-999

0246

M20

-999

0246

10K

DN

I10

K

10K

10K

10K

DN

I

DN

I10

K

10K

10K

DN

I

10K

M20

-999

0246

M20

-999

0246

DN

ID

NI

10K

DN

I

DN

I

OP

EN

10K

10K

10K

DN

I

10K

DN

I10

K

0

0

CLO

SE

D

DN

I0

CLO

SE

D

OP

EN

48M

EG

HZ

1UF

0.1UF

10UF

DN

I

0.1UF

20PF

48M

EG

HZ

20PF

0.1UF

0.1UF

20PF

48M

EG

HZ

20PF

AD

R44

4BR

Z

0.1UF

10UF

10UF

10UF

0

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

AD

R44

4BR

Z

DN

I

0

0.1UF

0.00

1UF

0

DN

I

0 0 0

0

1UF

000 0

DN

I

DN

I

1K

0

0

0

0 0 0

0 0

1UF

0

0

00

0

0

0

0

0

10K

0

0

DN

ID

NI

DN

I

0

DN

I

DN

ID

NI

0

DN

I

0

0

DN

ID

NI

DN

I

DN

I

0

00 0

00

1K

0 0

0

131-

3701

-271

DN

I

AD

7134

AC

PZ

RE

D

AD

7134

AC

PZ

RE

D

0

RE

D

0

DN

I

0

0.1UF

0.1U

F

0.1U

F

0.1U

F

0.1U

F0.

1UF

0.1U

F

0.1U

F

0.1U

F

0.1U

F

0D

NI

DN

I0

0

DN

I0

DN

I

DN

I0

DN

I

R14

4

R14

3

R14

5

R14

6R

119

R12

0R11

7

R11

8

R10

7

R10

8R10

3

R10

4

R93

R10

2

R91

R92

R11

2R10

9

R11

3

R11

4 R11

5

R11

6

R10

5

R10

6

R13

7

R13

8

R12

2R12

1

R12

4

R12

3

R12

6R12

5

R13

5

R13

6

R13

3

R13

4

R12

7

R12

8

R13

0R12

9

R13

2

R13

1

R13

9

R14

0

R14

2

R14

1

C44

C47

C46

C62

C61

R222

R223

R221

R23

1

JP15

R21

7

C52

C45

C59

C57

JP14

C49

C83

C77

C82

C134

C78

C74

C67

C63

C66

C69

C56

R224

C68

C43

C135

C73R78

C71

JP16

C41

R54

C64

C51

R44

R34 R37

R39

R42

R43

U6

C48

R45

R47

R46

R69

R72

R55

R52

R73

R74

J1

R49

R79

R82

R75

C75

C54

R51

C55

C58

C60

R53

C80

C76

R83

C79

C72

C70

R66

R65

R68

R67

R64

R62

R70

U7 R

76

Y2

R77

TP11

0

Y1

C42

R81

R80 C

81

R85

R84

R71

R50

C50

C53

TP10

9

R48

R38

R40

R35

R36

Y3

U9

TP11

1

U8

R41

JP17

R23

0

C65

R63

R60

R61

R59

R56

R57

R58

AIN

0+_2

DO

UT1

_2

XTA

L2_2

ME

MS

CLK

CLK

OU

T_2

CLK

OU

T_1

DV

DD

5V_1

LDO

IN_2

IOV

DD

1V8C

LKV

DD

DE

C1/

DC

LKM

OD

E

DE

C0/

DC

LKIO

_1

FOR

MA

T0/C

SB

_1

FOR

MA

T0/C

SB

_2IO

VD

DIO

VD

D

IOV

DD

FILT

ER

0/G

PIO

4

PW

RM

OD

E/G

PIO

3

DC

LKR

ATE

2/G

PIO

2IO

VD

D

DC

LKR

ATE

1/G

PIO

1IO

VD

D

DC

LKR

ATE

0/G

PIO

0IO

VD

DFI

LTE

R1/

GP

IO5

IOV

DD

LDO

IN_1

1V8C

LKV

DD

_1

IOV

DD

FRA

ME

0/G

PIO

6IO

VD

D

FRA

ME

1/G

PIO

7IO

VD

D

IOV

DD

IOV

DD

FOR

MA

T1/S

CLK

IOV

DD

IOV

DD

1V8C

LKV

DD

DE

C3/

SD

OIO

VD

D

DE

C2/

SD

IIO

VD

D

IOV

DD

DE

C0/

DC

LKIO

_2

IOV

DD

1V8A

VD

D_1

CLK

SE

L_2

CLK

SE

L_1

MO

DE

_1

PD

NB

_1IO

VD

D

PD

NB

_2

PIN

B/S

PI

IOV

DD

1V8A

VD

D_2

1V8D

VD

D_2

AV

DD

5V_2

1V8C

LKV

DD

_2A

VD

D5V

_1

RE

FIN

_1V

CO

M_1

MO

DE

_2

VC

M_1

VC

OM

_2R

EFI

N_2

VC

M_2

1V8D

VD

D_1

IOV

DD

RE

FIN

_1

1V8D

VD

D_2

1V8A

VD

D_2

XTA

L2_1

1V8C

LKV

DD

PW

RM

OD

E/G

PIO

3

PW

RM

OD

E/G

PIO

3

DV

DD

5V_1

RE

FCA

P_1

LDO

IN_2

RE

FIN

_2

DV

DD

5V_2

XTA

L1_1

FOR

MA

T0/C

SB

_2

AIN

1+_2

DC

LKR

ATE

1/G

PIO

1

PIN53PIN52

FOR

MA

T0/C

SB

_1

PD

NB

_1

PIN51

DC

LKR

ATE

2/G

PIO

2

CLK

SE

L_1

XTA

L2_1

DO

UT0

_1D

OU

T1_1

DO

UT2

_1D

OU

T3_1

DE

C0/

DC

LKIO

_1

FOR

MA

T1/S

CLK

DE

C1/

DC

LKM

OD

ED

EC

2/S

DI

XTA

L2_2

FRA

ME

1/G

PIO

7

LDO

IN_1

DN

C1

MO

DE

_1

PIN

B/S

PI

CLK

OU

T_1

1V8C

LKV

DD

_1

1V8D

VD

D_1

DC

LKR

ATE

0/G

PIO

0

RE

SE

TB_1

DE

C3/

SD

O

OD

R

FRA

ME

0/G

PIO

6

FRA

ME

1/G

PIO

7

AIN

3–_1

AIN

3+_1

DC

LKR

ATE

0/G

PIO

0

DC

LKR

ATE

1/G

PIO

1

DC

LKR

ATE

2/G

PIO

2

AIN

3–_2

AIN

1–_2

AIN

0–_2

AIN

2+_1

AIN

1–_1

AIN

1+_1

AIN

0+_2

DE

C2/

SD

ID

EC

3/S

DO

FOR

MA

T1/S

CLK

OD

R

RE

SE

TB_2

PD

NB

_2

MO

DE

_2

PIN

B/S

PI

CLK

OU

T_2

CLK

SE

L_2

XTA

L1_2

XTA

L2_2

1V8C

LKV

DD

_2

RE

FIN

_2V

CM

_2

AV

DD

5V_2

DV

DD

5V_2

DO

UT3

_2D

EC

0/D

CLK

IO_2

DE

C1/

DC

LKM

OD

E

VC

M_1

RE

FIN

_1

XTA

L1_2

AIN

2+_2

AIN

2–_2

AIN

3+_2

AIN

0–_1

RE

FCA

P_1

DN

C2

FILT

ER

0/G

PIO

4

FILT

ER

1/G

PIO

5FR

AM

E0/

GP

IO6

FILT

ER

1/G

PIO

5

AIN

0+_1

DC

LK

IOV

DD

XTA

L1_1

AV

DD

5V_1

IOV

DD

VR

EF

1V8A

VD

D_1

FILT

ER

0/G

PIO

4

IOV

DD

SD

PC

LK

DC

LKD

OU

T0_2

DO

UT1

_2D

OU

T2_2

AIN

2–_1

OD

R

DC

LK

FOR

MA

T0/C

SB

_1

FOR

MA

T1/S

CLK

AIN

0-_2

AIN

3–_1

DO

UT0

_2D

OU

T2_1

AIN

3+_1

DO

UT3

_1

1

2

48

41

PAD56

5453

55

50

47

5251

49

45

1 2 3 4 5 6 7 8 9 10 11 12 13 14

16171819202122

2425262728

293031323334353637383940

4344

46

4

3

PA

D

5655545352515049484746454443

42 41 40 39 38 37 36 35 34 33 32 31 30 29

2827

2524232221201918171615

1413121110987654321

26

42

15

23

NC

NC

TRIM

VIN

GN

D

TPTP

VO

UT

NC

NC

TRIM

VIN

GN

D

TPTP

VO

UT

GN

D

GN

D

VD

DO

UT

GN

DO

E/S

T_N

/NC

PADPWRMODE/GPIO3

PDNRESET

DCLKRATE2/GPIO2DCLKRATE1/GPIO1DCLKRATE0/GPIO0

MODEPIN_N/SPIXCLKOUT

CLKSELXTAL1

XTAL2/CLKINCLKVDDCLKGND

AIN

3–A

IN3+

AG

ND

5A

IN2–

AIN

2+R

EFG

ND

RE

FCA

PR

EFI

NV

CM

AIN

1–A

IN1+

AG

ND

5A

IN0–

AIN

0+

DNCAGND5AVDD5DVDD5DGND5LDOINAGND1V8AVDD1V8DVDD1V8DGND1V8FRAME1/GPIO7FRAME0/GPIO6FILTER1/GPIO5FILTER0/GPIO4

IOG

ND

IOV

DD

OD

RD

CLK

DO

UT0

DO

UT1

DO

UT2

DO

UT3

DE

C0/

DC

LKIO

DE

C1/

DC

LKM

OD

ED

EC

2/S

DI

DE

C3/

SD

OFO

RM

AT1

/SC

LKFO

RM

AT0

/CS

PADPWRMODE/GPIO3

PDNRESET

DCLKRATE2/GPIO2DCLKRATE1/GPIO1DCLKRATE0/GPIO0

MODEPIN_N/SPIXCLKOUT

CLKSELXTAL1

XTAL2/CLKINCLKVDDCLKGND A

IN3–

AIN

3+A

GN

D5

AIN

2–A

IN2+

RE

FGN

DR

EFC

AP

RE

FIN

VC

MA

IN1–

AIN

1+A

GN

D5

AIN

0–A

IN0+

DNCAGND5AVDD5DVDD5DGND5LDOINAGND1V8AVDD1V8DVDD1V8DGND1V8FRAME1/GPIO7FRAME0/GPIO6FILTER1/GPIO5FILTER0/GPIO4

IOG

ND

IOV

DD

OD

RD

CLK

DO

UT0

DO

UT1

DO

UT2

DO

UT3

DE

C0/

DC

LKIO

DE

C1/

DC

LKM

OD

ED

EC

2/S

DI

DE

C3/

SD

OFO

RM

AT1

/SC

LKFO

RM

AT0

/CS

20895-019

Figure 19. ADC Main Page




AM

C C

ON

NE

CTO

RA

MC

CO

NN

EC

TOR

RE

D

AD

A40

75-2

AR

Z DN

I0

DN

I

0R

ED

00

0

DN

I0

DN

I00

2.2U

H

DN

I

2.2U

H 0

DN

I0

TLW

-107

-05-

G-S

SS

W-1

07-0

1-T-

S

RE

D

AD

A46

10-2

AR

MZ

AD

A40

75-2

AR

Z

DN

I

10U

F

AD

A46

10-2

AR

MZ

0.1UF

0

0

0

10U

F

0.00

1UF

0.1UF

0.1UF

AD

A40

75-2

AR

Z

AD

A46

10-2

AR

MZ

0.1UF

DN

I

0.00

1UF

RE

D

10K

DN

I

AD

A40

75-2

AR

Z

0

DN

I

RE

D

DN

I

DN

I

0

10K

RE

D

RE

D

10K

AD

A46

10-2

AR

MZ

0

0

0

DN

I

0

RE

D

DN

I

AD

A40

75-2

AR

Z

AD

A46

10-2

AR

MZ

SS

W-1

07-0

1-T-

STL

W-1

07-0

5-G

-S

DN

I

RE

D

0

10K

DN

I

0

0

0

DN

I

AD

A40

75-2

AR

Z

RE

D

RE

D

RE

D

RE

D

RE

D

0

DN

I

DN

IDN

I

DN

I

DN

I

DN

I

DN

I

DN

I

0

DN

I

DN

I

DN

I

DN

I

00

0

0

0 00

DN

ID

NI

AD

A46

10-2

AR

MZ

DN

I

00

DN

I

DN

I

DN

ID

NI

R15

0

R14

7

R15

6

R15

5

R17

2

R17

3L8L7

R17

0

R17

1

R15

8

R15

7TP

107

TP10

8

C11

3

C11

2

C86 C89

R16

3

A9

P10

C109

R17

6

C108

C155

C13

3

TP48

A10

C127

R15

1 R15

3

R15

2

TP90

A1

C125

R96

R87R

86 R89

C84 C85C88C

87

C92

TP31

R15

4

C154

P9

R99

TP32

TP93

R10

0

TP36

R10

1

R90

C124

R98

TP47

TP30

TP35

TP89

TP88

TP94

R15

9 R16

4

R16

0

R16

2

C126

A5

C13

2

R17

5

R16

5

R16

1R16

6

A5

C93

R97

A9R11

0

R95

R94

A1

A10

P5

A9

A5

P6

R11

1

A10

A1

+15V

AIN

0+_1

AIN

0+_I

NP

_1

AFE

OU

T0+_

1A

IN0+

_2A

IN0+

_IN

P_2

AIN

0–_1

AIN

0-_I

NP

_1

AFE

OU

T0–_

1A

FEO

UT0

-_2

+PW

RA

FE

-PW

RA

FE

5V_S

MP

S

–15V

AFE

OU

T0+_

2

AIN

0-_I

NP

_2A

IN0-

_2

–PW

RA

FE

+PW

RA

FE–PW

RA

FE

VC

OM

_2

AIN

0–_I

NP

_1

AIN

0+_I

NP

_1

VC

OM

_1

AIN

0+_I

NP

_2

VC

OM

_2

AIN

0–_I

NP

_2

VC

OM

_1 AIN

0+_I

NP

_1

VC

OM

_2

AFE

OU

T0–_

2

+PW

RA

FE

AFE

OU

T0-_

1

AFE

OU

T0+_

1

AIN

0+_I

NP

_2

AIN

0–_I

NP

_2

–PW

RA

FE

VC

OM

_1–P

WR

AFE

+PW

RA

FE

AIN

0–_I

NP

_1

+PW

RA

FE

AFE

OU

T0+_

2

8

62 3

8

7

7

6

6

2

8 4 44

3

12

132

55

7

56

31 7

5

1

V+ V–

V+ V–

OU

T A

+IN

A

–IN

A

+IN

A

–IN

A

OU

T B

+IN

B

–IN

BOU

T B

+IN

B

–IN

B

OU

T A

+IN

A

–IN

A OU

T B

+IN

B

–IN

BOU

T A

+IN

A

–IN

A

OU

T B

+IN

B

–IN

B

OU

T A

V+ V–

V+ V–

20895-020

0.1U

F

0.1U

F

0.1U

F

0.1U

F

0.1U

F

0.1U

F

0.1U

F

0.1U

F

0.1U

F0.1U

F

0.1U

F

0.1U

F

Figure 20. Front-End Section




RE

D

0

10K

0

1727

078

131-

3701

-271

131-

3701

-271

131-

3701

-271

131-

3701

-271

131-

3701

-271

131-

3701

-271

131-

3701

-271

1727

078

AS

P-1

3460

4-01

10K

AS

P-1

3460

4-01

AS

P-1

3460

4-01

AS

P-1

3460

4-01

131-

3701

-271

131-

3701

-271

131-

3701

-271

131-

3701

-271

131-

3701

-271

10B

Q03

0PB

FM

24C

02-W

MN

6TP

131-

3701

-271

131-

3701

-271

131-

3701

-271

131-

3701

-271

RE

D

RE

DR

ED

RE

DR

ED

RE

D

RE

D

RE

D

RE

D

RE

D

RE

D

RE

D

RE

D

RE

D

RE

D

RE

DRE

D

RE

D RE

D

RE

D

RE

D

RE

D

RE

D

RE

D

RE

D

RE

D

RE

D

RE

D

RE

D

RE

DR

ED

RE

D

0

RE

D

RE

D

0

RE

D

RE

D

RE

D

0

R28

R10

R27

R88

R148

P8

J5J9

J13

J17

J4J8

J12

J16

J7J1

1

P7

J2J6

J10

J15

J14

R149

P8

P8

P8

U10

P1

J3

D5

TP49

TP61

TP56

TP59

RE

DTP

63

TP53

TP57

TP50

TP54

TP58

TP60

TP62

TP64

TP67

TP68

TP52

TP69 TP

70

TP84

TP81

TP71

TP74

TP76

TP79

TP82

TP85

TP87

TP80

TP78

TP77

TP51

TP55

TP72

R33

TP86

TP83

TP73

TP75

TP66

TP65

OD

R

RE

SE

TB_1

DO

UT2

_1

DC

LK

AIN

3–_1

AIN

2+_1

AIN

1–_1

AIN

1+_1

AIN

3+_1

AIN

2–_1

AIN

1+_2

AIN

3–_2

AIN

1–_2

AIN

2+_2

AIN

3+_2

AIN

2–_2

DE

C0/

DC

LKIO

_2

PW

RM

OD

E/G

PIO

3

IOV

DD MO

DE

_1

PD

NB

_1

DO

UT3

_1

PD

NB

_2

FILT

ER

1/G

PIO

5FI

LTE

R0/

GP

IO4

MO

DE

_2

OD

RD

OU

T0_1

DE

C3/

SD

O

DO

UT0

_2D

OU

T1_2

DC

LKR

ATE

2/G

PIO

2

GA

03P3V

AU

X

SD

A

PIN

B/S

PI

GA

0

3P3V

AU

X

DO

UT1

_1

DE

C1/

DC

LKM

OD

E

DC

LKR

ATE

0/G

PIO

0

SD

PC

LK

DE

C0/

DC

LKIO

_1

DC

LKR

ATE

1/G

PIO

1

DO

UT3

_2

RE

SE

TB_2

SC

L

AIN

0+_I

NP

_1

AIN

0–_I

NP

_1

AIN

0–_I

NP

_2

AIN

0+_I

NP

_2

PV

IN

DE

C2/

SD

I

GA

1

GA

1

FRA

ME

1/G

PIO

7FR

AM

E0/

GP

IO6

FOR

MA

T0/C

SB

_2FO

RM

AT0

/CS

B_1

FOR

MA

T1/S

CLK

DO

UT2

_2

4 87321 5 6

GN

D3P

3VG

ND

12P

0VG

ND

12P

0VG

A0

GN

DG

ND

SD

AS

CL

GN

DG

ND

LA27

_NLA

27_P

GN

DG

ND

LA18

_N_C

CLA

18_P

_CC

GN

DG

ND

LA14

_NLA

14_P

GN

DG

ND

LA10

_NLA

10_P

GN

DG

ND

LA06

_NLA

06_P

GN

DG

ND

DP

0_M

2C_N

DP

0_M

2C_P

GN

DG

ND

DP

0_C

2M_N

DP

0_C

2M_P

GN

D

3P3V

GN

D3P

3VG

ND

3P3V

GA

1TR

ST_

LTM

S3P

3VA

UX

TDO

TDI

TCK

GN

DLA

26_N

LA26

_PG

ND

LA23

_NLA

23_P

GN

DLA

17_N

_CC

LA17

_P_C

CG

ND

LA13

_NLA

13_P

GN

DLA

09_N

LA09

_PG

ND

LA05

_NLA

05_P

GN

DLA

01_N

_CC

LA01

_P_C

CG

ND

GN

DG

BTC

LK0_

M2C

_NG

BTC

LK0_

M2C

_PG

ND

GN

DP

G_C

2M

VS

S

SC

L

SD

A

WC

E2

E1

E0V

CC

VA

DJ

GN

DLA

32_N

LA32

_PG

ND

LA30

_NLA

30_P

GN

DLA

28_N

LA28

_PG

ND

LA24

_NLA

24_P

GN

DLA

21_N

LA21

_PG

ND

LA19

_NLA

19_P

GN

DLA

15_N

LA15

_PG

ND

LA11

_NLA

11_P

GN

DLA

07_N

LA07

_PG

ND

LA04

_NLA

04_P

GN

DLA

02_N

LA02

_PG

ND

CLK

0_M

2C_N

CLK

0_M

2C_P

GN

DP

RS

NT_

M2C

_LV

RE

F_A

_M2C

GN

DV

AD

JG

ND

LA33

_NLA

33_P

GN

DLA

31_N

LA31

_PG

ND

LA29

_NLA

29_P

GN

DLA

25_N

LA25

_PG

ND

LA22

_NLA

22_P

GN

DLA

20_N

LA20

_PG

ND

LA16

_NLA

16_P

GN

DLA

12_N

LA12

_PG

ND

LA08

_NLA

08_P

GN

DLA

03_N

LA03

_PG

ND

LA00

_N_C

CLA

00_P

_CC

GN

DG

ND

CLK

1_M

2C_N

CLK

1_M

2C_P

GN

D

20895-021

Figure 21. Input and Output Connectors




RED

47U

F

0D

NI 0

DN

I0

DN

I

0

DN

I0D

NI

0

DN

I0

0

0

0

0

DN

I0

DN

I0

0

0

DN

I

47U

F

RED

0

1.1KAP

T160

8LZG

CK

0

DN

I0

0

DN

I

DN

I0

0 0

0

DN

I0

0

RED

DN

I0

RED

0 0

47U

F47

UF

RED

RED

RED

RED

R18

1

R18

0

R18

7

R18

6

R18

3

R18

2

R20

0

R20

1R

177

R17

4

R18

5

R18

4

R18

9

R18

8

R19

3

R19

2

R19

5

R19

4 R19

9

R19

8

R19

6

R19

7

R19

0

R19

1

R17

8 R17

9

R22

6

TP22

C39

TP29

C37

R21

4

TP24

R22

7

C38

TP23

TP28

C40

TP25

DS2

TP26

TP27

1V8_

SMPS

AVD

D5V

_2

1V8C

LKVD

D_1

5V_S

MPS

DVD

D5V

_2

AVD

D5V

_1

1V8_

SMPS

5V_L

DO

1V8_

SMPS

IOVD

D1V

2

LDO

IN_1

5V_S

MPS

5V_S

MPS

DVD

D5V

_1

1V8D

VDD

_1

5V_S

MPS

5V_L

DO

1V8_

LDO

1V8_

SMPS

LDO

IN_2

VREF

5V_S

MPS

5V_L

DO

5V_L

DO

5V_S

MPS

5V_L

DO

5V_S

MPS

1V8D

VDD

_21V

8_LD

O

1V8_

SMPS

1V8A

VDD

_21V

8_SM

PS

1V8_

LDO

1V8A

VDD

_11V

8_SM

PS

1V8_

LDO

1V8C

LKVD

D1V

8_SM

PS

1V8_

LDO

1V8C

LKVD

D_2

5V_S

MPS

20895-022

Figure 22. Power Link Options




2089

5-02

3

Figure 23. Layer 1, Primary Layer

2089

5-02

4

Figure 24. Layer 2, Ground Layer




2089

5-02

5

Figure 25. Layer 3, Supply Layer

2089

5-02

6

Figure 26. Layer 4, Bottom Layer




ORDERING INFORMATION BILL OF MATERIALS

Table 11. Qty Reference Designator Description Manufacturer Part Number 1 PCB PCB Revision C Analog Devices EVAL-AD7134FMCZ 2 A9, A10 IC, ultralow noise amplifiers at lower power Analog Devices ADA4075-2ARZ

3 C1, C9, C28 Ceramic capacitors, X5R, general-purpose Murata GRM216R61E105KA12D 6 C112, C113, C57, C59,

C61, C62 Ceramic capacitors, X7R, general-purpose Murata GRM31CR71E106KA12L

4 C5, C7, C10, C12 Ceramic capacitors, X5R, general-purpose Murata GRM31CR60J476ME19L 18 C4, C16, C19, C41, C43,

C46, C49, C65, C67, C68, C73, C74, C108, C109, C134, C135, C150, C151

Ceramic capacitors, X7R, general-purpose Murata GRM188R71H104JA93D

8 C2, C6, C11, C26, C36, C56, C66, C69

Ceramic capacitors, X5R, general-purpose Murata GRM21BR61D106KE15L

3 C63, C154, C155 Ceramic capacitors, C0G (NP0), general-purpose Murata GRM1885C1H102JA01D 5 C13, C22, C23, C31, C32 Ceramic capacitors, X5R, general-purpose Murata GRM31CR61E106KA12L 1 C14 Ceramic capacitor, X7R, general-purpose Murata GRM188R71H153KA01D 1 C15 Ceramic capacitor, X7R Yageo 2238 586 15629 1 C17 Ceramic capacitor, C0G, 0603 TDK C1608C0G2A102J 1 C18 Ceramic capacitor, X5R, general-purpose Murata GRM188R61C105KA93D 1 C20 Ceramic capacitor, X7R TDK C3216X7R1C106M160AC 2 C21, C27 Ceramic capacitors, X5R, general-purpose Murata GRM188R61E105KA12D 2 C3, C8 Ceramic capacitors, X5R, general-purpose Murata GRM31CR60J107ME39L 4 C37 to C40 Ceramic capacitors, high value multilayer, X5R, 0805 Taiyo Yuden JMK212BJ476MG-T 4 C42, C47, C52, C64 Ceramic capacitors, X7R AVX 0603YC105KAT2A 2 C44, C45 Ceramic capacitors, X7R, general-purpose Murata GRM188R71A225KE15D 1 D1 Diode, transient voltage suppressor (TVS), bidirectional Littelfuse SMBJ16CA 2 D2, D5 Diodes, Schottky, rectifier, surface-mount diode (SMD) International Rectifier 10BQ030PBF 2 D3, D4 Diodes, Schottky, barrier ON Semiconductor NSR0240HT1G 1 DS1 LED, SMD, 0603, red Vishay TLMS1000-GS08 1 DS2 LED, chip lamp, green, 525 nm (clear) Kingbright Electronic APT1608LZGCK 17 J1 to J17 PCB connectors, SMB, PC mount, jack receptacle Cinch Connectivity

Solutions, Inc. 131-3701-271

2 SL25, SL26 Resistors, spacer jumper solder pads, Link 2 to Link 3 TDK GLFR1608T2R2M-LR 14 SL1 to SL3, SL5 to SL7,

SL15 to SL18, SL21 to SL24

Resistors, spacer jumper solder pads, Link 2 to Link 3 Panasonic ERJ-3GEY0R00V

9 JP1 to JP3, JP5, JP6, JP9, JP10, JP12, JP13

Resistors, spacer jumpers, 10 kΩ, Link 2 to Link 3 Panasonic ERJ-3EKF1002V

4 SL8 to SL10, SL20 Resistors, spacer jumper solder pads, Link 1 to Link 2 Panasonic ERJ-3GEY0R00V 10 JP4, JP7, JP8, JP11, JP27

to JP32 Resistors, spacer jumpers, 10 kΩ, Link 1 to Link 2 Panasonic ERJ-3EKF1002V

2 JP14, JP16 PCB connectors, header, single-row, 2-way, open Harwin M20-9990246 2 JP15, JP17 PCB connectors, header, single-row, 2-way, closed Harwin M20-9990246 2 L1, L2 Thick film chip resistors Panasonic ERJ-6GEY0R00V 1 L3 Inductor, shielded power, 5.6 A, 0.05512 Ω, dc resistance

(DCR) Coilcraft Inc. XAL6060-223MEB

1 L4 Inductor shielded power, 5.8 A, 0.03977 Ω DCR Coilcraft Inc. XAL6060-153MEB 1 L5 Inductor, shielded power Murata LQH32PN6R8NN0L 1 L6 Inductor, shielded power Coilcraft Inc. ME3220-153KLB 2 P1, P7 PCB connectors, terminal block, 8-position, green Phoenix Contact 1727078 2 P6, P10 PCB connectors, header, low profile Samtec TLW-107-05-G-S

https://www.analog.com/ADA4075-2?doc=EVAL-AD7134FMCZ-UG-1599.pdf




Qty Reference Designator Description Manufacturer Part Number 1 P3 PCB connector, terminal block, 2-position Phoenix Contact 1725656 1 P4 PCB connector, terminal block, 2.54 mm, 3-position Phoenix Contact 1725669 2 P5, P9 PCB connectors, 0.025 in, square post socket Samtec SSW-107-01-T-S 1 P8 PCB connector, single-ended array, male, 160-position,

use alternate symbol for RF application Samtec ASP-134604-01

20 R18, R21, R23, R86, R87, R95, R96, R99, R101, R110, R111, R151, R152, R160 to R162, R166, R175, R176, R218

Film resistors, SMD, 0603 Panasonic ERJ-3GEY0R00V

2 R11, R16 Precision thick film chip resistors Panasonic ERJ-3EKF4993V 1 R12 General-purpose chip resistor Yageo RC0603FR-0766K5 1 R13 Precision thick film chip resistor Panasonic ERJ-6ENF1873V 2 R7, R14 Precision thick film chip resistors Panasonic ERJ-6ENF6042V 2 R8, R15 Precision thick film chip resistors Panasonic ERJ-3EKF1132V 47 R33, R35 to R55, R62,

R64 to R85, R226, R227 Standard thick film chip resistors Vishay CRCW06030000Z0EAHP

1 R17 General-purpose chip resistor Yageo RC0603FR-0747KL 1 R19 Precision thick film chip resistor Panasonic ERJ-3EKF2493V 2 R2, R5 Thick film chip resistors Vishay CRCW060322K0FKEA 2 R3, R213 Film resistors, SMD, 0603 Panasonic ERJ-3GEYJ302V 1 R214 Thick film chip resistor Bourns CR0603-FX-1101ELF 3 R24 to R26 Thick film chip resistors Bourns CR0603-FX-1003ELF 1 R29 Precision thick film chip resistor Panasonic ERJ-3EKF1183V 1 R30 General-purpose chip resistor Yageo RC0805FR-072M32L 1 R31 Precision thick film chip resistor, R0603 Panasonic ERJ-3EKF6342V 1 R32 Thick film chip resistor, standard Vishay CRCW08053K57FKEA 2 R34, R63 Thick film chip resistors Multicomp (SPC) MC0063W060311K 6 R89, R90, R148, R149,

R153, R154 Film resistors, SMD, 0603 Panasonic ERJ-3EKF1002V

5 R6, R221 to R224 Pulse proof, thick film chip resistors Vishay CRCW060310K0FKEAHP 1 R9 Precision thick film chip resistor Panasonic ERJ-3EKF6192V 85 TP1 to TP32, TP35, TP36,

TP47 to TP90, TP93, TP94, TP107 to TP111

PCB connectors, test point, red Keystone Electronics 5000

1 U10 IC, 2 kb, serial I2C bus, electrically erasable programmable read only memory (EEPROM)

STMicroelectronics M24C02-WMN6TP

1 U2 IC, 18 V, dual, 1 A synchronized, switching regulator Analog Devices ADP2311ACPZ

1 U3 IC, dc-to-dc switch regulator with independent positive and negative outputs

Analog Devices ADP5070ACPZ-R7

2 U6, U7 IC, 24-bit, continuous time Σ-Δ ADCs Analog Devices AD7134ACPZ

2 U8, U9 Ultralow noise LDO regulators, junction field effect transistor (XFET) voltage references with current sink and source

Analog Devices ADR444BRZ

2 Y2, Y3 IC crystal oscillators, 20 pF load capacitance ECS ECS-480-20-30B-DU

https://www.analog.com/ADP2311?doc=EVAL-AD7134FMCZ-UG-1599.pdf

https://www.analog.com/ADP5070?doc=EVAL-AD7134FMCZ-UG-1599.pdf






NOTES

I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

ESD Caution ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.

Legal Terms and Conditions By using the evaluation board discussed herein (together with any tools, components documentation or support materials, the “Evaluation Board”), you are agreeing to be bound by the terms and conditions set forth below (“Agreement”) unless you have purchased the Evaluation Board, in which case the Analog Devices Standard Terms and Conditions of Sale shall govern. Do not use the Evaluation Board until you have read and agreed to the Agreement. Your use of the Evaluation Board shall signify your acceptance of the Agreement. This Agreement is made by and between you (“Customer”) and Analog Devices, Inc. (“ADI”), with its principal place of business at One Technology Way, Norwood, MA 02062, USA. Subject to the terms and conditions of the Agreement, ADI hereby grants to Customer a free, limited, personal, temporary, non-exclusive, non-sublicensable, non-transferable license to use the Evaluation Board FOR EVALUATION PURPOSES ONLY. Customer understands and agrees that the Evaluation Board is provided for the sole and exclusive purpose referenced above, and agrees not to use the Evaluation Board for any other purpose. Furthermore, the license granted is expressly made subject to the following additional limitations: Customer shall not (i) rent, lease, display, sell, transfer, assign, sublicense, or distribute the Evaluation Board; and (ii) permit any Third Party to access the Evaluation Board. As used herein, the term “Third Party” includes any entity other than ADI, Customer, their employees, affiliates and in-house consultants. The Evaluation Board is NOT sold to Customer; all rights not expressly granted herein, including ownership of the Evaluation Board, are reserved by ADI. CONFIDENTIALITY. This Agreement and the Evaluation Board shall all be considered the confidential and proprietary information of ADI. Customer may not disclose or transfer any portion of the Evaluation Board to any other party for any reason. Upon discontinuation of use of the Evaluation Board or termination of this Agreement, Customer agrees to promptly return the Evaluation Board to ADI. ADDITIONAL RESTRICTIONS. Customer may not disassemble, decompile or reverse engineer chips on the Evaluation Board. Customer shall inform ADI of any occurred damages or any modifications or alterations it makes to the Evaluation Board, including but not limited to soldering or any other activity that affects the material content of the Evaluation Board. Modifications to the Evaluation Board must comply with applicable law, including but not limited to the RoHS Directive. TERMINATION. ADI may terminate this Agreement at any time upon giving written notice to Customer. Customer agrees to return to ADI the Evaluation Board at that time. LIMITATION OF LIABILITY. THE EVALUATION BOARD PROVIDED HEREUNDER IS PROVIDED “AS IS” AND ADI MAKES NO WARRANTIES OR REPRESENTATIONS OF ANY KIND WITH RESPECT TO IT. ADI SPECIFICALLY DISCLAIMS ANY REPRESENTATIONS, ENDORSEMENTS, GUARANTEES, OR WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THE EVALUATION BOARD INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, TITLE, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS. IN NO EVENT WILL ADI AND ITS LICENSORS BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT, OR CONSEQUENTIAL DAMAGES RESULTING FROM CUSTOMER’S POSSESSION OR USE OF THE EVALUATION BOARD, INCLUDING BUT NOT LIMITED TO LOST PROFITS, DELAY COSTS, LABOR COSTS OR LOSS OF GOODWILL. ADI’S TOTAL LIABILITY FROM ANY AND ALL CAUSES SHALL BE LIMITED TO THE AMOUNT OF ONE HUNDRED US DOLLARS ($100.00). EXPORT. Customer agrees that it will not directly or indirectly export the Evaluation Board to another country, and that it will comply with all applicable United States federal laws and regulations relating to exports. GOVERNING LAW. This Agreement shall be governed by and construed in accordance with the substantive laws of the Commonwealth of Massachusetts (excluding conflict of law rules). Any legal action regarding this Agreement will be heard in the state or federal courts having jurisdiction in Suffolk County, Massachusetts, and Customer hereby submits to the personal jurisdiction and venue of such courts. The United Nations Convention on Contracts for the International Sale of Goods shall not apply to this Agreement and is expressly disclaimed.

©2020 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. UG20895-4/20(0)

https://www.analog.com
