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1. PUBLISHABLE SUMMARY The main and last objective of EUROSOI Network is to establish Europe as the

international scientific leader in Silicon on Insulator (SOI) Technology, Devices, Circuits and Systems. In this sense, the EUROSOI+ co-ordination efforts during this second reporting period have been focused on the promotion of those activities that contribute to improving the role of the European Semiconductor Industry with regard to SOI and to the knowledge that will enable Europe to compete internationally.

Although EUROSOI achievements during FP6 have been many and very important for the European SOI technology, and the situation of SOI technology in Europe has greatly improved during the last three years, there are plenty of challenges at the near future. Even if we now are in the right direction, Europe is still far away from the pursued international leadership. After the elaboration of the State-of-the-Art report and EUROSOI Roadmap we have identified the main actors, the strong points and weaknesses of Silicon-On-Insulator technology in Europe. All this information is collected in the EUROSOI Roadmap, where the challenges which will have to be faced in the future are also identified. Our first stage was a passive one (collecting and structuring the information). This second stage is being much more active; we are not only looking at around us, collecting and re-structuring the available information, but we have passed to the action in a more active role, developing the tasks, fostering creation of consortiums and leading the projects and proposals which give Europe and the European Semiconductor Industry the international leadership which they deserve as pioneers and big developers of SOI technology.

The best way to reach this goal is to try to spread the SOI technology all over Europe, making it accessible to any European semiconductor actor:

“We want that SOI technology is reachable to any European research group or

Fabless Semiconductor company; we want that any circuit design has the chance to become a SOI circuit using European technology.”

To do so, we have to work in two directions: i) the training of researchers and engineers in the particularities of this

technology, i.e., in the design of circuits taking advantage of SOI technology. Spreading and promotion of the benefits and advantages of SOI technology.

ii) the development of a platform which offers SOI technology for the actual fabrication of SOI circuits

It is widely accepted by the International Semiconductor Community that most of the

electronic circuits (in the whole application spectra) will have a better performance, and therefore, they will be more competitive, if they are built using SOI technology. However, nowadays it is not easy to have access to this technology, even when we count in Europe with some of the most advanced SOI technologies all over the World.

Up to now, a lot of research activities have been pursued in Europe around SOI at different levels: substrate, device, and circuit. Since few years, advanced SOI technologies have been developed in research labs in order to address the downscaling required for 32 nm nodes and below. Today such researches are mainly dedicated to technology development. Among the various ones, we can mention the LETI Fully Depleted SOI technology (developed with high-k and metal gate) that currently has enough maturity to be evaluated at circuit level. So, it becomes obvious that a research-dedicated platform is

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necessary in order to address the circuit design aspects, focussing on the advantages of such technology for Low Power applications. Access to such platform is a long-time wish of European researchers. Hence, the main goal of EUROSOI+ is to coordinate the formation of such research-dedicated platform which will provide, through the integration in EUROPRACTICE, prototyping and Multi-Project-Wafers (MPW) in SOI open to all European companies using LETI SOI process. We are co-ordinating all the activities which will make this platform a reality. In fact, CEA-LETI has launched an Exploratory MPW (Multi Project Wafers) initiative based on FDSOI (Fully Depleted SOI) 20nm process through CMP (Circuit Multi Project, http://cmp.imag.fr), opening the access of its 300mm infrastructure to the design community. This MPW offer is partly supported by EUROSOI+.

This process will allow Researchers and Engineers to experiment the benefits of SOI on an advanced technology node. CEA-LETI has developed both an advanced High-K/Metal Gate FDSOI process and a number of specific design and simulation tools based on industry standard design flow packages. FDSOI technology presents key advantages over conventional bulk technology for future nodes: the electrostatic integrity of the transistors is ensured by the thinness of the body without the need for extra litho steps, like in the case of FinFETs, or of channel doping. The consequence is a planar technology that exhibits at the same time excellent short channel behaviour and significant improvement of the variability as shown in a number of recent papers.

The basis of LETI technology offer will be the following: • CMOS transistors with an undoped channel and a silicon film thickness of

6nm • High-k / Metal Gate stack • Single threshold voltage (Vth) n- and pMOSFET with balanced Vth of ±0.4V • Associated Design Kit, including SPICE model (Verilog-A language) model

cards extracted from silicon data, p-cells, DRC, LVS, schematic, parasitics • Design Kit documentation

The first run is scheduled to be launched in September 2011. All details can be found at CMP website (http://cmp.imag.fr).

The two lines referenced above, summarize EUROSOI+ activities during this

period:

I. Training and promotional activities.

a. Website database (http://www.eurosoi.org) i. EUROSOI Virtual Journal

http://www.eurosoi.org/articles.asp ii. EUROSOI Landmark publications

http://www.eurosoi.org/landmark_publications.asp iii. EUROSOI Newsletters

http://www.eurosoi.org/newsletters.asp iv. EUROSOI News&Announcements

http://www.eurosoi.org/news.asp v. EUROSOI Training material database

http://www.eurosoi.org/tutorials.asp

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b. Organization of Training events and Tutorials

i. Multigate SOI MOSFETs (January 23rd,2008, Cork, Ireland) • The SOI MOSFET: from Single Gate to Multigate (Prof. Jean-Pierre Colinge,

Tyndall, Ireland) • Physics of the Multigate MOS System (Prof. Bogdan Majkusiak, Warsaw

University of Technology, Poland) • Mobility in Multigate MOSFETs (Francisco Gamiz, University of Granada, Spain) • Multigate MOSFET Technology (Malgorzata Jurczak, IMEC, Belgium) • Radiation Effects in Advanced Single- and Multi-Gate SOI MOSFETs (Véronique

Ferlet-Cavrois, CEA, France) • Multigate MOSFET Circuit Design (Gerhard Knoblinger, Infineon, Germany)

ii. First FDSOI tutorial of the Thematic Network on SOI technology, devices and circuits (November 17-18, 2008, Grenoble, France)

• Introduction of the First FDSOI Tutorial (Olivier Faynot, CEA-LETI, Grenoble, France)

• Variability Issues (Asen Asenov, Glasgow University) • Fully-Depleted SOI for Nanometer Subthreshold Circuits (D. Bol, UCL, Belgium) • Compact Modeling of Undoped FDSOI MOSFET (O. Rozeau, LETI, Grenoble,

France) • FDSOI Devices: Physics and Characterization (Prof. Sorin Cristoloveanu, IMEP,

Grenoble, France) • FDSOI Circuit Design (Alexandre Valentian, CEA-LETI, Grenoble, France) • FDSOI: Technology and Electrical Results (F. Andrieu, CEA-LETI, Grenoble,

France) • EUROSOI+: European Platform for low-power applications on Silicon on

Insulator Technology (Prof. F. Gámiz, UGR, Spain)

iii. SOI from modelling to design (January 19th, 2009, Goteborg, Sweden) • Modelling of ultra thin body SOI nano-transistors (Prof. Luca Selmi, University of

Udine) • Strained channel materials for SOI transistors (Prof.Siegfried Mantl,

Forschungszenter, Jülich, Aachen) • SOI technology: an opportunity for RF designers, (Prof.Jean-Pierre Raskin,

Université Catholique de Louvain) • From MEMS to embedded NEMS (Dr.Julien Arcamone, CEA-LETI, Grenoble) • Ultimately thin carbon on insulators : Graphene (Prof.Max Lemme, Harvard

University, Cambridge, Massachusetts) • SOI Circuits: Do you want Partially Depleted or Fully Depleted Devices?

(Prof.Jean-Pierre Colinge, Tyndall National Institute, Cork) • Digital SOI design in the nanometer era - from high-performance to ultra-low-

power circuits (Prof.David Bol, Université Catholique de Louvain)

iv. SOI Concepts: from materials to devices and applications (June 20th-26th, Autrans, France, 2009). MIGAS Summer School

!!!! Introduction to SOI - What is SOI?, J.P. Colinge, Tyndall, Ireland - SOI zoo, J.P. Colinge, Tyndall, Ireland SOI Material - Smart-Cut and beyond, L. Clavelier, Leti, France - Technology modules, C. Fenouillet-Béranger, STmicroelectronics & Leti, France

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!!!! SOI transistors: device physics - Mechanisms in PDSOI and FDSOI devices, O. Faynot, Leti, France

- Transport in double-gate and nanowire MOSFET, T. Hiramoto, University of Tokyo, Japan

- Quantum and tunneling SOI devices, A. Zaslavsky, Stony Brook University, USA - Advanced simulation, F. Gamiz, UGR, Spain - Advanced modelling and ultimate scaling, T. Ernst, Leti, France !!!! Electrical characterization and reliability

- Advanced techniques for material and device characterization, S. Cristoloveanu, IMEP-LAHC, France

- Radiation effect and reliability, R. Schrimpf, Vanderbilt, USA - How SOI can solve variability issues?, A. Asenov, Glasgow Univ., UK Designing SOI circuits - SOI circuit design plateform, P. Flatresse,STMicroelectronics, France - SOI memories, B. De Salvo, Leti, France - Low power RF, J.-O. Plouchart, IBM, USA - Power devices, P. Wessels, NXP, Netherlands - MEMS, NEMS, sensors, D. Elata, Technion, Israel

v. Exploring new routes with SOI (January 25th, 2010, Grenoble, France)

• Advanced SOI Technology (Dr.Jan Hoentschel, GlobalFoundries, Dresden, Germany)

• Composite single-crystal-based wafers for advanced radiofrequency acousto-electric devices (Dr.Sylvain Ballandras, FEMTO-ST, France)

• Electrical characterisation of SOI nanodevices, (Prof.Gerard Ghibaudo, IMEP-LAHC, INPG-MINATEC, Grenoble, France)

• Wafer Level 3D Integration: Overview of technologies (Dr.N.Sillon, CEA-LETI, Grenoble)

• SOI substrate for RF applications? (Dr.Eric Desbonnets, SOITEC, Bernin, France)

vi. Silicon on Insulator: Materials to Circuit Design (September 13th, 2010, Seville, Spain)

• Smart cut enabled materials (Cindy Colinge, Tyndall, Cork, Ireland) • Physics of SOI devices (Jean Pierre Colinge, Tyndall, Cork, Ireland) • SOI MOSFET compact models (Benjamin Iñiguez, URV, Tarragona, Spain) • SOI technology: An opportunity for RF designers?. (Jean Pierre Raskin, UC,

Louvain-la-Neuve, Belgium) • Analog SOI CMOS devices : figures of merit, design techniques and

applications. (Denis Flandre, UCL, Louvain-la-Neuve, Belgium ) • SOI design: logic circuits. (Philippe Flatresse, STMicroelectronics, Crolles,

France)

vii. Silicon on Insulator technologies for future electronics (January 17th, 2011, Granada, Spain)

• SOI solutions for next technological nodes. (Sigfried Mantl, FZJülich, Aachen, Germany)

• ETSOI Technology (Bruce Doris, IBM Research, Yorktown Heights, USA) • CMOS-SOI-MEMS Imagers (Yael Nemirovsky, Technion, Haifa, Israel) • SOI Low-power applications (Noboyuki Sugii, LEAP, Tokyo, Japan) • Memories on SOI (Malgorzata Jurczak, IMEC, Leuven, Belgium) • SOI Photonics (Jean Marc Fedeli, CEA-LETI, Grenoble, France)

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c. Organization of Workshops.

i. Fourth Workshop of the Thematic Network on Silicon on Insulator Technology, Devices and Circuits (Tyndall National Institute, Cork, Ireland, Jan 23-25th, 2008): http://www.tyndall.ie/eurosoi2008/ (56 accepted communications, 80 attendants)

ii. Fifth Workshop of the Thematic Network on Silicon on Insulator

Technology, Devices and Circuits (Chalmers University of Technology, Goteborg, Sweden, Jan 19-21st, 2009): http://chalmers2009.eurosoi.org (60 accepted communications, 90 attendants)

iii. Sixth Workshop of the Thematic Network on Silicon on Insulator

Technology, Devices and Circuits (MINATEC, Grenoble, France, Jan 25-27th, 2010): http://grenoble2010.eurosoi.org/ (56 accepted communications, 110 attendants)

iv. Seventh Workshop of the Thematic Network on Silicon on Insulator

Technology, Devices and Circuits (Parque de las Ciencias, Granada, Spain, Jan 17-29th, 2011): http://granada2011.eurosoi.org/ (64 accepted communications, 120 attendants)

d. Discussion Panels. The opinion of SOI experts.

i. “Key Issues in SOI: Solutions and Ideas”, chaired by Prof.Sorin Cristoloveanu, January 24th, 2008, Cork, Ireland

Participants: Dr. Damien Bretegnier, SOITEC

Prof. Denis Flandre, UCL Dr. Segei Okonin, Innovative Silicon Dr.Olivier Faynot, CEA-LETI Prof. Jean-Pierre Colinge, Tyndall

ii. “What is the killing advantage of multiple-gate SOI MOSFETs: electrostatics and scalability, transport or functionality”, chaired by Prof.Sorin Cristoloveanu, January, 20th, 2009 Goteborg, Sweden

Participants: Prof. Cor Claeys, IMEC Prof. Jerry Fossum, University of Florida Prof. Jean-Pierre Colinge, Tyndall Dr.Olivier Faynot, CEA-LETI Dr.Stephane Monfray, STMicroelectronics, Crolle Prof.Francis Balestra, IMEP, SINANO Institute

iii. “SOI Technologies: What kind of research for what kind of products?”,

chaired by Prof.Raphael Clerc, January 26th, 2010, MINATEC, Grenoble, France

Participants: Dr. Horacio Mendez, SOI Industrial Consortium, USA

Dr. Christophe Tretz, IBM, USA Dr. Frederic Bouef , STMicroelectronics, Crolles, France Dr. Jan Hoentschel, GlobalFoundries, Dresden, Germany

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Prof. Jean-Pierre Colinge, Tyndall, Cork, Ireland Prof. K.Saraswat, Stanford University, Stanford, USA

iv. “The contribution of SOI to the brilliant future of Nanoelectronics””, chaired by Prof.Francis Balestra, January 18th, 2011, Parque de las Ciencias, Granada, Spain

Participants: Dr. Malgorzata Jurczak, IMEC, Belgium

Dr. Bruce Doris, IBM, USA Dr. Olivier Faynot, LETI, Grenoble, France Prof. Massimo Fischetti, UT Dallas, USA Prof. Carl Das, EUROPRACTICE, IMEC, Belgium Dr. Nobuyuki Sugii, Leap, Japan

e. Student and travel grants.

• 13 student grants (for a total of 9390,24€ ) to attend EUROSOI workshops in Cork-2008 and Goteborg-2009 have been given to PhD students who works to our their PhD in European Universities in the field of SOI technology.

• 7 student grants (for a total of 5250,00€ ) to attend EUROSOI workshop in

Grenoble in January 2010 have been given to PhD students who works to their PhD in European Universities in the field of SOI technology.

• 15 student grants (for a total of 9851,90€ ) to attend EUROSOI workshop in

Granada in January 2011 have been given to PhD students who works to their PhD in European Universities in the field of SOI technology

During the whole life of the project a total of 35 student grants (for a total of 24492,14 €) have been given to attend EUROSOI workshops.

f. Scientific Exchanges

• 5 Exchange visits (15 weeks) of EUROSOI members to other European Research Centers for a total of 15052,54€ have been funded by EUROSOI+ in 2008.

• 8 Exchange visits (20 weeks) of EUROSOI members to other European Research Centers for a total of 17394,68 € have been funded by EUROSOI+ in 2009.

• 6 Exchange visits (17 weeks) of EUROSOI members to other European

Research Centers for a total of 17556,41 € have been funded by EUROSOI+ in 2010.

• 4 Exchange visits (7 weeks) of EUROSOI members to other European

Research Centers for a total of 9316,70€ have been funded by EUROSOI+ in 2011.

In summary, 23 exchange visits (59 weeks) of EUROSOI members to other European Research Centers have been funded for a total of 59320,33 €.

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g. Elaboration & Upgrading of Technical Focused Reports (TFRs). i. EUROSOI State of the art report:

Deliverable D4.4. (To be published online on EUROSOI Website). ii. EUROSOI roadmap.

Deliverable D4.5. (To be published online on EUROSOI Website). iii. EUROSOI who is who.

Deliverable D4.6. (To be published online on EUROSOI Website). iv. Benchmark of UTB vs. FinFET vs. DG SOI transistors. Which SOI

device is favourite and for which application? http://www.eurosoi.org/public/D4.15.focused.report.utb_finfet_def.pdf

v. Reliability, lifetime,and ageing are relevant topics from an industrial perspective. http://www.eurosoi.org/public/D4.16.focused.report.soi_reliability.pdf

vi. SOI model with parameters representative of technologies of interest http://www.eurosoi.org/public/D4.17.focused.report.soi_model.pdf

h. Sponsoring of SOI events (Deliverables D2.6 & D2.7)

1. IEEE International SOI conference (2008-2009)

2. nanoKISS 2010: Korean International Summer School on Nanoelectronics

3. International SemOI Workshop "Nanoscaled Semiconductor-on-Insulator Materials, Sensors and Devices"

4. European Solid State Device Research Conference 2010, ESSDERC-2010, Tutorial: “Silicon on Insulator: Materials to Circuit Design”

5. nanoKISS 2011: Korean International Summer School on Nanoelectronics

II. Development of EUROSOI fabrication & prototyping platform for the design of low-

power SOI circuits.

a. Coordination of information exchange on LETI FDSOI technology. FDSOI wafers with functional devices have been provided to UCL, IMEP, URV and UGR. Also, electrical measurements have been provided to UGR.

b. Coordination of activities for the documentation, promotion and spreading of Research-dedicated Design Kit (RDK). The development of the research design kit is progressing in phase with what has been planned in the European project called DECISIF. This design kit contains a digital part that includes device model, Design Rules Control file and Layout Versus Schematic file. These files are essential to model and control the layout generated by the designers. This part is completed at 100%. The design kit contains also an analog part that includes Matching parameters, RF parasitics and related model (completed at 100%). The design kit finally contains an automated digital Design flow that includes Standard cell library and SRAM memory cuts. This last part is completed at 100%. With such level of achievement, the design kit can already be used to design some elementary circuits.

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c. Promotion of the FDSOI technology.

Promotion of the FDSOI technology has been made by LETI during this period to the following companies:

- Presentation of the technology and results are regularly (every 3 months) made to SOITEC.

- Technology and electrical results have been also presented to ST Microelectronics in order to highlight the interest of such technology for Low Power applications.

- Promotion of FDSOI technology has also been done to AMD and ARM through a presentation at the SOI consortium meeting in November 2008.

- During the LETI annual review (in June 2009), a specific presentation has been made by Olivier Faynot in order to make a status of this technology at LETI and present the state of the art of the Research dedicated Design Kit.

- In the frame of the 2009 VLSI symposium, held in Kyoto, Olivier Faynot had the opportunity to participate to the evening rump session. The rump session was focussed on ‘The Key technology options for sub 20nm nodes’.

- A FDSOI workshop has been co-organized in Leuven from October 15-16th 2009, by the SOI Consortium and IMEC. This workshop was dedicated to the promotion of the FDSOI technology for the industrial companies that are more focussed on Bulk and FinFET technologies. (http://www.soiconsortium.org/resources/fully-depleted-soi-october-2009.php )

- After 2009 IEDM conference in Baltimore, a second FDSOI workshop has been co-organized (on December 9th) by the SOI Consortium and LETI. The goal was the same as the previous workshop. This meeting was a good opportunity to expose ARM company to the recent FDSOI results. (http://www.soiconsortium.org/resources/fully-depleted-soi-december-2009.php )

- In the frame of the DECISIF project, the most recent FDSOI technology developments have been presented in Dresden (Global Foundries site), in front of the project partners: ST, SOITEC, SILTRONIC, MPI Halle, Juelich. (http://www.catrene.org/web/downloads/profiles_medea/2T104-DECISIF-profile-outMEDEA%20(21-7-09).pdf )

- During the EUROSOI 2010 workshop, a working group meeting has been organized and Carlo Reita (LETI) presented the status of the FDSOI platform. Outcomes of this meeting are summarized in deliverable D5.3.

- Technology and electrical results have been also presented to ST Microelectronics and SOITEC in order to highlight the interest of such technology for Low Power applications. No travel expenses are related to this promotion.

- An article has been written in ‘Advanced Substrates News’, in the Spring 2009 edition. The title is: ‘Leti, Soitec and ST have discovered the sources of threshold voltage variation in undoped, ultrathin FD-SOI architectures.’ It can be read using the following website: http://www.advancedsubstratenews.com/index.php?newsletter=4&nomRubrique=IEDM-Highlights&rubrique=78#Leti

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- A FDSOI workshop has been held in Japan during SSDM conference

(Sept. 2010). During this workshop, Carlo Reita presented a status of the platform and announced its availability through CMP in France.

- A press release announcement has been made, in October 2010, to announce the availability of the FDSOI platform through CMP. http://www.eetimes.com/electronics-news/4208994/20-nm-MPW-run-for-SOI-scheduled http://cmp.imag.fr/aboutus/slides/Slides2011/20_CEALeti_Carlo_Reita_2011.pdf

- During the LETI annual review (in June 2011), a specific presentation has been made by Olivier Faynot in order to make a status of this technology at LETI and present the state of the art of the Research dedicated Design Kit.

- In the frame of the 2010 IEDM conference, held in San Francisco, Olivier Faynot had the opportunity to give an invited talk on the FDSOI technology. This was a good opportunity to expose the Semiconductor community to the last results obtained with this technology

- After IEDM conference in San Francisco, a FDSOI workshop has been

co-organized (on December 9th) by the SOI Consortium and LETI. The goal was the same as the previous workshop. This meeting was a good opportunity to expose ARM and ST companies to the recent FDSOI results.

- During the EUROSOI 2011 workshop, several presentations were dedicated to the promotion of the FDSOI technology: Carlos Mazuré, from SOITEC, presented a status on the readiness of the SOI wafers for such platform and Bruce Doris presented the status of the ongoing technology developed in USA, in collaboration with CEA-LETI.

- Technology and electrical results have been also presented, during

technical meetings, to ST Microelectronics and SOITEC in order to highlight the interest of such technology for Low Power applications.

- A workshop has been organized in Taiwan, during the VLSI-TSA

conference. CEA-LETI was co-organizer of this workshop.

d. Coordination of activities for the evaluation of the possible integration in the existing EUROPRACTICE structure.

1. We are now considered as one of the EUROPRACTICE projects (http://www.europractice.org/).

2. We participated in the EUROPRACTICE Workshop held in Leuven on September 4th, 2008.

3. A telephone meeting with Dr.Carl Das (IMEC) and Dr.John Mclean (RAL), Dr.Olivier Faynot (LETI), Dr.Carlo Reita (LETI) and Prof.Francisco Gamiz (UGR) was held on September 9th, 2009 to discuss the following steps to be given in order that LETI-FDSOI

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technology could be offer in the framework of EUROPRACTICE program.

4. A meeting with EUROPRACTICE was organized in Granada (Deliverable D5.6)