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Circuit Paradigm in the 21 Century
ECCTD '01
Proceedings of the 15th EuropeanConference on Circuit Theory and Design
Editors: V. Porra, M. Valtonen, I. Hartimo, M. Ilmonen, O. Simula, T. Veijola
Helsinki University of Technology, Finland
28th-31st August 2001
Vol 2 of 3
Organized under the Patronage ofthe
EUROPEAN CIRCUIT SOCIETY, ECS
Sponsored by
The Society of Electronics Engineers in Finland, EIS
Co-sponsored by
IEEE Circuits and Systems Society
IEEE Finland Section
Supported by
Helsinki University ofTechnology
The Academy of Finland
Helsinki University of Technology, Department ofElectrical and Communications EngineeringElectronic Circuit Design Laboratory, Report 33
ESPOO, 2001
UB/TIB Hannover 89
122 558 693
Ace Box: High-Performance Visual 1-361
Computer Based on the ACE4k AnalogicArray Processor ChipAkos Zarandy, Hungarian Academy of
Sciences, Hungary
Some New Analogic CNN Algorithms for I-365
PCB Quality ControlTimot Hidvegi, Peter Szolgay, Computer and
Automation Institute, Hungarian Academy of
Sciences, Hungary
An Analogic CNN Algorithm - a Switch I-369
ImplementationIstvan Beszten, Oy LM Encsson AB, Finland,Tamas Bezak, Hungarian Academy of
Sciences, Hungary, Peter Szolgay, Universityof Veszprem, Hungary
SESSION R7; SPEECH AND AUDIO PROCESSING
DEVICES AND APPLICATIONS
Session Room A
Multichannel Audio Acquisition for Medical 11-1
Supervision in an Intelligent Habitat
Eric Castelli, Dan Istrate, CLIPS/IMAG, France
A New Method to Represent Speech 11-5
Signals via Predefined Functional Bases
Umit Guz, B S Yarman, Hakan Gurkan, Isik
University, Turkey
Conversion of Sampling Rate Using New 11-9
Generation of DSP's
Tomasz Marcmiak, Adam Dabrowski, Poznan
University of Technology, Poland
Comparative Study of Speaker Verification 11-13
Techniques Based on Vector Quantization,
Sphericity Models and Dynamic Time
WarpingSofia Tsekendou, Constantine Kotropoulos,Alexandros Xafopoulos, loanms Pitas,Anstotle Univ of Thessaloniki, Greece
SESSION R8: ANALOGIC WAVE ALGORITHMS
Session Room B
Calculating Local and Global PDEs by 11-17
Analogic Diffusion and Wave AlgorithmsCsaba Rekeczky, Tamas Roska, PPCU,
Hungary
Feature Extraction from Brain Electrical 11-21
Activity in Epilepsy Using Cellular Neural
Networks
Roland Kunz, Ronald Tetzlaff, Institutfur
Angewandte Physik, JWG Universitat
Frankfurt, Germany
CNN Analogic Wave Algorithms: Template II-25
Design Methods
PierPaolo Ctvallen, Marco Gilli, Pohtecnico di
Torino, Italy
Comparing Dynamic Behaviour in 1-D II-29
CNNs and Reaction-Diffusion-Convection
Pdes: a Review
Claudio Serpico, DIE, University of Naples"Fedenco II", Italy, Gianluca Setti, DI -
University of Ferrara, Italy, Patnck Thiran, ICA-
DSC EPFL, Switzerland, Sergio Callegan,DEIS - University of Bologna, Italy
SESSION S9: MEMORY EFFECTS in RF POWER
AMPLIFIERS
Session Room C '<
Effects of Filter Ripple in Predistortion H-33
Linearizer Architectures
Weiyun Shan, Lund University, Sweden,
Lars Sundstrom, Ericsson Mobile
Communications AB, Sweden, Bo Shi, Lund
University, Sweden, Michael Faulkner, Victoria
University of Technology, Australia
Analysis of Amplitude-Dependent Memory II-37
Effects in RF Power AmplifiersJoel Vuolevi, Timo Rahkonen, Univ of Oulu,Finland
A Volterra Model for Common-Source FET 11-41
Amplifiers in Third Order Intermodulation
Distortion Simulations
Joel Vuolevi, Timo Rahkonen, Univ of Oulu,
Finland
A 29 DBM, 50% PAE, 1.9 GHz Power II-45
Amplifier Using a 20 GHz Ft Silicon BipolarTechnologyFrancesco Carrara, University of Catania,
Italy, Angelo Magliansi, Antonino Scuden,
STMicroelectronics, Italy;Giuseppe Palmisano, University of Catania,
IX
SESSION S10: LOW-POWERCMOS SENSORS AND
ELECTRONICS FOR DIGITAL SINGLE-CHIP
CAMERAS
Session Room D
High Dynamic Range CMOS Image Sensors II-49
Featuring Multiple Integration and Auto-
Calibration
Markus Schwarz, Amdt Bussmann,
Thorsten Heimann, Bedrich Hosticka,JOrgen Huppertz, OlafSchrey, FhG-IMS
Duisburg, Germany
Bulk vs SOI CMOS APS Optimal Design for II-53
Low Power Low Voltage ApplicationsAryan Afzalian, Pierre Delatte,Jean-Didier Legat, Denis Flandre, Ucl-dice,
Belgium
A New Cmos Imager Using the Pseudo- II-57
Active-Pixel-Sensor(PAPS) Circuit for High
Resolution Applications
Chung-Yu Wu, Yu-Chuan Shih, National
Chiao Tung University, Taiwan
A Test Chip for a Novel High-Dynamic- 11-61
Range CMOS Image Sensor
David Stoppa, Andrea Simoni,Lorenzo Gonzo, Massimo Gottardi,
Gian-Franco Dalla Betta, Gemma Hornero,
ITC-IRST, Microsystems Division, Italy
SESSION R9: SIMULATION ANDMODELING II
Session Room E
The Implementation and Development of A II-65
Time-Domain Model of DispersiveTransmission Line
Anu Lehtovuori, Martti Valtonen,
Jarmo Virtanen, Helsinki University of
Technology, Circuit theory lab., Finland
Computationally-Efficient Behavioral II-69
Modeling of Pulsed Injection-LockedAmplifiersEnrico Calandra, Palermo University, Italy
A New Approach to Adaptive Modeling of II-73
the Electromagnetic Near and Far Field
Jan Wilk, University of the Federal Armed
Forces Hamburg, Germany; Horst R&hm,
Philips GmbH Hamburg, Germany
Effective Parameters for Complex II-77
Multilayers in Electromagnetic AnalysisAn Sihvola, Swiss Federal Institute of
Technology, EPFL, Switzerland;
Stefano Vaccaro, Jean-Francois Zurcher,Juan Mosig, EPFL, Switzerland
SESSION R10: LOW-VOLTAGE ANALOGINTEGRATED CIRCUITS
Session Room Y228
A Robust and Universal Constant-GM 11-81
Circuit Technique for Low-Voltage Rail-To-
Rail AmplifiersJ. M. Carrillo, J. L. Ausin, J. F. Duque-Carrillo,University of Extremadura, Spain;E. Sanchez-Sinencio, Texas A&M University,USA
Cmos Real-Time Analog Computational II-85
Circuits for Very LowVoltage ApplicationsAntonio J. Lopez-Martin, Alfonso Carlosena,Dept. of Electrical and Electronic Eng., Public
University of Navarra, Spain
A Versatile 1.5V Current-Mode Cmos II-89
Analog Multiplier/Divider Circuit
Antonio J. Lopez-Martin, Alfonso Carlosena,Dept. of Electrical and Electronic Eng., Public
Univ. of Navarra, Spain
1-V CMOS Class AB Current Mirror II-93
Salvatore Pennisi, Univ. Catania, Italy
SESSION R11: ANALYSIS AND MODELING OF
CHAOTIC CIRCUITS
Session Room 307
Bifurcations and Continuation in a Smooth II-97
Model of a Buck Converter
Gerard Olivar, Enric Fossas, UPC, Spain
Two-Dimensional Basic Bifurcation 11-101
Analysis of a Chaotic Oscillator Based on
HysteresisFederico Bizzarri, Marco Storace, D.I.B.E. -
University of Genoa, Italy
Markov Chain Modeling of Chaotic 11-105
Wandering in Simple Coupled Chaotic
Circuits
Yoshifumi Nishio, Martin Hasler, Swiss
Federal Institute of Technology, Switzerland;
Akio Ushida, Tokushima University, Japan
Frequency Studies of Bandpass Sigma- 11-109
Delta Modulation
Daniele Fournier-Prunaret,
Veronique Guglielmi, SYD-LESIA-DGEI-INSA,
France; Orla Feely, UCD, Ireland
X
SESSION PS3: ANALYSIS AND DESIGN TOOLS,MODELING AND SIMULATION
Multilevel Newton-Raphson Method for 11-113
Parallel Circuit Simulation
Mikko Honkala, Janne Roos, Martti Valtonen,Helsinki University of Technology, Finland
Performance Estimation in Analog 11-117
Computer Aided DesignFaik Baskaya, Gunhan Dundar, BogaziciUniversity, Turkey
A Complete Retargeting Methodology for 11-121
Mixed-Signal IC DesignsRafael Castro-Lopez, Francisco Fernandez,Manuel Delgado-Restituto,Angel Rodriguez-Vazquez, IMSE-CNM-CSIC,Spain
VHDL-AMS Model of Sense Amplifier for 11-125
Flash Memories
Ivan Boccuni, ST-Microelectronics, MPG
Group, Italy; Rosario Gulino,Gaetano Palumbo, DEES - University of
Catania, Italy
High-Level Circuit and System Simulation 11-129
With Java
Ulrich Kaiser, Texas Instruments, Germany
Simulation of Multiconductor Transmission 11-133
Lines Using Two-Dimensional LaplaceTransformation
Lubomir Braneik, Brno University of
Technology, Czech Republic
Digital Filter Design Through Simulated 11-137
Evolution
Massimiliano Erba, Roberto Rossi, Universityof Pavia, Italy; Valentino Liberali,Andrea Tettamanzi, University of Milan, Italy
Digital Standard Cell Library Migration 11-141
Using a Genetic ApproachKenneth Francken, Georges Gielen, K.U.
Leuven, Belgium
Efficient Spice-Netlist Representation of 11-145
Reduced-Order Interconnect Model
Yuya Matsumoto, Sophia University, Japan;Yuichi Tanji, Kagawa University, Japan;Mamoru Tanaka, Sophia University, Japan
Interconnect Model for Simulation of a 11-149
Low-Voltage Integrated Power AmplifierJohan Sjdstrom, Ericsson Microelectronics AB,
Sweden; Chnstian Nystrom, Wireless
Solutions Sweden; Ted Johanson, Ericsson
Microelectronics AB, Sweden; TorkelArnborg,
Ericsson Microelectronics AB, Sweden
Faster Incremental VLSI Placement 11-153
OptimizationChieh Lin, Eindhoven University of
Technology, The Netherlands;Domine Leenaerts, Philips Research Labs,The Netherlands; Arthur van Roermund,
Eindhoven University of Technology, TheNetherlands
The Vector Network Approach to 11-157
Inconsistent Initial Conditions in Linear
and Nonlinear Switch-Mode Circuits
Jan Ogrodzki, Warsaw University of
Technology, Poland
A Rigorous Approach to Electro-Thermal 11-161
Network ModelingLorenzo Codecasa, Dario D'Amore,
Paolo Maffezzoni, Politecnico di Milano - DEI,Italy
SESSION S11: NONLINEAR CIRCUITS IN
COMMUNIVATION SYSTEMS (NCCS)Session Room A
Exploiting Chaos in Multibit Sigma Delta 11-165
Modulation
Joshua Reiss, Mark Sandler, King's CollegeLondon, UK
Mode-Locking and Strange Nonchaotic 11-169
Attractors in a Digital Phase-Locked LoopWith FM InputAnna Vasylenko, Institute of Mathematics,
Ukraine; Orta Feely, University College Dublin,Ireland; Yuri Maistrenko, Institute of
Mathematics, Ukraine
Simplification of Nonlinear DAE Systems 11-173
with Index TrackingTim Wichmann, Fraunhofer Institute for
Industrial Mathematics, Germany
About the Spectral Properties of Non- 11-177
Linear Zero-Position Coding AlgorithmFrank Felgenhauer, Martin Streitenberger,
Wolfgang Mathis, University of Hannover,
Germany
SESSION S12: APPLICATIONS OF CHAOS I \"
Room B «,. A
J'
,
' "' '
Chaos Based DS-CDMA Systems: Steps 11-181
from Theory to ExperimentsGianluca Mazzini, CEGDI - Universty of
Ferrara, Italy; Riccardo Rovatti, CEGDEIS -
University of Bologna, Italy; Gianluca Setti,
CEGDI - University of Ferrara, Italy
XI
Comparison of Different Chaos Shift 11-185
Keying MethodsThomas Schimming, Martin Hasler, EPFL,
Switzerland
On the Spectrum of Signals Obtained by 11-189
Driving FM Modulators with Chaotic
SequencesSergio Callegari, Riccardo Rovatti, DEIS,
University of Bologna, Italy; Gianluca Setti, Dl,University of Ferrara, Italy
Non-Redundant Error Correction in FM- 11-193
DCSK Chaotic Communications SystemsZoltan Jako, Budapest University of
Technology and Economics, Hungary;Daniele Fournier-Prunaret,
Veronique Guglielmi, L.E.SJA, I.N.S.A.,
France; GaborKis, Budapest University of
Technology and Economics, Hungary
SESSION S13: ADVANCED NUMERICAL
TECHNIQUES FOR TRANSIENT AND STEADY-
STATE ANALYSIS OF NONLINEAR CIRCUITS
Session Room C
Analysis of Digitally Modulated Steady 11-197
States in Nonlinear Circuits by Krylov-Subspace Harmonic Balance
Vittorio Rizzoli, Alessandra Costanzo, DEIS,
University of Bologna, Italy; Franco Mastri,
DIE, University of Bologna, Italy
Advanced Analysis and Design Methods 11-201
for RF and Millimeter Wave Mems
Katia Grenier, LAAS CNRS, France;Laurent Rabbia, Patn'ck Pons, A Takacs,T Parra, J Graffeuil, H Aubert, LAAS, France;
Robert Plana, LAAS CNRS, France
Generalized Circuit Formulation for the II-205
Transient Simulation of Circuits Using
Wavelet, Convolution and Time-MarchingTechniquesMichael Steer, Carlos Christoffersen, North
Carolina State University, USA
Combined State-Space and Convolution II-209
Techniques for Transient and Steady-StateSimulation of RF/Microwave Circuits
Thomas Brazil, University College Dublin,
Ireland
SESSION S14: OPTIMIZATION OF DIGITAL FILTERS
Session Room D
Express Coefficients in 13-ary radix-4 CSD 11-213
to Create Computationally Efficient
Multiplierless FIR Filters
Jeffrey Coleman, Naval Research Laboratory,USA
An MILP Approach for the Design of 11-217
Linear-Phase FIR Filters with Minimum
Number of Signed-Power-Of-Two Terms
Oscar Gustafsson, Hakan Johansson,
Lars Wanharrimar, Linkoping University,Sweden
New Cost Evaluation Schemes in Graph- 11-221
Based Memory Allocation Method for
Indirect Addressing DSPs
Nobuhiko Sugmo, Tomoyuki Matsuura,
Akinori Nishihara, Tokyo Institute of
Technology, Japan
An Algorithm for the Optimization of II-225
Pipelined Recursive Digital Filters
Juha Yli-Kaakinen, Tapio Saramaki, SignalProcessing Lab., Tampere University of
Technology, Finland
SESSION R12: ANALYSIS AND DESIGN TOOLS I
Session Room E
A Combined Structural and Symbolic II-229
Method for Automatic Behavioral Modelingof Nonlinear Analog Circuits
Markus Olbrich, RalfPopp, Lutz Nathke,
Lars Hedrich, Erich Barke, University of
Hanover, Institute of Microelectronic Circuits
and Systems, Germany
Optimal Zero Locations of Continuous- li-233
Time Systems Tracking Reference StepResponsesAnna Soffia Hauksdottir, University of Iceland,
Iceland
Efficient Methods for Reducing Register li-237
And Phase Requirements for SynchronousCircuits Derived Using Software PipeliningTechniquesNoureddine Chabini,El Mostapha Aboulhamid, Universite de
Montreal, Canada; Yvon Savaria, Ecole
Polytechnique de Montreal, Canada
I.M.A.G.E A New Cad Tool for Device 11-241
Modeling in SpiceMarco Zorzi, Francesco Franze, Nicold
Speciale, DEIS, University of Bologna, Italy
SESSION R13: DIGITAL SYSTEMS
Session Room Y228
Optimized Design of Carry-Bypass Adders II-245
Massimo Alioto, Gaetano Palumbo, DEES -
University of Catania, Italy
A 200-MHz RNS Core II-249
Haridimos Vergos, Computer Engineering &
Informatics Dept., Greece
Minimizing Sensitivity to Clock Skew II-253
Variations Using Level Sensitive Latches
Frangois-Raymond Boyer,El Mostapha Aboulhamid, DIRO, Universite de
Montreal, Canada; Yvon Savaria, DGEGI,Ecole Polytechnique de Montreal, Canada
xn
Color Filter Array and Color Correction for 11-257
High Dynamic Range CMOS Image Sensors
Thorsten Heimann, Markus Schwarz,Bedrich Hosticka, Fraunhofer Institute of
Microelectronic Circuits and Systems,Germany
SESSION R14: CNN CIRCUIT DESIGN
Session Room Y307
Robust Multilayer DTCNN Design for B/W 11-261
and Grayscale Input ApplicationsPaula Lopez, David L Vilarino, VictorM. Brea,Diego Cabello, Departamento de Electronica e
Computacion, Universidade de Santiago de
Compostela, Spain
2d Two-Channel MR PRQMF Bank Design II-265
Using CNNEmir Tufan Akman, Koray Kayabol, Universityof Istanbul, Turkey
A DTCNN CMOS Implementation of a Pixel- li-269
Level Snake AlgorithmVictor M. Brea, University of Santiago de
Compostela, Spain; Ah Paasio, Helsinki
University of Technology, ECDL, Finland;David L Vilarino, Diego Cabello, University of
Santiago de Compostela, Spain
CNNS, Intelligence and Synchronization II-273
TheoryJohan Suykens, Joos Vandewalle, K.U.
Leuven, ESAT-SISTA, Belgium
SESSION,S15: SYSTEM£>N A pHiP 1v , ,u
Session Room Y227 „,*$.,*£ i ? ,'}%lt <. ** .>t
. > l-»
*i x„
" \i> >. .,i i
Early Estimation of Interconnect Effects on 11-277
the Operation of System-On-Chip Platforms
Tero Nurmi, University of Turku, Finland,Li-Rong Zheng, Royal Institute of Technology,Sweden; Jouni Isoaho, University of Turku,
Finland, Hannu Tenhunen, Royal Institute of
Technology, Sweden
Interconnect IP for Gigascaie System-On- 11-281
Chipllkka Saastamoinen, TUT, Finland;Teemu Suutari, Jouni Isoaho, UTU, Finland;Jari Nurmi, TUT, Finland
Reed-Muller Transform Based Boolean li-285
Matching Filters
Chip-Hong Chang, Bogdan Falkowski, School
of Electrical & Electronic Engineering,Singapore
Generic Interface Block for System-on-a- II-289
Chip DesignsVesa Lahtinen, Kimmo Kuusilinna, Tampere
University of Technology, Digital and
Computer Systems Laboratory, Finland;
Timo HSmSISinen, Jukka Saarinen, Tampere
University of Technology, Digital and Comp,
Finland
SESSION PS4: ANALOGUE AND DIGITAL SIGNAL
PROCESSING. FAULT DETECTION
Reconstruction of Nonuniformly Sampled II-293
Bandlimited Signals Using DigitalFractional Delay Filters: Error and
Quantization Noise AnalysisHakan Johansson, PerLowenborg, Linkoping
University, Sweden
On Adjustable Fractional Delay FIR Filters II-297
and Their DesignHakan Johansson, PerLdwenborg, LinkopingUniversity, Sweden
VLSI Parallel Architecture for Low Density 11-301
Parity Check Decoder
Wai Leng Lee, Angus Wu, Ping Li,
Department of Electronic Engineering, CityUniversity of Hong Kong, Hong Kong
Signal-Flow-Graph Identities for Structural II-305
Transformations in Multirate SystemsAlexandra Groth, Heinz Gockler, Ruhr-
Universitaet Bochum, Germany
Prototype Filter Design Techniques for II-309
Cosine-Modulated TransmultiplexersPilar Martin-Martin, Fernando Cruz-Roldan,Pedro Amo-L6pez, Francisco Lopez-Ferreras,University of Alcala, Spain
A Study of Distributed Algorithm for 11-313
Network Optimization Problem Based on
Tie-Set Graph TheoryTakeshi Ishibashi, Toshio Koide,Hitoshi Watanabe, Soka University, Japan
A Novel Technique for the Estimation of 11-317
Stability in Feedforward and Multiple-Feedback Oversampled Sigma-Delta A/DConverter ConfigurationsNeil Fraser, Behrouz Nowrouzian, Universityof Alberta, Canada
Optimization of Chirp-Z and Truncated 11-321
Shannon's InterpolationDjordje Babic, Markku Renfors, TampereUniversity of Technology, Telecommunications
Lab., Finland
Fractional Signal Processing: Scale II-325
Conversion
Manuel Ortigueira, UNINOVA, Portugal;Carlos Matos, Escola Superior de Tecnologia,Portugal; Mois4s Piedade, INESC, Portugal
Rns-Fpl Merged Polyphase DWT 11-329
Architectures
Javier Ramirez, University of Granada, Spain;Antonio Garcia, Universidad Autonoma de
Madrid, Spain; Pedro Garcia Fernandez,
University of Jaen, Spain; Luis Parrilla,
Antonio Lloris, University of Granada, Spain
An Efficient Semi-Systolic Architecture for 11-333
2-D Discrete Wavelet Transform
Kresimir Mihic, University of Zagreb, Croatia
Calculation of Dyadic Autocorrelation 11-337
Through Decision DiagramsRadomir S. Stankovic, Dept. of ComputerSceince, Faculty of Electronics, University of
Nis, Yugoslavia; Mrinmoy Bhattacharaya,Jaakko Astola, TICSP, Tampere University of
Technology, Finlad
Accelerated Analogue Fault Simulation by 11-341
Concurrent Fault Detection
Mustapha Dhifi, Institut of ElectromagneticTheory, Germany
New Reliability Indices for Multi-State li-345
SystemElena Zaitseva, Vitaly Levashenko, Belarus
State Economic Univ., Belarus
The Use of Correlation Technique II-349
Combined with EA-Modulation for
Detection of Defective Sensor Elements
Dirk Weiler, Dirk Hammerschmidt,Niels Chritoffers, Bedrich J. Hosticka,Fraunhofer IMS Duisburg, Germany
SESSION S16: ANALOG AND RF INTEGRATED
CIRCUITS DESIGN
Session Room A,
Integrated RF Front-End for WCDMA and 111-1
GSM 900
Jussi Ryynanen, Kalle Kivekas, Helsinki
University of Technology, ECDL, Finland;Jari Heikkinen, Nokia Networks, Finland;Jarkko Jussila, Helsinki University of
Technology, ECDL, Finland;Aarno P&rssinen, Nokia Research Center,Finland; Kari Halonen, Helsinki University of
Technology, ECDL, Finland
The Design of CMOS Cellular Transceiver III-5
Front-Ends
Michiel Steyaert, Bram de Muer,Johan Janssens, Marc Borremans,P. Leroux, ESAT- MICAS K.U. Leuven,Belgium
An Integrated 110 MHz Bandpass Filter in ill-9
Bipolar TechnologyFrancesco Belfiore, STMicroelectronics, Italy;Giuseppe Palmisano, University of Catania,
Italy
A CMOS 1.57 GHz Quadrature-VCO for a 111-13
GPS Receiver Front-End
Wouter De Cock, Michiel Steyaert,Katholieke Universiteit Leuven, Dept. ESAT-
MICAS, Belgium
SESSION S17: APPLICATIONS OF CHAOS II
Session Room B -
FM-DCSK Chaos Radio System 111-17
Karol Krol, Leonardo Azzinnari, Esa Korpela,Andras Mozsary, Mikko Talonen,Veikko Porra, Helsinki University of
Technology, ECDL, Finland
Mixed-Signal Map-Configurable IC Chaos 111-21
Generator for Digital Communication
SystemsManuel Delgado-Restituto,Angel Rodriguez-Vazquez, Instituto de
Microelectronics de Sevilla, Spain
A Simple Digital FPGA Pseudo-Chaos III-25
Generator
Leonardo Azzinnari, Andras Mozsary,Karol Krol, Esa Korpela, Veikko Porra,Helsinki University of Technology/ECDL,Finland
SESSION S18: RECENTTRENDS IN
INTERCONNECTS MODELING AND SIMULATIONSession Room C
Asymptotic Equivalent Circuits of III-29
Interconnects Based on ComplexFrequency Method
Akio Ushida, Tokushima University, Japan;Kouji Urabe, Niihama National Technical
College, Japan; Yoshihiro Yamagami,Yoshifumi Nishio, Tokushima University,Japan
Pspice Subcircuits for Passive Reduced ill-33
Order Interconnect Models
Murat Ding, Istanbul Technical University,Turkey; Izzet Cem Goknar, Dogus University,Turkey
Passive Time-Domain Model Order III-37
Reduction via Orthonormal Basis
Functions
Qingjian Yu, Ernest S. Kuh, University of
California at Berkeley, USA
Passive Macromodels for Distributed 111-41
High Speed Interconnects
Anestis Dounavis, Ramachandra Achar,Michel Nakhla, Carleton University, Canada
XIV