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Europaisches Patentamt

European Patent Office

Office europeen des brevets

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(ji) Publication number:

EUROPEAN PATENT S P E C I F I C A T I O N

:. a*: G01 R 31/28, G01 R 31 / 2 6 Int. Date of publication of the patent specification: 14.03.90

Application number: 86110460.2

Date of filing: 29.07.86

Full chip integrated circuit tester.

Proprietor: International Business Machines Corporation, Old Orchard Road, Armonk, N.Y. 10504(US) Priority: 23.09.85 US 778823

Date of publication of application: 01.04.87 Bulletin 87/14 Inventor: Beha, Johannes George, Santisstrasse 75,

CH-8820 Wadenswil(CH) Inventor: Kash, Jeffrey Alan, 122 Pleasant Avenue, Pleasantville New York 10570(US) Inventor: Dreyfus, Russell Warren, 70 Barker Street, Mt Klsco New York 10549(US) Inventor: Rubloff, Gary Wayne, 16 Nightingale Road, Katonah New York 10536(US)

Publication of the grant of the patent: 14.03.90 Bulletin 90/11

Designated Contracting States: DEFRGBIT

Representative: Johansson, Lars E. et al, IBM Svenska AB Intellectual Property Department 4-01, S-163 92 Stockholm(SE)

References cited: (continuation) pages 163-166, IEEE, New York, US; M. MACARI et al.: "Automated contactless SEM testing for VLSI development and failure analysis"

References cited: IBM TECHNICAL DISCLOSURE BULLETIN, vol. 25, no. 3A, August 1982, pages 1171-1172, New York, US; G.W. RUBLOFF: "Contactless measurement of voltage levels using photoemission" INTERNATIONAL TEST CONFERENCE, 1984 PROCEEDINGS, 16th-18th October 1984, pages 536-542, IEEE, New York, US; F.J. HENLEY: "An automated laser prober to determine VLSI internal node logic states" REVIEW OF SCIENTIFIC INSTRUMENTS, vol. 44, no. 11, November 1973, pages 1628-1629, American Institute of Physics, New York, US; WJ. BAXTER et al.: "A photoemission electron microscope using an electron multiplier array" 20TH ANNUAL PROCEEDINGS RELIABILITY PHYSICS, 30th-31st March, April, 1982, San Diego, CA,

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Note- Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid (Art. 99(1) European patent convention). ^ ^

ACTORUM AG

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Description

The present invention relates to noncontact dynamic operational monitoring testing of integrated cir- cuits, and more particularly to a full chip testing procedure by which instantaneous operational voltages

5 at a number of nodes on an integrated circuit are measured by pulsed laser induced photoemission at specific times during the chip clock cycle.

Known techniques for testing internal tiodes of integrated circuits, whether carried out by mechanical contact probing or contactless techniques, suffer from the inherently slow speed of any point-by-point measurement. In addition, most of these do not give as reliable a picture of the circuit operation as would

10 a real-time measurement. US-A 4 706 01 8 published on 1 0/1 1 /87, shows a tester which allows testing in vacuum of the dynamic op-

eration and performance of high-speed very large scale integration (VLSI) circuits, including on-chip contactless measurement of AC switching waveforms (picosecond time scales) as well as logic state evaluation (nanosecond time scales) using high energy photons (about 5-6 eV). This technique is based

15 on the phenomenon of photon-induced electron emission (photoelectron emission) from a solid surface into vacuum. In this technique, the voltage of a single circuit node is measured as a function of time dur- ing the chip clock cycle.

US-A 4 644 264 published 17/2/87 and US-A 4 786 864 published 22/1 1/88, show a tester which allows testing in air of the dynamic operation and performance of high-speed very large scale integration

20 (VLSI) circuits. This technique employs a transparent insulating passivation layer, often present over the circuit's internal nodes, together with a metal overlayer on top of the insulating layer in order to de- tect the monitoring signal, based on the phenomenon of photon-assisted tunneling from a metal into an ox- ide. The voltage of a single circuit node is measured as a function of time during the chip clock cycle.

US-A 4 670 710 published on 2/6/87, shows a tester which allows testing in vacuum of the dynamic op- 25 eration and performance of high-speed very large scale integration (VLSI) circuits. By producing a line

focus with the incident laser light and employing high-speed electron deflection optics for the photoemit- ted electrons (as exploited in a streak camera), this technique achieves simultaneous measurement of the voltage of a one-dimensional array of internal nodes on a circuit.

These real-time measurements of internal node voltages on a chip fall short of the high testing speed 30 attainable by simultaneous measurement of a two-dimensional array of circuit nodes, which is the object

of the present invention. U.S. Patent 1,957,249, Dantscher, ELECTRON DISCHARGE APPARATUS, May 1, 1934, merely

shows electron discharge from electron beam excitation. Electron beam testing methods are known as means for contactless measurement of internal circuit nodes. However, they carry several important

35 limitations. First, they require surface availability of metal conductor test points and are therefore inad- equate for testing of passivated circuits. Second, the electron beam causes damage to passivating lay- er materials such as oxides and must therefore be carefully directed away from such areas. Third, and most crucial, they do not permit simultaneous measurement of an array of circuit nodes.

In our copending patent applications listed above, we described techniques for testing of the dynamic 40 operation and performance of high-speed VLSI circuits. Besides the measurement of AC switching

waveforms (picosecond time scales) as part of the verification of hardware design, it is also important and helpful to be able to check that the logic operation of the chip is functionally correct. The ability to test the logic states and AC switching waveforms at internal nodes on the chip becomes increasingly im- portant with high chip complexity and wafer scale integration. This can be accomplished with the laser

45 test methods of US-A 4 706 018, US-A 4 644 264, US-A 4 786 864 and US-A 4 670 710 with scanning, or with available metal test points at the chip surface, with electron beam methods or by scanning the probe over the chip. Such scanning is time-consuming, making on-line product testing inconvenient, and does not provide a simultaneous test of the circuits on the chip.

The prior art does not teach nor suggest the invention, which permits dynamic real-time testing of a 50 large two-dimensional array of internal circuit node voltages, i.e. "full-chip" testing of logic states and

AC switching waveforms, to provide rapid and accurate evaluation of circuit operation. The main object of the present invention as defined in independent claims 1 and 6 is to provide sensi-

tive real-time contactless testing of integrated circuits. Specific embodiments permit such testing in air environment as well as in vacuum environment, and also allow testing with or without insulating passiva-

55 tion layers present above the circuit nodes to be tested. Another object of the invention is to extend such testing of integrated circuits to carry out "full-chip"

real-time testing of AC switching waveforms and logic states, i.e. simultaneous testing of a two-dimen- sional array of internal circuit nodes.

A specific object of the invention is to permit such testing with oxide, insulator, or passivation layers 60 present on top of the metal test points, thus bringing the test environment into operational similarity with

eventual use environment. Another specific object of the invention is to permit such testing in air environment, as well as in vacu-

um. A feature of the invention is the biasing of the chip-to-test to provide increased discrimination by pro-

65 viding a threshold for laser-induced photoemission.

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Another feature of the invention is the use of parallel optical processing of the two-dimensional array of information representing the voltage states of test points on the chip. The retained image is then eval- uated by computer to provide the necessary test results in computer-usable form.

A specific feature of two embodiments of the invention is the use of electron optics systems with mi- 5 crochannel plates and phosphor screen, to image a two-dimensional electron beam pattern and convert it

into a corresponding two-dimensional optical pattern. Another specific feature -of -an embodiment of the invention is the use of fluorescent material in the

passivating insulator layer on the chip to convert the two-dimensional electron signal pattern into a cor- responding optical signal pattern.

10 Another specific feature of two embodiments of the invention is the use of a thin metal overlayer on top of a transparent passivating insulating layer on the chip, such that electrons in the test signal can pass through this thin metal overlayer into vacuum for imaging and measurement.

Another feature of an embodiment of the invention is a chip with available test points passivated, equipped with luminescent screen and positioned in windows for easy testing.

15 An advantage of the invention is that the entire chip may be read simultaneously, during a single pulse of the chip clock, to provide an instantaneous readout of voltage state of all the test points from which test data might be required.

Another advantage of the invention is that though all test readings are taken at the high speeds nec- essary for laser induced photoemission and for reading the voltage state of a high performance inte-

20 grated circuit, readings are retained for evaluation by the computer. Multiple laser scans may thus be carried out in a very short time, followed by a relatively leisurely review of the test results to determine necessary action, such as reject, rework, accept.

Another advantage of the invention is that it achieves high time resolution (5 picosecond or less) and lateral resolution (1 micron or less) and high voltage resolution (of order 1mV in reasonable measurement

25 times). The manufacturing advantage of truly full-chip nondestructive testing, with passivation layers

present, which allows testing in the same tool used to carry out personalization, significantly extends the economic advantages of in-process testing by providing freer choice of test time and easier test setup.

The foregoing and other objects, features and advantages of the invention will be apparent from the 30 more particular description of the preferred embodiments of the invention, as illustrated in the accompa-

nying drawings, where

FIG. 1 is a schematic diagram of the invention, FIG. 2 is a schematic diagram of a first specific embodiment of the invention, directed at testing in

35 vacuum without passivation layers present,. FIG. 3 is a schematic diagram of a second specific embodiment of the invention, directed at testing in

vacuum with passivation layers present, FIG. 4 is a schematic diagram of a third specific embodiment of the invention, directed at testing in air

with passivation layers present. 40

FIG. 1 is a schematic diagram of the invention, showing the impinging pulsed laser beam, the chip under test, and the two-dimensional optical array processor according to the inventive technique.

This technique is a method and apparatus to measure logic states and AC switching waveforms simul- taneously in a two-dimensional array across an entire chip, thereby reducing testing time drastically. All

45 voltage levels on the chip are determined at the same time and during the same cycle of the chip clock. This ability to do full-chip testing represents a considerable advance.

The common and salient elements of the full-chip testing method are depicted schematically in FIG. 1. The chip under test 1 is mounted on a substrate or holder 2 so that its various internal nodes or test points 3 are accessible for testing. For high levels of chip integration (typically 10,000 - 100,000 transis-

50 tors or circuits per chip) many internal nodes are present which may be the subject of the testing. The op- eration of the circuitry on the chip is accomplished by driver circuitry in control unit 4, so that the chip runs during the test at full speed as designed.

At a particular instant of time a very fast laser pulse is delivered from the laser system 5 with suffi- cient photon energy to induce photoelectron emission from the test points 3 on the chip. The laser light is

55 expanded by optical system 6 to illuminate the entire chip, causing photoemission signals from all points which are indicative of the voltages to be determined at that instant of time. Laser system 5 and optical system 6 may be characterized as "activation means." The amount of the photoelectron signal emanating from each test point on the chip is indicative of its voltage during the laser pulse.

The photoelectron patterns are modified and processed by a luminescent target 7, optical processing 60 system 8 and voltage discrimination means 9 to represent test point voltages. These patterns then carry

the two-dimensional voltage information, which is translated into a corresponding two-dimensional optical emission pattern from a luminescent (phosphorescent or fluorescent screen) target 7. The pattern is then measured by a parallel optical processing system 8, such as is employed in a vidicon system. Al- though the response time of the phosphor and video system is not particularly fast, the information cor-

65 responds only to the voltage pattern which was present at test points on the chip during the fast laser

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pulse. With laser pulse widths of 5 picosends or less, time resolution of the full-chip testing system re- mains extremely fast, consistent with both AC waveform and real-time logic state testing of high perform- ance integrated circuits.

The mechanism by which the photoelectron pattern emanating from the chip is translated into a two-di- 5 mensional optical emission pattern from luminescent target 7 can vary considerably, accommodating ap-

plications in air or in vacuum, and also with or without passivation layers present on top of the chip test points 3. Three specific embodiments are discussed below.

FIG. 2 is a schematic diagram of a first specific embodiment of the invention, directed at testing in vacuum without passivation layers present. An ultraviolet laser beam from laser 5 via optics 6, pulsed

10 synchronously with the chip clock from control unit 4, impinges over the entire chip 1. With laser photon energies L above the work function W of the metal test points 3 on the chip 1, photoelectrons are gener- ated (primary and secondary). These photoelectrons are then imaged onto one or more microchannel plates by an electron lens 1 0. An accelerating grid 1 1 in front of the chip 1 may also be employed to reduce the effects of stray microfields on the chip 1 and to provide voltage discrimination in the signal pattern.

15 The microchannel plates 12 are a high density array of electron multiplier plates which produce high gain in the electron intensity (up to 1.000.000X). These larger electron currents are then accelerated to a lu- minescent (phosphor) target 7 in optical processing system 8, producing a luminescent representation of test voltages on the chip 1 . The image brightness at a given test point is a direct function of the voltage at that test point 3 on the chip 1. This luminescent image is then processed by the optical processing sys-

20 tern 8, which may be a vidicon or other video device. The image can be retained in the luminescent (phosphor screen) target 7 for much longer times than the laser pulse width.

Since this scheme measures all points on the chip simultaneously, high power laser pulses are re- quired to achieve sufficient signal. This can be attained with commercially available pulsed ultraviolet ex- cimer lasers. Such lasers now have pulse widths in the range 3-20 ns, which is sufficient to resolve

25 voltage levels within a chip clock cycle. A Lumonics TE-861T-4 excimer laser is an example. The charac- teristics of such a laser are given in Table I for three of the available gases. Using photoyields as esti- mated in Table 1 , assuming the laser beam to be imaged onto a 1 0 mm. x 1 0 mm. chip, and reducing the peak power density to an acceptable level (10 mJ/cm2), we find that each 1 micron x 1 micron test point could give 35,000 - 370,000 electrons per laser pulse. This is more than sufficient to make a reasonable volt-

30 age measurement for all points on the chip in one laser pulse. Consider the case of KrCI (the worst of the three in Table I) as an example. Assuming the same energy distribution of photoelectrons (1 eV width), a 10 mV change in voltage could be measured with a signal/noise ratio of 2 in a single laser pulse for all 1 mi- cron points on the chip.

Table I. Characteristics of some pulsed uv excimer lasers (i.e, Lumonics TE-861T-4) and expected 35 testing photocurrents from Au metal pad/interconnect test points.

Photoyield: calculated from yield above threshold from Au data of W. F. Krolikowski and W. E. Spicer, Phys. Rev. B 1,478 (1970)

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F2 K r C l A r F L a s e r G a s

W a v e l e n g t h (ran) 193. 157. 2 2 2 .

P h o t o n e n e r g y (eV) 6 .42 7 .90 5 . 5 9

Min p u l s e w i d t h (ns) 10. 6. 6 .

Max p u l s e e n e r g y (mJ) 140. 12. 2 5 .

Max p u l s e r a t e ( p i c o s e c o n d s ) 200. 200. 2 0 0 .

Pho ton -Flux d u r i n a 1 .3E+25 1 .5E+24 4 . 0 E + 2 4

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15 p u l s e ( p h o t o n s / s e c )

E s t i m a t e d p h o t o y i e l d a t l a s e r 6 . 0 E - 0 4 w a v e l e n g t h ( e l e c t r o n s / a b s o r b e d p h o t o n )

3 . 0 E - 0 3 2 . 0 E - 0 4

20 8 .0E+21 4 .5E+21 8 . 8 E + 2 0 E l e c t r o n f l u x d u r i n g p u l s e

( e l e c t r o n s / sec )

No. e l e c t r o n s pe r p u l s e 4 .5E+13 8 . 8 E + 1 2

4 .5E+05 8 . 8 E + 0 4

3 .7E+05 3 . 5 E + 0 4

8 . 0 E + 1 3 25

No. e l e c t r o n s / p u l s e a t e a c h t e s t pt 8 . 0 E + 0 5 ( a s s u m i n g 1 sq. m i c r o n e a ,

10 mm. x 10 mm. c h i p a n d l a s e r beam s i z e )

No. e l e c t r o n s / p u l s e a t each t e s t p t 5 . 7 E + 0 4 f o r peak power d e n s i t y r e d u c e d t o 10 m J / c m 2 .

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FIG. 3 is a schematic diagram of a second specific embodiment of the invention, directed at testing in vacuum with passivation layers present. The presence of the passivation layers causes three funda- mental changes from the first embodiment. First, the threshold energy which the laser light must oyer- come is reduced by the presence of the passivation layers. Second, the photoelectron energy discrimi- nation is accomplished differently, by the use of photon-assisted tunneling, rather than by electrostatic grids and electron optics in vacuum. Third, electrons having passed the energy analysis stage (photon- assisted tunneling into the insulator or passivation layer) must be emitted into vacuum. This is accom- plished by making the metal overlayer very thin.

The apparatus for this second embodiment in Fig. 3 is very similar to that in the first embodiment (Fig. 2) and for common elements is numbered the same. Elements added are metallic overlayer 13, bias means 14 and passivation layer 15. In this case, however, the photon energy from the laser 5 is lower so as to accomplish photon-assisted tunneling of electrons from the metal test points 3 into the conduction band of the insulator/passivation layer 15 present on the chip 1. It is also a condition, easily achieved, that the passivation layer 15 be transparent to the laser light.

The photoelectrons are collected at a very thin (few hundred angstroms or less) metallic overlayer 13 which is deposited onto the passivation layer, such that laser light can also pass through this metal over- layer. With a voltage applied to the metal overlayer 13 by voltage supply 14, proper electrostatic fields are generated across the passivation layer. A fraction of the electrons reaching the metal overlayer 13 will pass through the metal into the vacuum, since the metal overlayer 13 is thin. These electrons are then accelerated and imaged onto microchannel plates 9 as before (if increased gain is necessary) and thence onto the luminescent target 7 to produce a two-dimensional optical image which can be processed to attain the desired test information. In this embodiment, the function of the electron optics is accelera- tion and reimaging, but not voltage discrimination as in the first embodiment.

FIG. 4 is a schematic diagram of a third specific embodiment of the invention, directed at testing in air with passivation layers present. As in the second embodiment, the voltage discrimination is accom- plished by photon-assisted tunneling from the chip test points 3 into the conduction band of the insula- tor/passivation layer 15. However, in this case the photoelectron signal is converted to an optical signal by interaction of the electrons with a luminescent target layer 7 between the insulator 15 and the metal

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overlayer 13 in windows on the chip 1; this luminescent target layer 7 contains electroluminescent or phosphorescent material. Voltage contrast between different points allows the photoelectron-excited lu- minescence of luminescent target 7 to be differentiated from the uniform luminescence likely to be excit- ed by the impinging laser pulse itself. In this third embodiment, no further processing is required other

5 than the reading of the two-dimensional luminescence pattern of luminescent target 7 with a vidicon-type processing system 8. The entire test can be accomplished in air ambient.

Claims

10 1. A system for contactless probing of an integrated circuit chip (1) having test points (3) of interest for testing characterized by control means (4) for introducing dynamic operational signals to the chip (1), so as to cause instantane- ous operational voltages at selected test points (3) as a function of operation; activation means (5-6) for flooding the chip surface with pulsed ultraviolet laser light, causing photoelec-

15 tron emission as a function of the potentials at test points (3) on the chip (1 ); luminescent target means (7), for converting to luminescence values the photoelectron emission from test points (3); and voltage discrimination means (9) located between chip (1) and said luminescent target (7) for modifying photoelectron patterns to represent test point voltages.

20 2. A system according to claim 1 characterized by optical processing system (8) for viewing said luminescent target means (7) and for processing lumines- cent values at selected test points (3) to develop test values as a function of luminescent values.

3. A system according to claims 1 and 2, where vacuum means enclose at least the chip (1 ) and said luminescent target means (7) characterized in that

25 said voltage discriminating means (9) comprises accelerating grid means (11) and electron optics (10) lo- cated between the chip (1) and said luminescent target means (7), whereby laser stimulated photoemis- sions are differentiated over a threshold for detection.

4. A system according to claims 1 and 2 characterized by a thin metallic overlayer (13) and bias means (14), whereby the photoelectron energy discrimination is ac-

30 complished by photon-assisted tunneling through a passivation layer (15) and said metallic overlayer (13), a fraction of emitted photoelectrons passing out of said metallic overlayer (13) into the vacuum to be focussed by electron optics means (10), and to activate said luminescent target (7) for processing by op- tical processing system (8).

5. A system according to claims 1 and 2 characterized by 35 microchannel plates (9) positioned between said accelerating grid means (11) and said optical processing

system (8). 6. A testing method for an integrated circuit chip-to-test (1), characterized by

equipping each integrated circuit to be placed under test with a number of conductive test points (3), at identifiable locations accessible by photons even though covered with a passivation layer (15), the pas-

40 sivation layer (15) being dimensioned and selected of material which is photon transmissive and suscepti- ble to photon assisted tunneling when activated by laser light; adding a thin conductive overlayer (13) over the passivation layer (15), said thin conductive overlayer being metallic or otherwise electrically conductive while penetrable by photons; placing luminescent target means (7) adjacent to the thin conductive overlayer (13) of the integrated cir-

45 cuit 1 under test, to luminesce as a composite function of the laser light activation of the test points (3) and the instantaneous voltage at such test points (3); connecting pulsed laser means, for activating selected test points (3) on the chip-to-test (1) so as to ex- cite luminescence at values related to the instantaneous voltage potential at the accessed test point; connecting integrated circuit test exercise control means (4) to the chip-to-test (1) to cause electronic

50 activity in the chip-to-test (1) appropriate to the desired test, so as to provide at test points (3) voltage potentials related to operation, whether correct or faulty; placing target evaluation means (8) in position for viewing the luminescent target and processing lumines- cence values as a function of control values so as to determine test values for the chip-to-test (1).

7. A testing method according to claim 6 for dynamic testing of an integrated circuit chip-to-test (1) be- 55 fore passivation, said chip-to-test (1) having a number of operational circuits and input/output connec-

tions, whereby a plurality of test points (3) are connected to said operational circuits, characterized by placing the chip-to-test (1) in a vacuum environment in a mounting (2) having electrical connections com- plementary to the input/output connections of the chip-to-test (1), and supporting the chip-to-test (1) for accessibility by laser (5) photons to the test points (3);

60 connecting input/output exercise means (4) to the chip-to-test (1), so as to exercise the circuits on the chip-to-test (1) in a predetermined pattern, to cause electronic activity in the chip-to-test (1) appropriate to the desired test, so as to provide at the selected test point (3) a voltage potential related to operation, whereby the test point (3) accessed by the pulsed laser (5) provides differing values of electron cur- rents as a function of operation voltage differences;

65 control means (4) connected to said laser so as to excite photoemission from selected test points (3),

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which photoemission occurs as electron currents at values related to the instantaneous voltage at the accessed test point (3); placing luminescent target means (7) adjacent to the chip-to-test (1), so as to convert to luminescence of significant duration the photoemission which is a composite function of laser light excitation and of the

5 voltage of the test points, via the passivation layers (15); and evaluating the luminescence to provide test data related to chip (1) operational values.

8. A testing method according to claim 6 for dynamic testing of an integrated circuit chip-to-test (1) af- ter passivation, characterized by the test point (3) accessed by the pulsed laser (5) providing via photon assisted tunneling through the

10 passivating layer to the conductive layer differing values of electron currents as a function of opera- tion voltage differences.

9. A testing method according to Claim 7, characterized by connecting bias means (11) adjacent to the integrated circuit (1) under test, thus controlling the threshold for photoemission;

15 whereby the test point (3) activated by the pulsed laser (5) provides significantly differing readings for proper operation and for faulty operations.

10. A testing method according to Claim 8, further characterized by connecting bias means (14) to the thin conductive overlayer (13) of the integrated circuit (1) under test, thus controlling the threshold voltage for photon assisted tunneling;

20 whereby the test point (3) activated by the pulsed laser (5) provides significantly differing readings for proper operation and for faulty operations.

1 1 . A testing method according to Claim 6, characterized in that the chip-to-test (1) has luminescent target means (7) arrayed over said test points (3) in a fashion where- by relatively long duration luminescence is activated as a composite function of a laser pulse and instan-

25 taneous voltage on the respectively related test point (3). 12. A test method according to claims 8 and 10, characterized by

equipping said test points (3) with a biased metallic overlayer (13), over said luminescent target means (7), thin enough to be penetrable by a laser activation pulse and also by a fraction of emitted lumines- cense.

30 Patentanspruche

1. Anordnung zum kontaktlosen Untersuchen eines integrierten Schaltkreis Chip (1) mit Prufpunkten (3), die fur eine Prufung von Interesse sind, gekennzeichnet durch: Steuerungsmittel (4) zum Einspei-

35 sen dynamischer Arbeitssignale in den Chip (1), urn an ausgewahlten Prufpunkten (3) momentane Arbeits- spannungen in Abhangigkeit von dem Betriebszustand hervorzurufen, Aktivierungsmittel (5-6) zum Ausstrahlen der Chipoberflache mit gepulstem ultraviolettem Laserlicht, wodurch eine Photoelektronen- emission in Abhangigkeit von den Potentialen an den Prufpunkten (3) auf dem Chip (1) hervorgerufen wird, ein lumineszierendes Target (7) zum Umwandeln der Photoelektronenemission von den Priifpunk-

40 ten (3) in Lumineszenzwerte und Spannungsunterscheidungsmittel (9), die zwischen Chip (1 ) und dem lumi- neszierenden Target (7) zum Modifizieren von Photoelektronenmustern gelegen ist, urn Priifpunkts- spannungen darzustellen.

2. Anordnung nach Anspruch 1, gekennzeichnet durch eine optische Verarbeitungsanordnung (8) zum Betrachten des lumineszierenden Target (7) und zum Verarbeiten von Lumineszenzwerten an aus-

45 gewahlten Prufpunkten (3), urn Priifwerte in Abhangigkeit von Lumineszenzwerten hervorzubringen. 3. Anordnung nach Anspruch 1 und 2, bei welcher Vakuum-Mittel zumindest den Chip (1) und das lumi-

neszierende Target (7) einschlieBen, dadurch gekennzeichnet, daB die Spannungsunterscheidungsmittel (9) aus einem Beschleunigungsgittermittel und einer Elektronenoptik bestehen, die zwischen dem Chip (1) und dem lumineszierenden Target (7) gelegen sind, wodurch laserangeregte Photoemissionen Ober einer

50 Schwelle zum Erfassen unterschieden werden. 4. Anordnung nach Anspruch 1 und 2, gekennzeichnet durch eine dunne, metallische Uberdeckungs-

schicht (13) und ein Vorspannungsmittel (14), wodurch die Unterscheidung der Photoelektronenenergien durch photonenunterstutztes Tunneln durch eine Passivierungsschicht (15) und die metallische Uber- deckungsschicht (13) erreicht wird, einen Bruchteil von emittierten Photoelektronen, die aus der metalli-

55 schen Uberdeckungsschicht (13) in das Vakuum hinausgelangen, urn durch Elektronenoptikmittel (10) fokussiert zu werden und das lumineszierende Target (7) zum Verarbeiten mittels einer optischen Ver- arbeitungsanordnung (8) zu aktivieren.

5. Anordnung nach Anspruch 1 und 2, gekennzeichnet durch Mikrokanalplatten (9), die zwischen dem Beschleunigungsgittermittel (11) und der optischen Verarbeitungsanordnung (8) gelegen sind.

60 6. Verfahren zur Priifung eines integrierten Schaltkreis-Chippruflings (1) gekennzeichnet durch: Versehen jedes einer Prufung zu unterziehenden integrierten Schaltkreises mit einer Anzahl von leit- fahigen Prufpunkten (3) an identifizierbaren, gegebenenfalls auch mit einer Passivierungsschicht (15) bedeckten, von Photonen erreichbaren Stellen, wobei die Passivierungsschicht (15) aus einem Material dimensioniert und ausgewahlt wird, das photonendurchlassig ist und ein photonenunterstutztes Tunneln

65 zulaBt, wenn es durch ein Laserlicht aktiviert wird, zusatzliches Anbringen einer diinnen leitfahigen

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Oberdeckungsschicht (13) uber die Passivierungsschicht (15), wobei die dunne leitfahige Uberdeckungs- schicht metallisch oder anderweise elektrisch leitfahig ist, wahrend sie zugieich fur Photonen durch- dringbar ist, Anordnen eines iumineszierenden Target (7) angrenzend an die dunne leitfahige Ober- deckungsschicht (13) des unter Prufung befindlichen integrierten Schaltkreises (1), urn in einer zusam-

5 mengesetzten Abhangigkeit von der Laserlichtaktivierung der Priifpunkte (3) und der momentanen Spannung an solchen Prufpunkten (3) zu lumineszieren, Zuschalten eines gepulsten Lasermittels zum Aktivieren von ausgewahlten Prufpunkten (3) auf dem Chipprufling (1) um eine Lumineszenz bei dem mo- mentanen Spannungspotential an dem erreichten Prufpunkt zugehorigen Werten zu erregen, Zuschal- ten einer Steuereinrichtung (4) zur Durchfiihrung der Prufung eines integrierten Schaltkreises an den

10 Chipprufling (1), damit eine fur die gewunschte Prufung geeignete elektronische Aktivitat in dem Chip- prufling (1) hervorgerufen wird, um an den Prufpunkten (3), entweder richtige oder fehlerbehaftete, dem Betriebszustand zugehorige Spannungspotentiale geliefert werden, Anordnen eines Targetauswertemit- tels (8) in einer Lage zum Betrachten des Iumineszierenden Target und zum Verarbeiten von Lumines- zenzwerten in Abhangigkeit von Steuerwerten, um Prufwerte fur den Chipprufling (1) zu bestimmen.

15 7. Verfahren zur Prufung nach Anspruch 6, zur dynamischen Prufung eines integrierten Schaltkreis- Chippruflings (1) vor einer Passivierung, wobei der Chipprufling (1) eine Anzahl von Arbeitsschaltkrei- sen und Eingabe/Ausgabe-Anschliissen besitzt, wodurch eine Mehrzahl von Prufpunkten (3) an die Ar- beitsschaltkreise geschaltet ist, gekennzeichnet durch: Anordnen des Chippruflings (1) in einer Va- kuumumgebung in einer Fassung (2) mit elektrischen Anschliissen, die komplementar zu den Ein-

20 gang/Ausgang-Anschliissen des Chippruflings (1) sind und Haitern des Chippruflings (1), um von Laser (5) Photonen zu den Prufpunkten (3) hin erreichbar zu sein, Zuschalten des Eingabe/Ausgabe-Durch- fuhrmittels (4) an den Chipprufling (1), um die Schaltkreise auf dem Chipprufling (1) in einem vorbestimm- ten Muster zu betreiben, damit eine fur die gewunschte Prufung geeignete elektronische Aktivitat in dem Chipprufling (1) hervorgerufen wird, um ein dem Betriebszustand zugehoriges Spannungspotential

25 an dem ausgewahlten Prufpunkt (3) zu liefern, wodurch der von dem gepulsten Laser (5) erreichte Pruf- punkt (3) verschiedene Werte der Elektronenstrome in Abhangigkeit von den Betriebsspannungsdiffe- renzen liefert, ein an dem Laser geschaltetes Steuermittel (4) um jene Photoemission von den ausgewahl- ten Prufpunkten (3) anzuregen, welche bei der momentanen Spannung an dem erreichten Prufpunkt (3) zugehorigen Werten als Elektronenstrome in Erscheinung tritt, Anordnen eines an dem Chipprufling (1)

30 angrenzenden, Iumineszierenden Target (7), um die Photoemission, welche eine zusammengesetzte Funktion von Laserlichterregung und der Spannung der Prufpunkte ist, uber die Passivierungsschich- ten (15) in eine Lumineszenz signifikanter Dauer umzuwandeln und Auswerten der Lumineszenz, um den Chip (I)-Arbeitswerten zugehorige Prufungsdaten zu liefern.

8. Verfahren zur Prufung nach Anspruch 6 zur dynamischen Prufung eines integrierten Schaltkreis- 35 Chippruflings (1) nach einer Passivierung, gekennzeichnet durch den von dem gepulsten Laser (5) er-

reichten Prufpunkt (3), der via photonenunterstutztes Tunneln durch die Passivierungsschicht zu der leitfahigen Schicht verschiedene Werte von Elektronenstromen in Abhangigkeit von Betriebsspan- nungsdifferenzen liefert.

9. Verfahren zur Prufung nach Anspruch 7, gekennzeichnet durch Zuschalten eines Vorspannungs- 40 mittels (11) angrenzend an dem unter Prufung befindlichen integrierten Schaltkreis (1), womit die Schwelle

fur eine Photoemission gesteuert wird und wodurch der von dem gepulsten Laser (5) aktivierte Pruf- punkt (3) signifikant verschiedene Ablesungen fur einen richtigen Betrieb und fur einen fehlerhaften Betrieb liefert.

10. Verfahren zur Prufung nach Anspruch 8, ferner gekennzeichnet durch Zuschalten eines 45 Vorspannungsmittels (14) an die dunne leitfahige Oberdeckungsschicht (13) des unter Prufung befindli-

chen integrierten Schaltkreises (1), womit die Schwellspannung fur ein photonenunterstutztes Tunneln gesteuert wird, wodurch der von dem gepulsten Laser (5) aktivierte Testpunkt (3) signifikant verschie- dene Ablesungen fur einen richtigen Betrieb und fur einen fehlerhaften Betrieb liefert.

11. Verfahren zur Prufung nach Anspruch 6, dadurch gekennzeichnet, daB bei dem Chipprufling (1) 50 uber den Prufpunkten (3) ein lumineszierendes Targetmittel (7) derail gruppiert angeordnet ist, daB da-

durch eine verhaltnismaBig lang dauernde Lumineszenz in einer zusammengesetzten Abhangigkeit von einem Laserimpuls und der momentanen Spannung auf dem jeweilig zugehorigen Prufpunkt (3) aktiviert wird.

12. Verfahren zur Prufung nach Anspruch 8 und 10, gekennzeichnet durch das Versehen der Priif- 55 punkte (3) mit einer vorgespannten metallischen Oberdeckungsschicht (13) uber dem Iumineszierenden

Target (7), die genugend dunn ist, um fur einen Laser-Aktivierungsimpuls und auch fur einen Bruchteil einer emittierten Lumineszenz durchlassig zu sein.

Revendications 60

1. Systeme pour la verification sans contact d'une puce de circuit integre (1) comportant des points d'essai (3) interessants pour le controle, caracterise par des moyens de commande (4) pour introduire des signaux operationnels dynamiques dans la puce (1), de fagon a engendrer des tensions operationnel- les instantanees, a des points d'essai choisis (3), qui sont representatives du fonctionnement;

65 des moyens d'activation (5-6) pour eclairer la surface de la puce avec une lumiere laser ultra-violette

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pulsee, provoquant une emission de photo-electrons qui est fonction des potentiels aux points d'essai (3)surlapuce (1); des moyens de cible luminescente (7), pour convertir en valeurs de luminescence remission de photo- electrons venant des points d'essai (3); et des moyens de discrimination de tension (9) places entre la

5 puce (1) et ladite cible luminescente (7) pour modifier les configurations photo-electroniques afin de re- presenter les tensions aux points d'essai. 2. Systeme suivant Ja-revendication 1 , -caracterise par un systeme de traitement optique (8) pour ob-

server lesdits moyens de cible luminescente (7) et pour traiter les valeurs de luminescence a des points d'essai choisis (3), afin d'obtenir des valeurs d'essai en fonction des valeurs de luminescence.

10 3. Systeme suivant les revendications 1 et 2, dans Jequel des moyens sous vide entourent au moins la puce (1) et lesdits moyens de cible luminescente (7); caracterise en ce que lesdits moyens de discrimina- tion de tension (9) comprennent une grille d'acceleration (11) et une optique electronique (10) placees en- tre la puce (1) et ladite cible luminescente (7), de sorte que les photo-emissions stimulees par laser sont differences par rapport a un seuil pour detection.

15 4. Systeme suivant les revendications 1 et 2, caracterise par une mince couche de revetement metalli- que (13) et des moyens de polarisation (14), de sorte que la discrimination d'energie des photo-electrons est effectuee par effet tunnel aide par photons a travers une couche de passivation (15) et ladite cou- che de revetement metallique (13), une fraction des photo-electrons traversant ladite couche de revete- ment metallique (133) et sortant dans le vide pour etre concentree par I'optique electronique (10) et pour

20 exciter ladite cible luminescente (7) pour un traitement par le systeme de traitement optique (8). 5. Systeme suivant les revendications 1 et 2, caracterise par des plaques a micro-canaux (9) placets

entre ladite grille d'acceleration (1 1) et ledit systeme de traitement optique (8). 6. Methode de verification d'une puce de circuit integre en essai (1), caracterisee par Pequipement de

chaque circuit integre a mettre en essai avec une pluralite de points d'essai conducteurs (3), a des en- 25 droits identifiables accessibles par des photons meme si ces points sont recouverts d'une couche de

passivation (15), la couche de passivation (15) etant dimensionnee et choisie en une matiere qui transmet les photons et qui est capable de produire un effet tunnel aide par photons lorsqu'elle est activee par une lumiere laser;

I'addition d'une mince couche de revetement conductrice (13) sur la couche de passivation (15), ladite 30 couche de revetement conductrice mince etant metallique ou electriquement conductrice d'une autre

fagon tout en etant penetrable par les photons; ('installation d'une cible luminescente (7) pres de la couche de revetement conductrice mince (13) du circuit integre (1) en essai, pour produire une luminescence qui est une fonction composite de I'activa- tion par lumiere laser des points d'essai (3) et de la tension instantanee a ces points d'essai (3);

35 la connexion de moyens a laser pulse pour activer des points d'essai choisis (3) sur la puce en essai (1 ) de fagon a exciter une luminescence a des valeurs liees a la tension instantanee au point d'essai ac- cede; la connexion de moyens de commande de programme d'essai de circuit integre (4) a la puce en essai (1) pour provoquer dans la puce en essai (1) une activite electronique appropriee a I'essai desire, de fa-

40 con a engendrer aux points d'essai (3) des tensions liees au fonctionnement, qu'il soit correct ou d&- fectueux; ('installation de moyens devaluation de cible (8) en position d'observation de la cible luminescente et de traitement des valeurs de luminescence en fonction de valeurs de commande, de fagon a determi- ner les valeurs d'essai pour la puce en essai (1).

45 7. Methode de verification suivant la revendication 6, pour la verification dynamique d'une puce de circuit int§gr§ en essai (1) avant passivation, ladite puce en essai (1) comportant une pluralite de circuits operationnels et de connexions d'entree/sortie, de sorte qu'une pluralite de points d'essai (3) sont relief auxdits circuits operationnels, caracterisee par I'installation de la puce en essai (1) dans une ambiance sous vide, dans une monture (2) comportant des connexions llectriques complementaires des con-

50 nexions d'entree/sortie de la puce en essai (1) et le maintien de la puce en essai (1) pour que des photons emis par laser (5) puissent acceder aux points d'essai (3);

la connexion de moyens d'application d'entree/sortie (4) a la puce en essai (1), de fagon a faire fonc- tionner les circuits de la puce en essai (1) suivant une configuration predetermined, pour engendrer dans la puce en essai (1) une activite electronique appropriee a I'essai d6sire, de fagon a creer au point

55 d'essai choisi (3) une tension liee au fonctionnement, de sorte que le point d'essai (3) touche par le laser pulse (5) fournit differentes valeurs de courants d'eiectrons en fonction des differences de tension de fonctionnement; •

des moyens de commande (4) connectes audit laser pour exciter une photo-emission a partir de points d'essai choisis (3), cette photo-emission se produisant sous la forme de courants d'eiectrons a des

60 valeurs liees a la tension instantanee au point d'essai touche (3); I'installation de moyens de cible luminescente (7) pres de la puce en essai (1), de fagon a convertir en

luminescence d'une duree significative la photo-emission qui est une fonction composite de I'excitation par la lumiere laser et de la tension des points d'essai, a travers les couches de passivation (15); et revaluation de la luminescence pour fournir des resultats d'essai lies aux valeurs operationnelles de la

65 puce(1).

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8. Methode de verification suivant la revendication 6, pour la verification dynamique d'une puce de circuit integre en essai (1) apres passivation, caracteris^e en ce que le point d'essai (3) touche par le la- ser pulse (5) fournit, par effet tunnel aide par photons a travers la couche de passivation, a la couche conductrice, des valeurs differentes de courants d'electrons qui sont fonction des differences de ten-

5 sion de fonctionnement. 9. Methode de verification suivant la revendication 7, caracterisee par la connexion de moyens de po-

larisation (11) adjacents au circuit integre (1) en essai, de fagon a fixer le seuil pour la photo-emission; de sorte que le point d'essai (3) active par le laser pulse (5) fournit des indications significativement diffe- rentes pour un fonctionnement correct et pour des fonctionnements defectueux.

10 10. Methode de verification suivant la revendication 8, caracterisee en outre par la connexion de moyens de polarisation (14) a la couche de revetement conductrice mince (13) du circuit integre (1) en es- sai, afin de fixer la tension de seuil pour I'effet tunnel aide par photons; de sorte que le point d'essai (3) active par le laser pulse (5) fournit des indications significativement differentes pour un fonctionnement correct et pour des fonctionnements defectueux.

15 11. Methode de verification suivant la revendication 6, caracterisee en ce que la puce en essai (1) est pourvue de moyens de cible luminescente (7) disposes au-dessus desdits points d'essai (3) d'une facon telle qu'une luminescence de duree relativement longue est activee comme une fonction composite d'une impulsion laser et de la tension instantanee sur le point d'essai respectivement associe (3).

12. Methode de verification suivant les revendications 8 et 10, caracterisee par I'equipement desdits 20 points d'essai (3) avec une couche de revetement metallique polarisee (13), au-dessus desdits moyens

de cible luminescente (7), assez mince pour etre penetrable par une impulsion d'activation laser et egale- ment par une fraction de la luminescence 6mise.

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