Ethernet Link Inspector User Guide for Intel® Stratix® 10 ... · Design examples generated in Intel Quartus Prime Pro Edition software are instantiated with JTAG to Avalon Master

Ethernet Link Inspector User Guidefor Intel® Stratix® 10 Devices

Updated for Intel® Quartus® Prime Design Suite: 19.1

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Contents

1. Overview of Ethernet Link Inspector for Intel® Stratix® 10 Devices............................... 31.1. Features...............................................................................................................3

1.1.1. Link Monitor..............................................................................................31.1.2. Link Analysis.............................................................................................4

1.2. Supported IP Cores and Devices.............................................................................. 4

2. Setting Up the Ethernet Link Inspector........................................................................... 62.1. System Requirements and Prerequisites................................................................... 6

2.1.1. System Requirements................................................................................ 62.1.2. Enabling Your Design For the Link Monitor.....................................................6

2.2. Running the Ethernet Link Inspector........................................................................ 72.2.1. Running the Link Monitor............................................................................ 82.2.2. Running the Link Analysis......................................................................... 10

3. Functional Description.................................................................................................. 133.1. Link Monitor Module............................................................................................. 13

3.1.1. Link Monitor Tabs and Settings.................................................................. 133.2. Link Analysis Module............................................................................................ 15

3.2.1. Sequencer State Machine..........................................................................163.2.2. Link Analysis Tabs and Settings..................................................................19

4. Document Revision History for the Ethernet Link Inspector User Guide for IntelStratix 10 Devices................................................................................................... 34

Contents

Ethernet Link Inspector User Guide for Intel® Stratix® 10 Devices Send Feedback

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1. Overview of Ethernet Link Inspector for Intel® Stratix®

10 DevicesThe Ethernet Link Inspector is an inspection tool that can continuously monitor anEthernet link that contains an Ethernet IP, which includes Ethernet lane alignmentstatus, clock data recover (CDR) lock, media access controller (MAC) statistics,Forward Error Correction (FEC) statistics, and others. If needed, the Ethernet LinkInspector can capture an event with the help of Signal Tap Logic Analyzer to furtherexamine the link behavior during Auto Negotiation (AN), Link Training (LT), or anyother event during the link operation. The Ethernet Link Inspector also creates agraphical user interface (GUI) to represent the link behavior.

1.1. Features

The Ethernet Link Inspector consists of two modules:

• Link Monitor

• Link Analysis

The following sections describe in detail the features of each module.

1.1.1. Link Monitor

The link monitor module performs real-time status monitoring of an Ethernet IP link.

It continuously reads and displays all of the required status registers related to theEthernet IP link. The Link Monitor helps to ensure that all of the Ethernet IP link statusat various stages are valid. In case of any failure, it narrows down to the type offailure based on the various status bits, which are based in the register bank of anEthernet IP core. For more information on the register map, refer to respectiveEthernet IP user guide.

Examples of the Ethernet link status displayed on the Link Monitor user interfaceinclude:

• State of Ethernet IP link (Up or Down)

• State of AN and LT process (Active or Done)

• Number of correct frames received

• Number of frame errors

• Transmitted and recovered clock frequencies etc.

Because the Link Monitor gives out real time link status through Ethernet IP registers,it needs to have a connection with the device that is powered on and configured withthe appropriate design file.

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Intel Corporation. All rights reserved. Agilex, Altera, Arria, Cyclone, Enpirion, Intel, the Intel logo, MAX, Nios,Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/orother countries. Intel warrants performance of its FPGA and semiconductor products to current specifications inaccordance with Intel's standard warranty, but reserves the right to make changes to any products and servicesat any time without notice. Intel assumes no responsibility or liability arising out of the application or use of anyinformation, product, or service described herein except as expressly agreed to in writing by Intel. Intelcustomers are advised to obtain the latest version of device specifications before relying on any publishedinformation and before placing orders for products or services.*Other names and brands may be claimed as the property of others.

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Related Information

• Intel Stratix® 10 10GBASE-KR PHY IP Core User Guide

• Intel Stratix® 10 Low Latency 40-Gbps Ethernet IP Core User Guide

• Intel Stratix® 10 Low Latency 100-Gbps Ethernet IP Core User Guide

• 25G Ethernet Intel Stratix® 10 FPGA IP User Guide

• H-Tile Hard IP for Ethernet Intel Stratix® 10 FPGA IP Core User Guide

• E-Tile Hard IP for Ethernet Intel FPGA IP Core User Guide

1.1.2. Link Analysis

The Link Analysis module displays a sequence of events on an Ethernet IP link, whichoccured in a finite duration of time.

The Link Analysis relies on Signal Tap Logic Analyzer to capture and store database(.csv) of all required signals. Once the Signal Tap Logic Analyzer creates a database,the Link Analysis performs an analysis on the database to extract all the requiredinformation and displays them in a user-friendly graphical user interface (GUI).

The features of the Link Analysis include:

• Ability to capture and display events that occur during Ethernet IP link bring-up.For example, Auto Negotiation and Link Training.

• Ability to capture the link behavior at an intended trigger point and analyze linkbehavior around that time period.

1.2. Supported IP Cores and Devices

Table 1. Ethernet Link Inspector Supported IP Cores for Intel Stratix® 10 L-, H-, andE-tile Devices

Device IP Core Data Rate(Gbps)

IP Type AutoNegotiation

and LinkTraining (1)

FEC (1) LinkMonitor

LinkAnalysis

Intel Stratix®

10 L-tile10GBASE-KR PHYIntel Stratix 10FPGA IP

10 Soft Yes Fire code(2112,2080)

Yes Yes

25G Ethernet IntelFPGA IP

25 Soft N/A RS-FEC(528,514)

Yes N/A

Low Latency 40GEthernet IntelFPGA IP


Yes Yes


100 Soft Yes RS-FEC(528,514)

Yes Yes

Intel Stratix10 H-tile

10GBASE-KR PHYIntel Stratix 10FPGA IP


Yes Yes

continued...

(1) Feature details here shows support model for the IP and not the Ethernet Link Inspectorsupport.

1. Overview of Ethernet Link Inspector for Intel® Stratix® 10 Devices

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IP Type AutoNegotiation

and LinkTraining (1)

FEC (1) LinkMonitor

LinkAnalysis


25 Soft N/A RS-FEC(528,514)

Yes N/A



Yes Yes


100 Soft Yes RS-FEC(528,514)

Yes Yes

H-tile Hard IP forEthernet IntelFPGA IP

50 Hard Yes N/A Yes Yes

100 Hard Yes N/A Yes Yes

Intel Stratix10 E-tile

E-tile Hard IP forEthernet IntelFPGA IP

10 Hard Yes N/A Yes N/A

25 Hard Yes RS-FEC(528,514)

Yes N/A

100(25Gx4 -

NRZ)

Hard Yes RS-FEC(528,514)

Yes N/A

100(50Gx2 -PAM4)

Hard Yes RS-FEC(544,514)

Yes N/A

(1) Feature details here shows support model for the IP and not the Ethernet Link Inspectorsupport.

1. Overview of Ethernet Link Inspector for Intel® Stratix® 10 Devices

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2. Setting Up the Ethernet Link InspectorThis section describes how to set up and run the Ethernet Link Inspector for IntelStratix 10 devices.

2.1. System Requirements and Prerequisites

2.1.1. System Requirements

To run this version of Ethernet Link Inspector for Intel Stratix 10 devices, your systemmust meet the following hardware and software requirements:

• Windows PC or Linux workstation.

• Intel Quartus® Prime Pro Edition software version 19.1 and later.

2.1.2. Enabling Your Design For the Link Monitor

To enable the use of Link Monitor, your design must instantiate JTAG to Avalon®

Master Bridge. The availability of the JTAG to Avalon Master bridge in the Intel Stratix10 Ethernet IP cores is shown in the following table.

Table 2. Availability of JTAG to Avalon Master Bridge in Intel Stratix 10 Ethernet IPCores


IP Type Design Example(2)

Standalone IP(3)

Intel Stratix 10 L-Tile

10GBASE-KR PHY IntelStratix 10 FPGA IP

10 Soft Yes Yes


25 Soft Yes N/A

Low Latency 40GEthernet Intel FPGA IP

40 Soft Yes Yes

continued...

(2) Design examples generated in Intel Quartus Prime Pro Edition software are instantiated withJTAG to Avalon Master Bridge. These design examples also include Ethernet Packet Generatorsthat can be controlled using the Link Monitor.

(3) Supported standalone IPs provide an option called Enable JTAG to Avalon Master Bridge inthe respective IP Parameter Editor GUI in Intel Quartus Prime Pro Edition software. Theselection of this option automatically includes JTAG to Avalon Master Bridge during IPgeneration. This JTAG to Avalon Master Bridge do not provide access to Packet Generators,which is originally part of design example. For non-supported standalone IPs, the JTAG toAvalon Master Bridge has to be manually instantiated from the IP Catalog. Refer to respectiveIP design example RTL and user guides for more details on IP connections.

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IP Type Design Example(2)

Standalone IP(3)


100 Soft Yes Yes

Intel Stratix 10 H-Tile

10GBASE-KR PHY IntelStratix 10 FPGA IP

10 Soft Yes Yes


25 Soft Yes N/A


40 Soft Yes Yes


100 Soft Yes Yes

H-Tile Hard IP forEthernet Intel FPGA IP

50 Hard Yes N/A

100 Hard Yes N/A

Intel Stratix 10 E-Tile

E-Tile Hard IP forEthernet Intel FPGA IP

10 Hard Yes Yes

25 Hard Yes Yes

100(25Gx4-NRZ)

Hard Yes Yes

100(50Gx2-PAM4)

Hard Yes Yes

Related Information

• Intel Stratix 10 10GBASE-KR PHY IP Core User Guide

• Intel Stratix 10 Low Latency 40G Ethernet Design Example User Guide

• Low Latency 100G Ethernet Intel Stratix 10 FPGA IP Design Example User Guide

• 25G Ethernet Intel Stratix 10 FPGA IP Design Example User Guide

• E-tile Hard IP for Ethernet Intel Stratix 10 FPGA IP Design Example User Guide

• H-tile Hard IP for Ethernet Intel Stratix 10 FPGA IP Design Example User Guide

2.2. Running the Ethernet Link Inspector

The Link Monitor and Link Analysis of the Ethernet Link Inspector can be usedindependently for inspecting Ethernet links of the supported IP cores.

(2) Design examples generated in Intel Quartus Prime Pro Edition software are instantiated withJTAG to Avalon Master Bridge. These design examples also include Ethernet Packet Generatorsthat can be controlled using the Link Monitor.

(3) Supported standalone IPs provide an option called Enable JTAG to Avalon Master Bridge inthe respective IP Parameter Editor GUI in Intel Quartus Prime Pro Edition software. Theselection of this option automatically includes JTAG to Avalon Master Bridge during IPgeneration. This JTAG to Avalon Master Bridge do not provide access to Packet Generators,which is originally part of design example. For non-supported standalone IPs, the JTAG toAvalon Master Bridge has to be manually instantiated from the IP Catalog. Refer to respectiveIP design example RTL and user guides for more details on IP connections.

2. Setting Up the Ethernet Link Inspector

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You can run the Ethernet Link Inspector using System Console in the Intel QuartusPrime Pro Edition software. There are two separate Launch buttons to open LinkAnalysis and Link Monitor of the Ethernet Link Inspector as shown in the followingfigure.

2.2.1. Running the Link Monitor

Perform the following steps to launch the Link Monitor module.

Figure 1. Example Link Monitor Tab


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1. In the Intel Quartus Prime Pro Edition software, select Tools ➤ SystemDebugging Tools ➤ System Console to launch the system console.

2. In the system console, click the Launch button under the Ethernet LinkInspector - Link Monitor section to run the Link Monitor module. The EthernetLink Inspector - Link Monitor tab appears.

Note: You can open multiple instances of the Link Monitor module simultaneouslyfor different IPs.

3. In the Ethernet Link Inspector - Link Monitor tab, follow these steps to set thecorrect JTAG to Avalon Master path:

a. Load the Programming File (*.sof) in System Console by clicking File ➤Load Design for the detailed JTAG to Avalon Master path.

b. Select List JTAG Masters to see all available JTAG to Avalon Master paths.

c. Select a JTAG to Avalon Master path number from the drop-down box and clickSet JTAG Master.

Note: Each JTAG to Avalon Master path lists two TYPE_NAME (marked by theblue box in the figure below). The instance name of the JTAG to AvalonMaster path is displayed in one of these TYPE_NAME along with the textFULL_HPATH (marked by the orange box in the figure below). Select theJTAG to Avalon Master path number that has the instance name of theJTAG to Avalon Master path connected to the Ethernet IP.

Figure 2. Example JTAG Master Selection Panel

The instance name of the JTAG to Avalon Master path is jtag_masterand it is displayed along with the text FULL_HPATH, as shown in thefigure below.

Figure 3. Example of Instance Name of JTAG to AvalonMaster Path

d. From the Select IP Variant drop-down list, select an IP Variant and clickLaunch to populate the user interface of the Link Monitor.


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2.2.2. Running the Link Analysis

Perform the following steps to launch the Link Analysis module.

Figure 4. Example Link Analysis Tab

1. In the Intel Quartus Prime Pro Edition software, select Tools ➤ SystemDebugging Tools ➤ System Console to launch the system console.

2. In the system console, click the Launch button under the Ethernet LinkInspector - Link Analysis section to run the Link Analysis module. TheEthernet Link Inspector - Link Analysis tab appears.

Note: You can open multiple instances of the Link Analysis module simultaneouslyfor different IPs.

3. In the Ethernet Link Inspector - Link Analysis tab, select the target IP corefrom the drop-down box.

4. Click the Select .csv file button to import the Signal Tap database (.csv) file.Refer to the Creating and Capturing Signal Tap Database and Exporting as CSVFile section in this user guide to create the .csv file. In the Status Bar, make surethe directory to the imported database is correct.

5. Click the Start Analysis button.

Note: If you want the summary of the Ethernet link capture without using the LinkAnalysis, enter a report name and click Generate Report button to createa report (.csv) file. This feature is supported only for 10GBASE-KR PHYIntel Stratix 10 FPGA IP and Intel Stratix 10 Low Latency 40G Ethernet IntelFPGA IP.

You can now use the Link Analysis to analyze the Signal Tap database.

2.2.2.1. Creating and Capturing Signal Tap File and Exporting Signal TapDatabase as CSV File

Creating a Signal Tap (.stp) File

To create a Signal Tap file, follow these steps:


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1. To create .stp file with the list of expected signals for a specific Ethernet IP core,refer to the document Link_Analysis_STP_RequiredSignals.xlsx provided in the Ethernet_Link_Inspector_Package.zip file.

2. For design examples, use the Signal Tap files provided in the Ethernet_Link_Inspector_Package.zip file to capture a Signal Tap file.

Capturing a Signal Tap (.stp) File

To capture a Signal Tap file (i.e., link bring up sequence after reset that includes AutoNegotiation and Link Training), follow these steps:

1. Program the .sof file using the Intel Quartus Prime Pro Edition software.

2. Double click on the created .stp file associated with the .sof file to open theSignal Tap Logic Analyzer.

3. Clear the .stp file so that it does not contain any previous captured data byholding the IP into reset and clicking Run Analysis, followed by Stop Analysison the Signal Tap Logic Analyzer toolbar.

The IP can be reset by using either of the following two methods:

a. Using the Link Monitor, click once on Assert Full System Reset in theResets panel under the MAC & PCS tab.

b. Direct access to reset ports or registers.

4. Using the Link Monitor, maintain the IP reset by clicking once on Assert FullSystem Reset in the Reset panel under the MAC & PCS tab.

5. To start the Signal Tap data capture, click Run Analysis in the Signal Tap LogicAnalyzer.

6. Using the Link Monitor, release the IP reset by clicking once on Deassert FullSystem Reset in the Reset panel under the MAC & PCS tab.

Note: The Signal Tap Logic Analyzer may not stop automatically after releasingreset if the captured data is not enough to completely fill the memory. If theSignal Tap capture does not stop on its own, follow the steps below:

a. Wait 2 to 5 seconds.

b. Click Stop Analysis on the Signal Tap Logic Analyzer toolbar.

Exporting a Signal Tap Database as Comma Separated Value (.csv) File

The Signal Tap Logic Analyzer can save Signal Tap database in a .csv format. Afterthe Signal Tap capture is completed, export the database. Once the database is saved,import the database through Link Analysis for further processing.

To export a Signal Tap data as CSV (.csv) database, follow these steps:

1. In the Signal Tap Logic Analyzer, select Files ➤ Export to export the captureddata.

2. Specify the File Name, Directory, and Export Format (in .csv file format).

3. Click OK to generate the .csv database of the captured data.

The Link Analysis reads all the data that are being captured and stored by Signal TapLogic Analyzer. To prevent processing error, it is important that you export and storethe Signal Tap waveform database in .csv format, which contains a list of signals thatthe Link Analysis expects to receive.


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Related Information

• Debug Tools User Guide: Intel Quartus Prime Pro EditionMore information on Signal Tap Logic Analyzer in Intel Quartus Prime ProEdition software.

• Ethernet Link Inspector Package (.zip) File


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3. Functional DescriptionThis section describes the various parts of the Ethernet Link Inspector user interfaceand how each part represents the device behavior. The Ethernet Link Inspectorconsists of two inspection modules: Link Monitor and Link Analysis.

3.1. Link Monitor Module

3.1.1. Link Monitor Tabs and Settings

The Link Monitor module of the Ethernet Link Inspector has three tabs. Each tabimplements various Control and Status Registers (CSR) of the selected Ethernet IPcore. There is also a Continuous Read All Registers option, which continuously pollsthe status of all the tabs.

Table 3. Link Monitor GUI Tabs

Tab Description

MAC & PCS Resets the IP core, reads the MAC configuration and checks the high level PCSstatus.• Resets: Implements the RESET register.• MAC Status: Shows the status of TX MAC registers and RX MAC registers.• PCS Status: Shows the status of PCS registers.• FEC Status: Shows the status of FEC registers.

Statistics • Displays MAC statistics registers for TX and RX traffic.• Displays FEC statistics.

PMA • Displays KR/KR4 registers that includes Auto Negotiation and Link Training.• Displays PMA parameters such as differential output voltage (VOD), continuous

time linear equalizer (CTLE), distributed feedback equalizer (DFE), and etc.

Help Displays link bring up guidelines

The following figures show the Link Monitor GUI tabs and are related to the 25G E-tileHard IP for Ethernet Intel FPGA IP. The availability of each tab depends on IP selectionand its features.

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Figure 5. Example MAC & PCS Tab

Figure 6. Example Statistics Tab

3. Functional Description

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Figure 7. Example PMA Tab

Figure 8. Example Help Tab

3.2. Link Analysis Module

Link Analysis module of the Ethernet Link Inspector plots the behavior of an EthernetIP link based on specific signals captured from Signal Tap Logic Analyzer.


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When an Ethernet IP core is configured in a KR/CR configuration (which includes AutoNegotiation and Link Training), the local device can be in either one of the followingfour operational modes starting from power-up to the device operation of the IP core:

1. Sequencer Initialize mode (SEQ_Initialize)

2. Auto Negotiation mode (Auto_Neg)

3. Link Training mode (Link_Training)

4. Data mode (Data)

The local device implements various internal states as part of the Sequencer StateMachine to represent the four modes above. The local device may use one or more ofthe internal states to represent any one of the above mode. Refer to Sequencer StateMachine on page 16 for more details.

3.2.1. Sequencer State Machine

The Ethernet IP cores for Intel Stratix 10 devices implement an internal state machinecalled Sequencer State Machine (SSM) that represents the Ethernet IP link bring-up.At any point of time, the device should be in one of SSM states.


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Figure 9. Flowchart of SSM StatesThis figure shows the various states of SSM and how these states are mapped to the operational modes.

1. SEQ_INITIALIZE

SSM_ENABLE

2. AUTO_NEG

SSM_RC_AN

SSM_AN_ABL

SSM_AN_CHK

3. LINK TRAINING

SSM_RC_LT

SSM_LT_CHK

4. DATA

SSM_RC_10G

SSM_10G_CHK

SSM_LNK_RDY

SSM_LR_WAIT

AN DONE (an_done==0)

AN DONE (an_done==1)

Local RX Ready(lcl_rx_ready ==0)

Local RX Ready (lcl_rx_ready ==1)

For 10GBASE-KR: (rx_data_ready==0)For LL 40GbE: (rpcs_deskew_lock==0)

For 10GBASE-KR PHY: (rx_data_ready==0 or rx_is_lockedtodata==0)For LL 40GbE:(rpcs_deskew_lock==0 or rx_is_lockedtodata==0)

For 10GBASE-KR PHY:(rx_data_ready==1 & rx_is_lockedtodata==1 for at least 1 ms)For LL 40GbE:(rx_deskew_lock==1 & rx_is_lockedtodata==1 for at least 1 ms)

For 10GBASE-KR PHY:(rx_data_ready==1 & rx_is_lockedtodata==1 for at least 1 ms)For LL 40GbE:(rx_deskew_lock==1 & rx_is_lockedtodata==1 for at least 1 ms)

For 10GBASE-KR PHY:(rx_data_ready==1 & rx_is_lockedtodata==1 for at least 1 ms)For LL 40GbE:(rx_deskew_lock==1 & rx_is_lockedtodata==1 for at least 1 ms)For 10GBASE-KR PHY: (rx_data_ready==0)

For LL 40GbE:(rpcs_deskew_lock==0)

For H-Tile Hard 50G and 100G:(o_rx_am_lock ==0 & o_rx_hi_BER == 1)


For H-Tile Hard 100G:(o_rx_am_lock ==1 & o_rx_hi_BER == 0)



For LL 100GbE:(deskew_lock==1 & rx_is_lockedtodata==1 for at least 1 ms)For LL 100GbE: (deskew_lock==0)

For LL 100GbE:(deskew_lock==1 & rx_is_lockedtodata==1 for at least 1 ms)

For LL 100GbE:(deskew_lock==1 & rx_is_lockedtodata==1 for at least 1 ms)

For LL 100GbE: (deskew_lock==0)

For LL 100GbE:(deskew_lock==0 & rx_is_lockedtodata==0)

Table 4. SSM State Descriptions

SSM State Description

SSM_ENABLE The first state used for Sequencer State Machine (SSM) initialization. This shouldbe the first state of device after a power cycle or a reset. If Auto Negotiation(AN) and Link Training (LT) are enabled, the local device moves to theSSM_RC_AN state after this state is completes.

SSM_RC_AN Indicates the reconfiguration of PHY for Auto Negotiation operation.

continued...


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SSM_AN_ABL After the completion of SSM_RC_AN state, the local device goes into theSSM_AN_ABL state. In this state, the transmitter of the local device is disabled(i.e., no transitions) so that the Ethernet IP link goes down and the Ethernet IPlink partner also goes back to Auto Negotiation. Even without any Ethernet IPlink partners connected, the local device should complete this state and move tothe next state i.e., SSM_AN_CHK. The local device spends an approximate timeof 60 to 75 miliseconds (ms) in this state. At the end of this state, the localdevice starts sending AN Base Page to the remote device.

SSM_AN_CHK Once the local device starts sending AN base page, it moves to the stateSSM_AN_CHK. The rest of the AN happens in this state. The following are majorAN events that happen in this state:1. Waiting for AN base Page from Remote Device2. Waiting for an ACK from Remote Device3. Sending an ACK to Remote Device4. Doing NEXT PAGE communication (if any)5. Asserting the an_done signalVarious events during AN are further categorized into a separate state machinecalled AN Arbiter State Machine. Refer to Auto Neg Tab on page 21 for moredetails.

SSM_RC_LT Indicates the reconfiguration of PHY for LT operation.

SSM_LT_CHK After completion of SSM_RC_LT, device goes into SSM_LT_CHK state. This stateincludes the LT packet communication between the two devices, local andremote. At the end of this state, both devices should have completed LT andacknowledge each other upon completion.

SSM_RC_10G (4)

SSM_RC_DAT (5)Indicates that the reconfiguration of PHY for:• 10G/10GFEC mode for 10GBASE-KR operation.• 40G/40GFEC mode for 40GBASE-KR4 operation.• 50G and 100G modes for H-tile Hard and 100GBASE-KR4 Low Latency

operation.

SSM_10G_CHK (4)

SSM_LNK_CHK (5)After the completion of the SSM_RC_10G/SSM_RC_DAT state, the local devicegoes into the SSM_10G_CHK/SSM_LNK_CHK state. In this state, the local devicetries to achieve lock on the received Ethernet packets. The following statussignals shows the lock status:1. 10GBASE-KR PHY Intel Stratix 10 FPGA IP core: rx_data_ready2. For Low Latency 40G Intel FPGA IP core: rpcs_deskew_lock3. For Intel Stratix 10 H-Tile Hard 50G and 100G IP cores: o_rx_am_lock4. For Low Latency 100G Intel FPGA IP core: deskew_lockThe local device will move to the next state called SSM_LNK_RDY when the lockconditions are met.

continued...

(4) SSM state for 10GBASE-KR PHY Intel Stratix 10 FPGA IP and Low Latency 40G Ethernet IntelFPGA IP cores.

(5) SSM state for Intel Stratix 10 H-Tile Hard 50G and 100G IP cores and Low Latency 100G IntelFPGA IP core.


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The local device can only remain in this state if the total time, starting fromSSM_RC_LT, does not exceed 500 ms. If the total time exceeds 500 ms and thelock conditions are still not met, the local device goes back to SSM_ENABLE stateand redo the AN and LT.

SSM_LNK_RDY Indicates that the local device has successfully locked on to the receivedEthernet packets and processed them accordingly. The local device is expected tobe in this state during the entire exchange of Ethernet packets unless it losseslock (rx_data_ready or rx_is_lockedtodata). If the local device losseslock, it goes to the next SSM state called SSM_LR_WAIT.

SSM_LR_WAIT The Ethernet IP link goes into SSM_LR_WAIT state if any of the following lockstatus signals goes low during SSM_LNK_RDY state:1. For 10GBASE-KR PHY Intel Stratix 10 FPGA IP core: rx_data_ready or

rx_is_lockedtodata

2. For Low Latency 40G Intel FPGA IP core: rpcs_deskew_locked orrx_is_lockedtodata

3. For Intel Stratix 10 H-Tile Hard 50G and 100G IP cores: o_rx_am_lock orrx_is_lockedtodata

4. For Low Latency 100G Intel FPGA IP core: deskew_locked orrx_is_lockedtodata

For example, the local device wait for maximum of 1000 clock cycles to check ifthe lock conditions are met. If lock conditions are not met within 1000 clockcycles, the link goes back into SSM_ENABLE state. If the lock conditions are metany time before the 1000 clock cycles, the link goes back to SSM_LINK_RDYstate.

3.2.2. Link Analysis Tabs and Settings

The Link Analysis (LINK ANALYSIS) module of the Ethernet Link Inspector has fivetabs:

• Sequencer State Machine tab

• Auto Neg tab

• Link Training tab

• Data Mode tab

• Help tab

3.2.2.1. Sequencer State Machine Tab

The Sequencer State Machine (SSM) tab shows the flow of sequencer state machinestates that the device goes through in the specific Signal Tap capture for the selectedEthernet IP core.


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Figure 10. Example of Sequencer State Machine Tab GUI

Note: SSM State names in below image is for 10GBASE-KR PHY Intel Stratix 10 FPGA IPcore. Based on the Ethernet IP, these state names may vary. Refer to Table 4 on page17 for details on state names specific to the IP.

Table 5. Sequencer State Machine Tab Parameters

Parameter Description

Assumed Reference Timer Clock Shows the assumed value of the clock frequency driving the reference timer.Ensure that the value of this clock is the same as the clock frequency configuredin the Platform Designer window of the selected Ethernet IP core.Note: If the assumed value of the clock frequency does not match the clock

frequency in Platform Designer window of the selected IP core, the timervalues displayed in Link Analysis GUI will be incorrect. For example, theTimer values reported in Start, Stop and Delta columns in the SequencerState machine tab would be incorrect.

States Shows the flow of SSM states (from SEQ_Initialize to Data modes) that thedevice goes through in a specific capture. A successful state completion ishighlighted in green whereas a state completion failure is highlighted in red.

continued...


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Start Timestamp for start time. Shows the reference timer value (in milisecond)corresponding to a specific state of SSM started.

Stop Timestamp for stop time. Shows the reference timer value (in milisecond)corresponding to a specific state of SSM finished.

Delta Timestamp for delta time. Shows the total time spent (in milisecond) on aspecific state of SSM.

3.2.2.2. Auto Neg Tab

The Auto Neg tab may have one or more subtabs based on number of times thedevice goes into Auto Negotiation (AN) state during the Signal Tap capture in a finiteamount of time. Each subtab displays the Ethernet IP link behavior during theoccurrence of AN. Each AN occurrence is also prefixed with a number to distinguishbetween various AN occurrences.

Table 6. Local Device Status Signals

Name Signal (6) Indication Description

Auto Negotiation (AN)Enable

an_enable LED • Green: Auto Negotiation is enabled.• Red: Auto Negotiation is disabled.

Auto Negotiation (AN)Done

an_done LED • Green: Auto Negotiation completed. This LEDindication does not mean that the local device hasfinalized the common technology. Even in case oftechnology mismatch between the local andremote devices, an_done will be asserted.

• Red: Auto Negotiation is not completed.

Local Auto Negotiation(AN) Technology

[lcl_tech] or[E25_TECH]

Text Displays the Auto Negotiation technology broadcastedby the local device.

Final Auto Negotiation(AN) Technology

[hcd_40g,hcd_kr,

hcd_xaui,hcd_gige] or

[ieee_mode] or[e25_mode]

Text • Displays the converged Auto Negotiationtechnology by the local device.

• Shows the corresponding timestamp of technologyconvergence.

Table 7. Remote Device Status Signals

Name Signal Indication Description

Remote Device AutoNegotiation Technology

[lp_tech] or[lp_e25_mode]

Text • Displays the Auto Negotiation technologybroadcasted by the remote device.

• Shows the timestamp when the local devicereceives this broadcasted technology.

AN Communication Packet

The AN Communication Packet section displays the exchange of AN packets betweentwo devices. There are two parts to the AN Communication Packets section:

(6) Actual signal names in the IP design file.


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• AN Packets Received—shows the sequence of AN packets (from left to right)received from a remote device.

• AN Packets Sent—shows sequence of AN packets (from left to right) sent to aremote device.

Figure 11. AN Communication Packet GUI

Table 8. AN Communication Packet GUI Parameters


AN Packets(48-bits) Shows the Auto Negotiation packets exchanged between local and remote devicesin hexadecimal format.

Time(msec) Shows the SSM state in which AN packets are sent/received along with thetimestamp with respect to reference timer

Packet Details(hex) Shows the breakout for various bits in an AN packet and displays whether an ANpacket in base page or next page.Note: The assumption for BASE PAGE or NEXT PAGE only holds true when AN

states are captured from the actual start point of Auto Negotiation (i.e.,start point of SSM_RC_AN). If the AN states are captured partially inSignal Tap Logic Analyzer, this assumption becomes unreliable.

AN Arbiter State Machine

The AN Arbiter State Machine section displays the AN Arbiter State Machine in theform of time domain waveforms. The AN arbiter state machine represents the entireEthernet IP link behavior in the AN mode of operation.


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Each waveform window represents a timescale for one Sequencer State Machine(SSM) state (i.e., SSM_RC_AN, SSM_AN_ABL or SSM_AN_CHK). The time scale ofwaveform windows, such as START and STOP time, should match the timestamp ofthe corresponding SSM state. The waveform windows are also tagged with specificSSM states, as shown in the following figure:

Figure 12. Time Domain Waveforms of the Sequencer State Machine States

Each AN Arbiter SM state is represented as an individual waveform. A logic 1 value ona state waveform at a particular timestamp signifies the current state of the device atthat timestamp. Device can possibly be in only one state at a given point of time. Tochange the magnification level of the waveforms, click the left mouse button and dragthe mouse cursor to the bottom right of the waveform windows to zoom in and dragthe mouse cursor the top right of the waveform windows to zoom out.

Note: While zooming in and out, the waveform windows may be offset in the vertical scale.This may cause several waveform windows in a row to be misaligned for logic 0 and 1.To remove any misalignments and scale the Y axis of all waveform window to acommon scale, click on the Scale Waveforms (Y-axis) button.

Figure 13. Flowchart of AN Arbiter State MachineThis figure shows a flow chart of the AN Arbiter State Machine and the conditions that drives the next state,based on the current state.

SSM_RC_AN SSM_AN_ABL SSM_AN_CHK

AN_ARB_ABL_DET

AN Base PageACK sent bylocal device

AN BasePage sent bylocal device

ANBase Page

Received from RD?

AN_ARB_AN_GOODAN Completed

No, NEXT PAGEnot requested in the

previous Page

AN_ARB_ACK_DET

ACKReceived from

RD?

AN_ARB_NXT_PAGENo

Yes

No

Yes

No

YesAN

Next PageReceived from

RD?Yes, NEXTPAGE requestedin previouspage

Yes

No

AN_ARB_ENABLE

AN NextPageACK sent bylocal device

AN NextPage sent bylocal device

AN_ARB_TX_DIS AN_ARB_COMP_ACKNextPage

Requested?

ACKReceived

from RD?


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Table 9. AN Arbiter State Machine State and Signal Descriptions

Name Indication Description

AN_ARB_ENABLE Waveform This is the initial state of the AN Arbiter State Machine. Thisshould be enabled (logic 1 value) during SSM_RC_AN state.This state ends after the start of SSM_AN_ABL and the localdevice moves to the next state i.e., AN_ARB_TX_DIS.

AN_ARB_TX_DIS Waveform In this state, the TX output of the local device is disabled fora finite amount of time to allow the remote device to startAuto Negotiation. This causes to link to go down. Theduration of this state can be 60 to 75 ms. Device shouldalways complete this state irrespective if there is a remotedevice available or not.

AN_ARB_ABL_DET Waveform In this state, the local device send out the AN Base Pageand waits for the AN base page from the remote device. Thelocal device goes into this state at the end of SSM_AN_ABL.The local device waits in this state until the AN Base page isreceived and the corresponding Acknowledgement (ACK) issent out to the remote device. The local device moves tonext state after sending ACK to the remote device.If the ACK is not received from the remote device at thistime, the local device moves to AN_ARB_ACK_DET where itwaits for ACK from the remote signal. Else, the local devicemoves to AN_ARB_COMP_ACK, which indicates thecompletion of ACK exchange between the two devices.

AN_ARB_ACK_DET Waveform In this state, the local device is waiting for ACK from theremote device.

AN_ARB_COMP_ACK Waveform When an acknowledgement is sent to as well as receivedfrom the remote device, the local device moves to this statecalled the Ack Complete state.

AN_ARB_AN_GOOD Waveform This state indicates that AN has succesfully completed onlocal device and is the final state of AN Arbiter StateMachine.

AN_ARB_NXT_PAGE Waveform This state shows that the local device is sending NEXT pageand waits for NEXT page from the remote device. This stateremains until the local device send ACK to the remotedevice.

Table 10. AN Arbiter State Machine Signal Descriptions

Name Indication Description

an_enable Waveform Displays when AN is enable. This is waveformrepresentation of the AN Enable signal described in Table 6on page 21.

an_done Waveform Displays when AN is completed successfully. This iswaveform representation of the AN Done signal described in Table 6 on page 21.

3.2.2.3. Link Training Tab

The Link Training Mode tab may have one or more subtabs based on number of timesthe device go into Link Training (LT) state during the Signal Tap capture in a finiteamount of time. Each subtab displays the Ethernet link behavior during the occurrenceof LT. Each LT occurrence is also prefixed with a number to distinguish betweenvarious LT occurrences.


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Link Training Enable lt_enable LED • Green: LT is enabled.• Red: LT is disabled.

Frame Lock frame_lock LED • Green: Detected andlocked from receiving LTpackets. Also shows thetimestamp of lock.

• Red: Not locked fromreceiving LT packets.

RX Trained rx_trained LED • Green: LT completed.• Red: LT not completed.

Local RX Ready lcl_rx_ready LED This signal is a delayedversion of rx_trainedsignal.• Green: LT completed.• Red: LT not completed.

Link Training commands sentby Local Device

rmt_coef_updl,rmt_coef_updh

— —

Init — Label Indicates the total Initializecommands sent.

Preset — Label Indicates the total Presetcommands sent.

Main Incr — Label Indicates the total main-tapincrement commands sent.

Main Dec — Label Indicates the total main-tapdecrement commands sent.

Post-Tap Incr — Label Indicates the total post-tapincrement commands sent.

Post-Tap Dec — Label Indicates the total post-tapdecrement commands sent.

Pre-Tap Incr — Label Indicates the total pre-tapincrement commands sent.

Pre-Tap Dec — Label Indicates the total pre-tapdecrement commands sent.

Table 12. Remote Device Status Signals


Remote RX Ready rmt_rx_ready LED • Green: LT completed.• Red: LT not completed.

Link Training commands sentby Remote Device

lcl_coefh, lcl_coefl — —

Init — Label Indicates the total Initializecommands sent.

continued...

(7) All the descriptions in Table 11 on page 25 are with reference to local device.

(8) All the descriptions in Table 12 on page 25 are with reference to remote device.


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Preset — Label Indicates the total Presetcommands sent.

Main Incr — Label Indicates the total main-tapincrement commands sent.

Main Dec — Label Indicates the total main-tapdecrement commands sent.

Post-Tap Incr — Label Indicates the total post-tapincrement commands sent.

Post-Tap Dec — Label Indicates the total post-tapincrement commands sent.

Pre-Tap Incr — Label Indicates the total pre-tapincrement commands sent.

Pre-Tap Dec — Label Indicates the total pre-tapdecrement commands sent.

Table 13. Link Training Status Signals

Signal Indication Description

frame_lock Waveform Displays the behavior of frame_lockin a time domain. When asserted, itindicates that the local device locked toLT packets. This is a waveformrepresentation of the Frame Locksignal in the Table 11 on page 25.

rx_trained Waveform Displays the behavior of rx_trainedin a time domain. When asserted, itindicates that the local devicecompleted LT. This is a waveformrepresentation of the RX Trained signalin the Table 11 on page 25.

lcl_rx_ready Waveform Displays the behavior oflcl_rx_ready in a time domain.When asserted, it indicates that thelocal device completed LT. This is awaveform representation of the LocalRX Ready signal in the Table 11 onpage 25.

rmt_rx_ready Waveform Displays the behavior ofrmt_rx_ready in a time domain.When asserted, it indicates that theremote device completed LT. This is awaveform representation of theRemote RX Ready signal in the Table12 on page 25.

LT Communication Packets

The LT Communication Packets section displays the LT packets exchanged betweentwo devices. The LT Communication packets option has to be enabled to start plottingLT packets. A timestamp header is stored with each packet with respect to thereference timer. The transaction of the LT packet plotting may take a few minutesbased on the number of packets that are being exchanged. To determine whether theplotting is completed or still in progress, monitor the status bar.

(8) All the descriptions in Table 12 on page 25 are with reference to remote device.


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Figure 14. LT Communication Packet Exchange between Local Device and RemoteDevice

LocalDevice

RemoteDevice

1. Commands

2. Status

3. Commands

4. Status

If the LT Communication Packets option is checked, the following subsections willbe displayed on the tab-window of the Link Training:

1. Commands sent by Remote Device (signals: lcl_coefh, lcl_coefl)

2. Status to Remote Device (signals: lcl_coef_sts)

3. Commands sent by Local Device (signals: rmt_coef_updl, rmt_coef_updh)

4. Status to Local Device (signals: rmt_coef_sts)

For every command sent by the local or remote device, there is an equivalent statusbeing sent back by the receiver end. The statuscorresponding to every command canbe mapped by monitoring their time stamps, as shown in the following figure:

Figure 15. LT Training SequenceThis figure shows the timestamps corresponding to Command1 (C1) -> Status1 (S1) and Command2 (C2) ->Status2 (S2) represents the time taken by taken by either device to respond to the LT commands.

Table 14. Link Training Command Definitions

Command Description

Post- Decreases post-tap by 2 and increases main-tap by 1.

Post+ Increases post-tap by 2 and decreases main-tap by 1.

Main- Decreases main-tap by 1.

continued...


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Command Description

Main+ Increases main-tap by 1.

Pre- Decreases pre-tap by 2 and increases main-tap by 1

Pre+ Increases pre-tap by 2 and decreases main-tap by 1

Hold Do not change any tap values.

Preset Sets pre-tap and post-tap to zero and main-tap to maximum, as defined inClause 72 of the IEEE 802.3 2015 Standard.

Initialize Sets the coefficients back to initial (start) values configured in the IP core.

The following figure shows the direction in which the digital values of main-tap, post-tap, and pre-tap move based on commands. For more details on these values, refer tothe Intel Stratix 10 L- and H-Tile Transceiver PHY User Guide.

Figure 16. Direction of Main-Tap, Post-Tap, and Pre-Tap Based On Link TrainingCommands

Increment

Decrement

-31 -15 -1 0 +1 +15 +30

Table 15. Status Definitions

Status Description

no upd No taps updated.

Post-upd Post-tap updated. This status is valid for both increment and decrementcommand

Post-max Post-tap incremented and is at maximum value

Post-min Post-tap decremented and is at minimum value

Pre-upd Pre-tap updated. This status is valid for both increment and decrement command

Pre-max Pre-tap incremented and is at maximum value.

Pre-min Pre-tap decremented and is at minimum value.

Main-upd Main-tap updated. This status is valid for both increment and decrementcommand.

Main-max Main-tap incremented and is at maximum value.

Main-min Main-tap decremented and is at minimum value.

Note: If the command or status shows "----", this indicates that the values in the LT packetare invalid.

Related Information

Intel Stratix 10 L- and H-Tile Transceiver PHY User Guide


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https://www.intel.com/content/www/us/en/programmable/documentation/wry1479165198810.html#thp1479167108381


3.2.2.4. Data Mode Tab

Data Mode tab may have one or more subtabs based on number of times the devicego into Data Mode state during the Signal Tap capture in a finite amount of time. Eachsubtab displays the Ethernet IP link behavior during the occurrence of Data Mode.Each Data Mode occurrence is also prefixed with a number to distinguish betweenvarious Data Mode occurrences.



For 10GBASE-KR Intel Stratix 10 FPGA IP:

RX Block Lock rx_block_lock LED • Green: Locked fromreceiving Ethernetpackets. Also shows thetimestamp of lock.

• Red: Not locked fromreceiving Ethernetpackets.

RX Data Ready rx_data_ready LED • Green: Representssuccessful block lockassertion. Also shows thetimestamp. an_done willbe asserted.

• Red: Block lock notasserted.

FEC pcs_mode_rc LED • Green: Local device isusing FEC.

• Red: Local device is notusing FEC.

For Intel Stratix 10 Low Latency 40G Ethernet Intel FPGA IP:

PCS Align Lock rpcs_align_locked LED • Green: All 4 lanes areskew compensated andaligned. Also shows thetimestamp of lock.

• Red: Lanes are not skewcompensated and notaligned.

PCS Deskew Lock rpcs_deskew_locked LED • Green: All 4 lanes arelocked for alignmentmarker. Also shows thetimestamp of lock.

• Red: Lanes are notlocked for alignmentmarker.



PCS Word Lock rpcs_word_locked LED This signal is available perchannel basis. There arefour signals for 40GBASE-KR.

continued...


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• Green: Locked fromreceiving Ethernetpackets.


RX ENH Block Lock rx_enh_blk_lock LED This signal is available perchannel basis. There arefour signals for 40GBASE-KR.• Green: FEC is locked

from receiving Ethernetpackets.

• Red: FEC is not lockedfrom receiving Ethernetpackets.

For Intel Stratix 10 H-Tile Hard 50G and 100G IPs:

RX Alignment Market Lock o_rx_am_lock LED • Green: All 4 lanes lockedto the alignment marker.

• Red: Lanes not locked tothe alignment marker.

RX Block Lock o_rx_block_lock LED • Green: All 4 lanes lockedto the incoming 64b/66b.

• Red: Lanes not locked tothe incoming 64b/66b.


PCS Align Lock align_locked LED • Green: All 4 lanes areskew compensated andaligned. Also shows thetimestamp of lock.

• Red: Lanes are not skewcompensated and notaligned.

PCS Deskew Lock deskew_locked LED • Green: All 4 lanes arelocked for alignmentmarker. Also shows thetimestamp of lock.

• Red: Lanes are notlocked for alignmentmarker.



PCS Word Lock word_locked LED • Green: Locked fromreceiving Ethernetpackets.



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Table 17. Data Mode Status Signals


For 10GBASE-KR Intel Stratix 10 FPGA IP:

rx_block_lock Waveform Displays the behavior ofrx_block_lock in time domain.When asserted, it indicates that thelocal device is locked from receivingEthernet packets. This is a waveformrepresentation of the RX Block Locksignal in the Table 16 on page 29.

rx_data_ready Waveform Displays the behavior ofrx_data_ready in time domain. Thisrepresents a successful block lockassertion. This is a waveformrepresentation of the RX Data Readysignal in the Table 16 on page 29.

rx_hi_ber Waveform Displays if the device receives invalidsync header for more than 16 timeswithin 125 us time period, as definedin Clause 49 of the IEEE 802.3 2015Standard.


rpcs_align_locked Waveform Displays the behavior ofrpcs_align_locked in time domain.When asserted, it indicates that all 4lanes are skew compensated andaligned. This is a waveformrepresentation of the PCS Align Locksignal in the Table 16 on page 29.

rpcs_deskew_locked Waveform Displays the behavior ofrpcs_deskew_locked in timedomain. When asserted, it indicatesthat all 4 lanes are locked to alignmentmarkers. This is a waveformrepresentation of the PCS Deskew Locksignal in the Table 16 on page 29.

rx_hi_ber Waveform Displays if device receives invalid syncheader for more than 16 times within125 us time period, as defined inClause 49 of the IEEE 802.3 2015Standard.

rpcs_word_locked Waveform Displays the behavior ofrpcs_word_locked in time domain.When asserted, it indicates that thelocal device is locked from receivingEthernet packets. This is a waveformrepresentation of the PCS Word Locksignal in the Table 16 on page 29.

rx_enh_blk_lock Waveform Displays the behavior ofrx_enh_blk_lock in time domain.When asserted, it indicates that FEC islocked from receiving Ethernetpackets. This is a waveformrepresentation of the RX ENH BlockLock signal in the Table 16 on page 29.

For Intel Stratix 10 H-Tile Hard 50G and 100G IPs:continued...


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o_rx_hi_ber Waveform Displays if the local device receivesinvalid sync header for more than 16times within 125 us time period, asdefined in Clause 49 of the IEEE 802.32015 Standard.

o_rx_am_lock Waveform Displays the behavior ofo_rx_am_lock in time domain. Whenasserted, it indicates that the localdevice is locked to alignment markers.This is a waveform representation ofthe RX Alignment Marker Lock signal inthe Table 16 on page 29.

o_rx_block_lock Waveform Displays the behavior ofo_rx_block_lock in time domain.When asserted, it indicates that thelocal device is locked to the 64b/66bblocks from receiving Ethernet packets.This is a waveform representation ofthe RX Block Lock signal in the Table16 on page 29.


align_locked Waveform Displays the behavior ofalign_locked in time domain. Whenasserted, it indicates that all 4 lanesare skew compensated and aligned.This is a waveform representation ofthe PCS Align Lock signal in the Table16 on page 29.

deskew_locked Waveform Displays the behavior ofdeskew_locked in time domain.When asserted, it indicates that all 4lanes are locked to alignment markers.This is a waveform representation ofthe PCS Deskew Lock signal in the Table 16 on page 29.

rx_hi_ber Waveform Displays if device receives invalid syncheader for more than 16 times within125 us time period, as defined inClause 49 of the IEEE 802.3 2015Standard.

word_locked Waveform Displays the behavior of word_lockedin time domain. When asserted, itindicates that the local device is lockedfrom receiving Ethernet packets. Thisis a waveform representation of thePCS Word Lock signal in the Table 16on page 29.

Table 18. Device Intrinsic Signals

Note: This table displays the device internal signals used mostly for debugging purpose. ContactIntel FPGA mySupport for any questions related to these signals.


rx_is_lockedtodata Waveform Shows if clock data recover (CDR)receiver of the Local Device is locked tothe incoming data. This is different

continued...


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than rx_is_lockedtodata comingfrom CDR. This is asserted only whenCDR is locked to data for 1 ms.

rx_is_lockedtoref Waveform Shows if CDR receiver of the LocalDevice is locked to a reference clock.

Related Information

Intel FPGA mySupport

3.2.2.5. Help Tab

The Help tab provides basic guidelines on:

• Capturing Ethernet link bring-up sequence.

• General recommendations for Signal Tap Logic Analyzer configuration.


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https://www.altera.com/mal-all/mysupport.html


4. Document Revision History for the Ethernet LinkInspector User Guide for Intel Stratix 10 Devices

Document Version Intel QuartusPrime Version

Changes

2019.04.15 19.1 • Updated the document title to Ethernet Link Inspector User Guide forIntel Stratix 10 Devices.

• Renamed the topic title Downloading and Running the Ethernet LinkInspector to Running the Ethernet Link Inspector.

• Added new Topic: Creating and Capturing Signal Tap File and ExportingSignal Tap Database as CSV File.

• Updated the following Tables:— Merged content of Table: Ethernet Link Inspector Supported IP

Cores for Intel Stratix 10 E-tile Devices to Table: Ethernet LinkInspector Supported IP Cores for Intel Stratix 10 L- and H-tileDevices.

— Renamed table title from Ethernet Link Inspector Supported IPCores for Intel Stratix 10 L- and H-tile Devices to Ethernet LinkInspector Supported IP Cores for Intel Stratix 10 L-, H-, and E-tileDevices

• Updated the following topics:— Overview of Ethernet Link Inspector for Intel Stratix 10 Devices— System Requirements— Enabling Your Design For the Link Monitor— Running the Ethernet Link Inspector— Running the Link Monitor— Running the Link Analysis— Link Monitor Tabs and Settings— Data Mode Tab

Document Version Ethernet LinkInspectorVersion

Changes

2018.12.21 4.1 • Updated the document title to Ethernet Link Inspector User Guide v4.1for Intel Stratix 10 Devices.

• Updated the following topics:— Downloading and Running the Ethernet Link Inspector— Running the Link Monitor— Link Analysis Tabs and Settings

• Updated Table: Ethernet Link Inspector Supported IP Cores for IntelStratix 10 E-Tile Devices.

2018.12.04 4.0.1 • Updated the document title to Ethernet Link Inspector User Guidev4.0.1 for Intel Stratix 10 Devices.

• Updated the following topics:— Overview of Ethernet Link Inspector for Intel Stratix 10 Devices— Downloading and Running the Ethernet Link Inspector— Running the Link Monitor— Link Analysis Tabs and Settings

continued...

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Send Feedback







Document Version Ethernet LinkInspectorVersion

Changes


• Added support for the following Ethernet IP cores:— 25G Ethernet Intel FPGA IP core for Intel Stratix 10 L-, H-, and E-

Tile devices— 50G H-Tile Hard IP for Ethernet Intel FPGA IP— 50G E-Tile Hard IP for Ethernet Intel FPGA IP

• Updated the following topics:— Supported IP Cores and Devices

• Renamed Table title Ethernet Link Inspector Supported IP Coresfor Intel Stratix 10 Devices to Ethernet Link Inspector SupportedIP Cores for Intel Stratix 10 L- and H-Tile Devices.

• Added a new Table: Ethernet Link Inspector Supported IP Coresfor Intel Stratix 10 E-Tile Devices.

— Downloading and Running the Ethernet Link Inspector for IntelStratix 10 Devices• Updated Table: Command Parameters.

— Link Monitor Tabs and Settings• Renamed Table title Ethernet Link Monitor Toolkit GUI Tabs to

Link Monitor GUI Tabs and updated the table.— Sequencer State Machine

• Updated Table: SSM State Descriptions.— Link Analysis Tabs and Settings— Link Training Tab

• Updated Table title Data Mode Status Signals to Link TrainingStatus Signals.

— Data Mode Tab• Updated Tables: Local Device Status Signals, Remote Device

Status Signals, and Link Training Status Signals.• Updated the following Figures:

— Removed Figures: Example MAC & PHY Tab, Statistics Counters Tab,and KR/KR4.

— Added new Figures: Example MAC & PCS Tab, Example StatisticsCounters Tab, and Example KR4 Tab.

— Updated Figures: Flowchart of SSM States and Flowchart of ANArbiter State Machine.

• Restructured the Running the Link Analysis and Running the LinkMonitor content in the Downloading and Running the Ethernet LinkInspector section into individual topics.

• Made minor editorial updates to the document.


• Updated Table: Ethernet Link Inspector Supported IP Cores for IntelStratix 10 Devices to add a new variant support for E-Tile Hard IP forEthernet Intel FPGA IP for 100G PAM4.

• Updated topics:— Downloading and Running the Ethernet Link Inspector for Intel

Stratix 10 Devices— Link Analysis Tabs and Settings

• Removed Table: Ethernet IP Core Support for Ethernet Link MonitorToolkit GUI Tabs.

• Made minor editorial updates.

2018.07.06 2.0 Initial release.

4. Document Revision History for the Ethernet Link Inspector User Guide for Intel Stratix 10Devices

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Documents

Ethernet Link Inspector User Guide for Intel® Stratix® 10 ... · Design examples generated in Intel Quartus Prime Pro Edition software are instantiated with JTAG to Avalon Master