Ethernet BomberStand-Alone / PCI-E controlled Ethernet

Packet Generator

Oren Novitzky & Rony Setter

Advisor: Mony Orbach

Spring 2008 – Winter 2009Spring 2008 – Winter 2009

Characterization PresentationCharacterization Presentation

Contents

General description

Project goals

System description

Top level block diagram

HW and SW requirements

Project millstone

General Description

The demand for effective, real-time

Ethernet monitoring and analysis

devices requires a high-speed HW

implemented Ethernet packet generator

(“Bomber”).

Project Goals

Developing a hardware Ethernet packet

generator and transmitter for Ethernet

network and devices testing.

Support Stand-alone operation mode

(PCI-E controlled – Optional).

Implementation of the system on Altera

PCI-E Development kit board with

Stratix II GX FPGA.

Project Goals

Learning common communication

protocols such as Ethernet, UDP, IP

Learning HW development language

(VHDL)

System Description

Network BomberEthernet

PC

PCI-E

optional

Stand Alone operation mode:

Generating and transmitting

Ethernet packets.

Configuration through

Ethernet protocol as well.

Configuration

through PCI-E

Top Level Block Diagram

FPGAUDP/IP Packet generator

NIOS IICore

PayloadData base

PHYMarvell

External Ethernet 10/100 Mbps

MII

RJ-4

5

Ethernet MAC

Altera MegaFunc

PCI-E interface – 2.5 Gb/s Altera MegaFunc

(optional)

Creating UDP/IP packets in Transport/Network layers .Implementation with NIOS II Core, using FPGA memory. External memory usage necessity is to be examined.

Creating Ethernet packets in Datalink layerImplementation with Altera Mega function Ethernet MAC

Sending packets through Marvell Physical layer (board Hw)Using RJ-45 connector for twisted pair

Optional implementation of PCI-E interface for configuration purpose only.

HW & SW Tools

SW:Quartus II – Altera

Nios II – Altera

SoPC Builder - Altera

Megacore-IP library - Altera

HDL-Designer

HW: PCIe Development Board - Altera

Project Milestones

Week

characterizing project

Top level Design and connectivity

Detailed design , sub-unit block diagram

Detailed characterization i.e. transfer speed, memory usage, configuration method etc.

Thorough Learning of relevant network protocols (Ethernet, UDP, IP)

Learning and exercising working environment

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