ETE 204 - Digital Electronics Flip-Flops and Registers
[Lecture:13] Instructor: Sajib Roy Lecturer, ETE, ULAB
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Flip-Flops (continued) Summer 2012ETE 204 - Digital
Electronics2
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SR Flip-Flop The SR Flip-Flop has three inputs - Clock (Ck) ---
denoted by the small arrowhead - Set (S) and Reset (R) Similar to
an SR Latch - S = 1 sets the flip-flop (Q + = 1) - R = 1 resets the
flip-flop (Q + = 0) Like the D Flip-Flop, the Q output of an SR
Flip-Flop only changes in response to an active clock edge. -
Positive edge-triggered - Negative edge-triggered 3Summer 2012ETE
204 - Digital Electronics
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SR Flip-Flop SRQ Q+Q+ 0 0 0101 0101 10101010 0 1 0 1010
01110111 }}}}}} Q + = Q store Q + = 0 reset Q + = 1 set positive
edge-triggered SR Flip-Flop 1 10not 111allowed State change occurs
after active Clock edge 4Summer 2012ETE 204 - Digital
Electronics
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SR Flip-Flop (master-slave) SR Latches Enabled on opposite
levels of the clock 5Summer 2012ETE 204 - Digital Electronics
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SR Flip-Flop: Timing Diagram 6Summer 2012ETE 204 - Digital
Electronics
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JK Flip-Flop The JK Flip-Flop has three inputs - Clock (Ck) ---
denoted by the small arrowhead - J and K Similar to the SR
Flip-Flop - J corresponds to S: J = 1 Q + = 1 K corresponds to R: K
= 1 Q + = 0 Different from the SR Flip-Flop in that the input
combination J = 1, K = 1 is allowed. - J = K = 1 causes the Q
output to toggle after an active clock edge. 7Summer 2012ETE 204 -
Digital Electronics
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JK Flip-Flop }}}}}}}} Q + = Q store Q + = 0 reset Q + = 1 set
Characteristic Equation: Q + = J.Q' + K'.Q Q + = Q' toggle 8Summer
2012ETE 204 - Digital Electronics
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JK Flip-Flop (master-slave) SR Latches Enabled on opposite
levels of the clock 9Summer 2012ETE 204 - Digital Electronics
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JK Flip-Flop: Timing Diagram 10Summer 2012ETE 204 - Digital
Electronics
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T Flip-Flop The Toggle (T) Flip-Flop has two inputs - Clock
(Ck) --- denoted by the small arrowhead - Toggle (T) The T input
controls the state change - when T = 0, the state does not change
(Q + = Q) - when T = 1, the state changes following an active clock
edge (Q + = Q') T Flip-Flops are often used in the design of
counters. 11Summer 2012ETE 204 - Digital Electronics
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T Flip-Flop Characteristic Equation: Q + = T.Q' + T'.Q = T xor
Q 12Summer 2012ETE 204 - Digital Electronics
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T Flip-Flop: Timing Diagram 13Summer 2012ETE 204 - Digital
Electronics
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Building a T Flip-Flop 14Summer 2012ETE 204 - Digital
Electronics
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Asynchronous Control Signals 15Summer 2012ETE 204 - Digital
Electronics
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Asynchronous Control Signals: Timing Diagram 16Summer 2012ETE
204 - Digital Electronics
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D FF with Clock Enable 17Summer 2012ETE 204 - Digital
Electronics
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Registers 18Summer 2012ETE 204 - Digital Electronics
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Registers Several D flip-flops may be grouped together with a
common clock to form a register. Because each flip-flop can store
one bit of information, a register with n D flip-flops can store n
bits of information. A load signal can be ANDed with the clock to
enable and disable loading the registers. A better approach is to
use registers with clock enables if they are available. 19Summer
2012ETE 204 - Digital Electronics
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Register: 4 bits 20Summer 2012ETE 204 - Digital
Electronics
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Data Transfer between Registers Data transfer between registers
is a common operation in computer (i.e. digital) systems. Multiple
registers can be interconnected using tri-state buffers. Data can
be transferred between two registers by enabling the proper
tri-state buffer. 21Summer 2012ETE 204 - Digital Electronics
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Data Transfer between Registers 22Summer 2012ETE 204 - Digital
Electronics
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Register with Tri-state Output 23Summer 2012ETE 204 - Digital
Electronics
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Data Transfer using Tri-state Bus 24Summer 2012ETE 204 -
Digital Electronics
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Shift Register A shift register is a register in which binary
data can be stored and shifted either left or right. The data is
shifted according to the applied shift signal; often there is a
left shift signal and a right shift signal. A shift register must
be constructed using flip-flops (i.e. edge- triggered devices); it
cannot be constructed using latches or gated-latches (i.e.
level-sensitive devices). 25Summer 2012ETE 204 - Digital
Electronics
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Shift Register: 4 bits 26Summer 2012ETE 204 - Digital
Electronics
8-bit SI SO Shift Register 28Summer 2012ETE 204 - Digital
Electronics
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4-bit PIPO Shift Register 29Summer 2012ETE 204 - Digital
Electronics
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4-bit PI PO Shift Register: Operation 30Summer 2012ETE 204 -
Digital Electronics
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Parallel Adder with Accumulator 31Summer 2012ETE 204 - Digital
Electronics
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Parallel Adder with Accumulator In computer circuits, it is
frequently desirable to store one number in a register (called an
accumulator) and add a second number to it, leaving the result
stored in the register. 32Summer 2012ETE 204 - Digital
Electronics
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n-bit Parallel Adder with Accumulator 33Summer 2012ETE 204 -
Digital Electronics
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Loading the Accumulator Before addition in the previous circuit
can take place, the accumulator must be loaded with X. This can be
accomplished in several ways. The easiest way is to first clear the
accumulator using the asynchronous clear inputs on the flip-flops,
and then put the X data on the Y inputs to the adder and add the
accumulator in the normal way. Alternatively, we could add
multiplexers at the accumulator inputs so that we could select
either the Y input data or the adder output to load into the
accumulator. 34Summer 2012ETE 204 - Digital Electronics
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Adder Cell with Multiplexer 35Summer 2012ETE 204 - Digital
Electronics
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Questions? 36Summer 2012ETE 204 - Digital Electronics