ESD PROTECTION FOR RF/AMS ICs - IEEE @ UCR Laboratory for Integrated Circuits and Systems • RF/Mixed-Signal/Analog IC & SoC • On-Chip ESD Protection for ICs • IC CAD & Modeling

ESD PROTECTION FOR RF/AMS ICs

April 25, 2008Prof. Albert Wang

Dept of Electrical EngineeringDept. of Electrical EngineeringUniversity of California

417 EBU2 Riverside CA 92521 Email: aw@ee ucr edu417 EBU2, Riverside, CA 92521 Email: [email protected]: (951) 827-2555 http://www.ee.ucr.edu/~aw Fax: (951) 827-2425 Lab: http://lics.ee.ucr.edu

Copyright © 2008 by Albert Wang, All Rights Reserved

LICS @ UCRLaboratory for Integrated Circuits and Systems

• RF/Mixed-Signal/Analog IC & SoC

• On-Chip ESD Protection for ICs

• IC CAD & Modeling

S i d t D i• Semiconductor Devices

1© Prof. Albert Wang/UCR - IEEE Phoenix, 04/25/2008

RECENT RESEARCH PROJECTSRECENT RESEARCH PROJECTSProjects:* Low-parasitic hi-robust ESD protection for RF/AMS ICs* Super compact ESD protection* 3D ESD protection simulation-design methodology* 3D hi-I electro-thermal ESD device modeling* ESDcat – whole-chip ESD design synthesis & verification CAD* ESD protection for nano technology

* Multi-mode CMOS RF transceiver ICs* Gbps full-band carrier-free impulse 1-UWB SoC* On-Si antenna for UWB* 24GHz RFID with on-chip antenna* Transistor-size M-cored inductors for CMOS RF SoCTransistor-size M-cored inductors for CMOS RF SoC* RF-ESD co-design methodology* New PA circuit model* Modeling & CAD for electro-magnetic devices

* Precision bandgap reference IC in CMOS/BiCMOSPrecision bandgap reference IC in CMOS/BiCMOS* Resolution/sampling/power-optimized ADC in SiGe BiCMOS* Low-power multi-Gsps ADC in CMOS

Sponsors:* N ti l S i F d ti

Lots of joint designs with companies.We use industrial design flows.W d li kin Si n t just p ts


* National Science Foundation* SRC, AKM, RF Integrated Corp., National Semiconductor, ESD Association, Mektronix,

Synopsys, Agilent, Skyworks, SMIC, GSMC, etc.

We deliver working Si, not just reports.

OutlinesOutlines

• Basics on ESD Protection

• Mixed-Mode ESD Simulation-Design Methodg

• RF ESD Protection Circuit Design

• ESD+RF IC Co-Design

• Summary


A Multi-Billion-$ Problem!A Multi Billion $ Problem!

• ESD = Electrostatic Dischargeg• Phenomena: huge I/V-pulses⇒ IC damages!

• A multi-billion-$ problem• ESD failures → 30%-50% IC failures• A killing factor to time-to-marketA killing factor to time to market

on-chip ESD protection required!

Informal ESD Failure Statistics

Electrica... Good 4%Ion 3%

Assembly14%

Unknown15%

Fab26%

Ref: L. Brown, et al, Electronic Packaging & Production, April 1990.

26%

ESD/EOS37%


g g pR. Merril, et al, EOS/ESD, 1993.

37%

ESD Testing StandardsESD Testing Standards

• HBM - human body model.• MM - machine modelMM machine model.• CDM - charged device model.

IEC• IEC - International Electrotechnical Commission

TLP t i i li l d l• TLP - transmission line pulse model• etc….


HBM Test ModelMIL STD 883E M th d 3015 7MIL-STD-883E, Method 3015.7

3

MIL-STD-883E

RESDR0 S1

MIL-STD-883E

L=0

LESD=15uHLESD=15uH

LESD=0HIp

90%

100%HV

Supply DUT

CESDVESD+-

A

B2

SD (A

)

L7.5uH/Cs1p/RL500/CL30pLESD=7.5uH, Cs=1pF, RL=500Ohm, CL=30pF

R0 106 – 107 Ω

RESD 1500Ω

1

I ES

DUT

RESD LESDS1 A

)(2

)( 21

20

2

tStS

ESD

ESDESD ee

L

Vti −

−=

ωα

CESD 100pF ±1%

10%

CESD

VESD

+

- B

0ESD


00E+0 2E-7 4E-7 6E-7 8E-7 1E-6

t (s)

td

ESD Protection BasicsESD Protection Basics

Various ESD protection solutions:• Advanced package solutions.p g• Buffers using new anti-ESD materials.• Surge protection devices on boardg p• etc.

On-Chip ESD protection i it f ll I/O f IC hi


circuitry for all I/Os of IC chips.

ESD Failure & ProtectionESD Failure & Protection

• Two types of ESD damages:• Thermal damage: heating in Si/metal ← high currents• Dielectric rupture ← high electric field ← high voltage• Dielectric rupture ← high electric field ← high voltage

• Two ESD protection principles:• To discharge hi-current safely,• To clamp pad voltage to a sufficiently low level.


ESD Protection MechanismsESD Protection Mechanisms

• Simple turn-on I-V, PDVDD

NDp ,• Snapback I-V.• Protect EVERY I/O pad on chip!

PD

I/O DS I

2nd Breakdown IPS

NSVSS

I (Vt2, It2)

(ESD protection region)

I

Low-R discharge (ESD protection region)

(Vt1 It1 t1)(Vh, Ih) Triggering

Holding

Low-R discharge

Turn on (Vt1, It1, t1)

V

(Vt1, It1, t1)

V

ESD iti l t th KEY t ESD i it d i t ti !

9© Prof. Albert Wang/UCR - IEEE Phoenix, 04/25/2008Ref.: A. Wang, On-Chip ESD Protection for Integrated Circuits, Kluwer, ISBN: 0-7923-7647-1, 2002.

ESD-critical parameters are the KEY to ESD circuit design protection!

Basic ESD ProtectionBasic ESD Protection

• Diodes• Bipolar transistorsBipolar transistors• MOSFET

SCR• SCR• Other novel/exotic structures


ESD Protection: Simple or Complex?!ESD Protection: Simple or Complex?!VDD

VDD

VSS

A

I/OVSSND

PDQ1

I

R2

I/O

VSS

PD

Q2

IDz

Rext

DZ

K

ext


VSSVSS

NSPS

Ref: J. Chen, et al, IEEE IEDM Digest, 1995, pp. 337-340; Ker, et al, US Patent 5,572,394, 1996.

Emerging Challenges in ESD DesignEmerging Challenges in ESD Design

• Design prediction by simulation

• Design optimization by simulation

• 3D ESD protection device modeling

• Whole-chip ESD design theory and methodology

• CAD algorithm & tools for ESD synthesis and verification

• ESD protection circuitry for RF/AMS ICs

• RF-ESD co-design method

• ESD protection for nano technologies


Mixed-Mode ESD Simulation-DesignMixed Mode ESD Simulation Design

2D/3D Mi d M d ESD Si l ti D i M th d l• 2D/3D Mixed-Mode ESD Simulation-Design Methodology:Electro-thermal-process-device-circuit-layout couplingStatic-transient ESD simulation

⇒ ESD design optimization, no trial-and-error!no over/under-design!

⇒ Forward ESD design, not backward analysis!⇒ Compact ESD protection designs⇒ Minimize ESD-induced parasitic effects⇒ Minimize ESD induced parasitic effects⇒ Explore novel ESD structures


Ref: A. Wang, et al, IEEE Trans Elec. Devs., v52, n7, p1304, 2005.

H. Feng, et al, IEEE JSSC, v38, n6, p995, 2003.

H. Xie, MS Thesis, IIT, 2004.

ESD Design Method: New ~ OldESD Design Method: New Old

N A h

Experience

TraditionalESD specs

New Approach

Isolated SIM(device or circuit)

Mixed-mode SIM(device + circuit)

Full ESD simulation

ESD design

Silicons Silicon

ESD design

Si w/ ConfidenceSilicons

Debug

iterationsSi w/ Confidence

Measurement


Goal: 1st Si Success!

Mixed-Mode ESD Design PrincipleMixed Mode ESD Design Principle

• Chip-level ESD circuit design• No-assumptions• Freeze-up your rich experiences for a while

Cs

Core ICChip

VHBM

CC

Ct

RdLs ESDCircuit

t

ESD source circuit( HBM d l)

ESD sub-circuit


(e.g., HBM model) to be simulated

Example-1: NMOS ESD DesignsExample 1: NMOS ESD Designs

• ggNMOS ⇒ gcNMOS

R 1 5K L=10uH

HBM Model

IC

R=1.5K L 10uH

C1=0.1pF

C=100pF

R1=10K


Example-1: ggNMOS ~ gcNMOS ESD4

1.4

2

3

nt (A

mp)

0.8

1

1.2

1.4

)

0

1

2

Cur

ren

0.2

0.4

0.6

0.8

I(A

00.E+00 2.E-07 4.E-07 6.E-07 8.E-07 1.E-06 1.E-06

Time (Second)0

0

0 5 10 15 20V(v)20

10

15

V(V)

0

5


01.E-12 1.E-11 1.E-10 1.E-09 1.E-08 1.E-07 1.E-06 1.E-05

t(s)

1.5 4

Example-1: ggNMOS ~ gcNMOS ESD

1

d(A

)

2

2.5

3

3.5

(V)

0

0.5

Id

0

0.5

1

1.5Vg(

00 5 10 15 20

Vd(V)

-0.51.E-14 1.E-12 1.E-10 1.E-08 1.E-06

log(t) (s)

20

10

15

Vd(V

)

To reduce triggering Vt1 by design

0

5


1.E-12 1.E-10 1.E-08 1.E-06 1.E-04 1.E-02log(t) (s)

Example-1: ggNMOS ~ gcNMOS ESD

GGNMOS GCNMOS

Example 1: ggNMOS gcNMOS ESD

GGNMOS GCNMOS

SIM. TEST SIM. TEST

Vt1(V) 14.68 12.56 7.54 6.66

t1(ns) 0.2 - 0.42 -

Vh(V) 6.92 6.48 7.41 6.08

VG(V) - - 3.67 -( )

tG (ns) - - 0.32 -

Triggering V reduced successfully


Triggering Vt1 reduced successfully,

Good design prediction and 1st Si success.

RF ESD Protection DesignRF ESD Protection Design

Wh t’ U i f RF ESD t ti ?!• What’s Unique for RF ESD protection?!– RF IC is sensitive to ESD-induced parasitic effects– Need accurate RF ESD characterization– Low-parasitic compact RF ESD protection design – Whole-chip ESD protection circuit design concept

• New & Critical: ESD Circuit Interactions• New & Critical: ESD-Circuit Interactions– ESD-to-Circuit Influences– Circuit-to-ESD Influences

RF ESD d i• RF+ESD co-design

Ref: A. Wang, et al, invited, IEEE Proc. CICC, 2002, pp411-418.


A. Wang, et al, invited, Proc. IEEE RFIC 2008.

Circuit-to-ESD InfluencesCircuit to ESD Influences

• ESD protection may be affected by the core circuits:– Weak discharge links in core IC ⇒ Early ESD Failure.

ESD unit triggers upon ESD pulses & stays OFF otherwise– ESD unit triggers upon ESD pulses & stays OFF otherwise,

– dV/dt, dI/dt effects contribute to ESD triggering,

– Fast RF and M-S signals may trigger ESD units ACCIDENTLY

Unique Challenge 1: q g

ESD Mis-Triggering by RF signals.


ESD Parasitics: CESDESD Parasitics: CESD

• Circuit performance may be affected by ESD circuitry:– ESD-induced parasitic CESD (up to ~pF) & RESD,

– CESD RESD delay ⇒ signal integrity, clock corruption, …

– CESD ⇒ loading effect, Z-matching, power efficiency, BW, …

– ΔCESD ΔRESD ~ frequency biasing temperatureΔCESD, ΔRESD frequency, biasing, temperature, …

Unique Challenge 2: Accurate CESD estimation,Including CESD in RF IC design,Reduce ΔC over Δf


Reduce ΔCESD over ΔfRF

ESD Parasitics: NoisesESD Parasitics: Noises

• Substrate noise coupling effect due to CESD:Substrate noise coupling effect due to CESD:– Incident noises at I/O coupled into substrate,

– Substrate noises ⇒ I/O ⇒ signal path

I/O• ESD self-generated noises:

– Thermal noises,

CESD– Flicker noises,

– Shot noises, etc.

Unique Challenge 3: ESD noises into RF ICs


ESD noises into RF ICs.

Mixed-Signal ESD ProtectionMixed Signal ESD Protection

• No global ESD solutions!• No one Vt1 fits the whole chip!• Multi-VDD/VSS ⇒ locally-optimized Vt1 for different I/Os,DD SS y p m t1 f ff ,• Need a safety margin for Vt1:

Vt1 of 5V fits VDD=3.3V blocks,V of 23V good for V =15V blocks

Challenge 4: multi-V ESD design in RF/AMS ICs

Vt1 of 23V good for VDD=15V blocks.

Challenge 4: multi-Vt1 ESD design in RF/AMS ICs⇒ whole-chip ESD design optimization,⇒ on-chip local ESD design optimization


p E D g p m z

Circuit-to-ESD InfluencesCircuit-to-ESD Influences• Observation in TLP testing of ESD structures:

– ggNMOS, dSCR ESD structures, etc.

– TLP pulse tr ≈0.2~20ns,

Strong V ~ t correlation

D

G BC

40NMOS-1

– Strong Vt1~ tr correlation,

– tr ⇒ Vt1

G

SR

20

30

)

OSNMOS-2NMOS-3dSCR-1dSCR-2dSCR-3

G DB S VDD

dV/dt

0

10Vt1

(V

N+N+P+

n-Wel

n-Well

R


00.1 1 10 100

tr (ns)p-Well

ll R

Isub

CESD

Example-3: ESD-Protected RF IC Designp g

ESD affects RF IC substantially:• 5GHz LNA for dual-band WLAN transceiver

– CE-CB cascode topology– High/low gain switching– Unique double shutdown function

• 0.18μm SiGe BiCMOS • 2KV ESD protection

G GS

ESDESD

GSG

RFIN

SG R

FOU

T


Ref.: G. Chen, et al, Proc. IEEE EMC, 2005.

Example-3: LNA Noise ~ ESDExample 3: LNA Noise ESD

LNA S (dB) S (dB) NF(dB)

NF

circuits S21(dB) S11(dB) NF(dB)

w/o ESD 18.11 -8.3 2.99

with ESD 15.08 -7.2 3.19

3 5

4

4.5

5

Degradation 16.73% 17.25% 6.8%

2

2.5

3

3.5

NF

(dB

) LNA w/ ESD LNA w/o ESD

NF: ESD deviceLNA

ESDTotal GFFF 1−

+=

0.5

1

1.5

NFESD ≥ 0.1 dB

ESDG


04.5 5 5.5 6 6.5 7

Frequency (GHz)

Reference-1: 2 4GHz LNA+ESDReference 1: 2.4GHz LNA+ESD

ESD modeled by Cp = CESD + CBP ??

External Lg & Cb to tune 50Ω matching?!

Still show big LNA degradation!!LNA

0.15μm CMOSf0 (GHz) NF (dB) S21 (dB) S11 (dB) S22 (dB)

2kV Diode ESD 2.46 2.36 14 -18.5 -15.5

g g


No ESD 2.4 2.77 12.1 -19 -20.7

Ref.: Chandrasekhar, et al, Proc. IEEE ESSCIRC, p347, 2002.

Reference-2: 5.5GHz LNA+ESDReference 2: 5.5GHz LNA+ESD

5.5GHz LNA5.5GHz LNA

2kV ESD

90nm CMOS

LESD = 3nHESD

Lg =4.3nH

Ls =0.4nH

RESD = ?

3-5GHz UWB LNA

6.5kV ESDESD

0.35μm CMOS

CPAD + CESD = 300fF

These ideal models do NOT work!


Ref.: Linten, et al, IEEE Journal of Solid-State Circuits, p1434, July, 2005.

Liu, et al, IEEE Trans. MTT, V54, N4, p1698, April 2006.

No co-design for RF optimization!

Reference Design 2: 5.5GHz LNA+ESDReference Design 2: 5.5GHz LNA+ESD

90nm f0 (GHz) NF (dB) S21 (dB) S11 (dB) S22 (dB)

No ESD 5.5 2.7 12.3 -10.3 -19

L-ESD 5.5?! 2.95 13.3 -14.4 -19?!

“…without altering anything to original core LNA design….”?!


“No significant degradation of core LNA RF performance…”?!

Ref.: Linten, et al, IEEE Journal of Solid-State Circuits, p1434, July, 2005.

RF ESD Design CharacterizationRF ESD Design Characterization

• Comprehensive & accurate RF ESD characterization:p– S-parameter measurement,– Noise measurement,

Q f t ? Q 1=– Q-factor?

– Critically affect I/O z-matching of RF ICs!– Never trust foundry ESD models yet!

ESDESDRfCQ

π2=

y y


Ref.: G. Chen, et al, Proc. IEEE RFIC Symp., pp347, 2003.

Wang, et al, IEEE Trans ED, V52, N7, p1304, 2005.

Example-4: RF ESD CharacterizationExample 4: RF ESD Characterization

• Most commonly ESD protection structures

– ggMOS– SCRSCR– dSCR– Diode string: Dx1, Dx2, Dx3, Dx4, Dx5, … Dxn

• Designed and fabricated in 0.35μm BiCMOS

• 2kV/5kV ESD protection

• Design optimization by mixed-mode ESD simulation

• Simulation matches measurement very well


Example-4: 2kV CESD by SIM & TestExample 4: 2kV CESD by SIM & Test1

Simulation

0.6

0.8

D (p

F)

SCR ggNMOSDx1Dx2dSCR

0.2

0.4CES

D

0 6

0.8 SCR ggNMOSDx1Dx2D 3

00 2 4 6 8 10

f (GHz)0.4

0.6

CESD (p

F)

Dx3Dx4Dx5dSCR

0.2

C

Measurement


00 2 4 6 8 10

f (GHz)

Example-4: 2kV CESD by Testp ESD y0.1 SCR

Dx1

0.08

Dx1Dx2Dx3Dx4

0.06

D(p

F)

Dx4Dx5dSCR

0.04C ESD

0.02


00 2 4 6 8 10f (GHz)

Example-4: 2kV CESD ~ Size

2000

2500

2kV Layout Size Comparison

1000

1500

yout

Siz

e (u

m2)

0.45

2kV CESD Comparison at 2.4GHz

0

500

Lay

Dx1 Dx2 Dx3 Dx4 Dx5 ggNMOS SCR dSCR

0 25

0.3

0.35

0.4

0.45

pF)

ESD Structures

0 05

0.1

0.15

0.2

0.25

CES

D (p


0

0.05

Dx1 Dx2 Dx3 Dx4 Dx5 ggNMOS SCR dSCRESD Structures

FoM for Overall ESD Design EvaluationFoM for Overall ESD Design Evaluation

• Each parameter has different/conflicting meaning,p g g,• Optimization by overall ESD design performance,• Need a new FoM parameter: F-factor

kV)()()( 2 dBNFpFCmSize

kVFESD ××

=μ

2kV F-Factor Comparison (Measured)

150

200

50

100

F-fa

ctor


0Dx1 Dx2 Dx3 Dx4 Dx5 ggNMOS SCR dSCR

ESD Structures

Example-4: Give me the NumbersExample 4: Give me the Numbers

• Extracted testing data at 2.4GHz,• Optimized ESD design by simulation for min-size, min-parasitics,• Some ESD designs just not good for RF ICs,• Trial-and-error designs and “rich” experiences do not work here!

ESD Dx1 Dx2 Dx3 Dx4 Dx5 ggNMOS SCR dSCR

You still have to integrate ESD into RF IC designs!!

gg

CESD (fF) 48.7 26.3 16.3 18.7 21.0 448.3 66.6 42.4

Size (μm2)506 956 1405 1855 2305 1433 396 257


F (V/μm2 pF) 79.4 88.1 88.1 60.6 44.1 3.1 75.0 180.4

RF ESD PROTECTION SOLUTIONSRF ESD PROTECTION SOLUTIONS

N ll fit RF ESD t ti d i !• No all-fit RF ESD protection design!• Any ESD protection ⇒ RF ESD

given ESD Circuit interactions ↓↓↓given ESD-Circuit interactions ↓↓↓

Goal for RF ESD ⇒ ANY NOVEL structures:oUltra-fast ESD switching,oNovel triggering mechanisms,gg g ,oHi-ESDV/Si ratio,oSmall size,oLow-parasitics,


oLow parasitics,oMultiple-mode ESD protection, ……

Novel ESD Protection Design HelpsNovel ESD Protection Design HelpsVDD VDD

VDD ND/PD

ND PD ND PD

INSD DS

ND/PD

S/ S

DS/SD

OUT

PSNS

DSPS NS

IN

NS/PSNS/PS

VSS

V V


VSS VSS

Example-5: A Dual-Direction ESD 1 5E 02

5.0E-03

1.0E-02

1.5E-02

-5.0E-03

0.0E+00-30 -20 -10 0 10 20 30

urre

nt D

ensi

ty (A

/um

)

Voltage (V)

1 E 081 00

-1.5E-02

-1.0E-02

C

1.E-09

1.E-08

0.80

1.00

A)

Snapback I-V (left scale)

N+ P+N+P+

AK

1.E-10

0.40

0.60

log(

Ileak

)(A

I (A

) Leakage-I (right scale)

N P+

p well

NP+

Q2R1

pw

Q3R2

nwnw nw1.E-11

0.20


p-well

N-isoQ1

pw

R3R4

Ref.: Wang, et al, US Patent No. 6,365,924, 2002.

1.E-120.000 5 10 15 20 25 30

V(V)

Example-6: All-Mode SCR ESD Protection

P+N-P+

ACK

031

(PD)

P+N-P+

CK

A

42

0(ND)

34N-Epi

P-wellPW

Q41

Q5

2Rw

N-Epi

P-wellPW

Q41

Q6

3Rw

34

C

0A

KAK KA1 2

P+N-P+

P-wellPWQ2Rw

01(PS)

P+N-P+

P-wellPWQ3Rw

20(NS)


N-Epi Q1N-Epi

P wellPW

Q1

w

Ref: A. Wang, et al, IEEE Electron Device Letters, Vol. 22, No. 10, pp.493-495, Oct. 2001.A. Wang, US Patent # 6,635,931 B1, 2003.

Example-7: Low-Parasitic Poly-Si SCR ESD Excellent Prediction Excellent Prediction

• 0.35μm SiGe BiCMOS.• 3 2kV HBM ESD protection level

2.5

3

Simulation

TLP T ti3.2kV HBM ESD protection level using a small 750μm2 poly-Si SCR

• a high F-factor of 42 • the lowest reported CESD of ~92.3fF.• Ajustable Vt1.

1.5

2

(Ano

de) (

A)

TLP Testing

0.5

1

I (2 5

3

3.5

4

A)

00 5 10 15 20 25

V (Anode) (V)

1

1.5

2

2.5

I (A

node

) (A

Poly DiodePoly SCR_1Poly SCR_2

S

Cathode Anode

N+ P+ N+ P+

Polysilicon

0

0.5

0 5 10 15 20 25 30 35 40

V (Anode) (V)

Poly SCR_3Poly SCR_4

N+ P+

I3

N+ P+

P4 N5 N2 P1

R2

D

Q1 (N

ot to

Sca

le)


( ) ( )Q2 R1

Field Oxide

P-Substrate

Xie, et al, “A New Low-Parasitic Polysilicon SCR ESD Protection Structure for RF ICs”,

IEEE Electron Device Letters, Vol. 26, No.2, pp.121-123, February 2005

Example 7: Design SplitsExample-7: Design Splits

Structures SRC_1 SCR_2 SCR_3 SCR_4 Diode

W (μm) 75 75 30 75 150

Dimensions

(μ )

N+ Length (μm) 2.3 2.3 2.3 2.3 3.0

P+ Length (μm) 1.6 1.6 1.6 1.6 3.0

S ( ) 0 8 2 4 0 8 0 0 8S (μm) 0.8 2.4 0.8 0 0.8

Measurements

Vt1 (V) 11.0 15.0 11.0 9.0 -

Vh (V) 5.5 9.6 5.4 5.0 -Measurements

Vt2 (V) 15.5 15.3 13.8 20.00 13.5

It2 (A) 2.1 1.4 1.5 2.8 1.1


Full-Chip ESD Protection Scheme-1Full Chip ESD Protection Scheme 1

• Full-chip ESD protection principles:p p p p• Set up a low-R discharging path between ANY two pads,• Estimate Ron in the longest path – worst case,• Solution 1: V• A pad + clamp scheme ⇒ ⇐

VCCVCC1 VCC26 7

⇒

⇒

⇒

Pad 1 Pad 2

1 3

5

⇒

⇒

2 4

f S


⇐ ⇒ VSS VSS2 VSS1 8 9

Ref: H. Feng, MS Thesis, IIT, 2001.

Full-Chip ESD Protection Scheme-2Full Chip ESD Protection Scheme 2

• Using a common ESD discharging path• Using a common ESD discharging path,

⇔

V

⇔

Pad 2Pad 1

VSS1

⇔

⇔

Core IC ⇔

VCC1


Global ESD Bus Ref: H. Feng, MS Thesis, IIT, 2001.

New ESD+RFIC Co-Design MethodNew ESD+RFIC Co-Design Method

ESD i d d iti i BIG d l t RF IC d i It t thESD-induced parasitics is a BIG deal to RF IC design. It corrupts the critical RF I/O matching and causes RF IC performance degradation,

Foundry-provided ESD structures are generally not optimized for minimized parasitics and sizes,

Don’t trust the so-called ESD SPICE models and parameters provided by foundries yet,

Using the foundry ESD model in RF simulation shows NO effect; but testing shows substantial specs shift from post-simulationtesting shows substantial specs shift from post-simulation.

New ESD-RFIC co-design method is critical to ESD protected RFIC designs.

Sorry, due to IEEE copy right rules, slides for the new ESD-RFIC Co-Design Method and related examples cannot be disclosed here until after it is presented at IEEE RFIC in June 2008. please go to the RFIC08 Proceedings for details


Proceedings for details.

Ref. Wang, et al, “ESD-RFIC co-design methodology”, invited, IEEE Proc. RFIC, 2008.

SummarySummary

• ESD failure is a killing factor to ICs,

• On-chip ESD protection required for ICs,

• RF/AMS ESD design is very challenging,

• ESD affects RF IC performance significantly:

RF ESD design optimization for minimum parasitics,

RF ESD design characterization is critical,

RF+ESD co-design is important & feasible!RF+ESD co-design is important & feasible!

• CMD ESD design is extremely challenging

• ESD design prediction by mixed-mode simulation


ESD design prediction by mixed mode simulation

REFERENCESREFERENCES• Wang, et al, “ESD-RFIC co-design methodology”, invited, IEEE Proc. RFIC, 2008• A. Wang, et al, “A Review on RF ESD Protection Design”, IEEE Trans. Electron Devices, V2, N7, p.1304, July 2005.• H. Xie, et al, “A New Low-Parasitic Polysilicon SCR ESD Protection Structure for RF ICs”, IEEE Electron Device Letters,

V26, N2, p.121, February 2005.• R. Zhan, et al, “ESDInspector: A New Layout-level ESD Protection Circuitry Design Verification Tool Using A Smart-

Parametric Checking Mechanism”, IEEE Trans on CAD of Integrated Circuits and Systems, V23, N10, p.1421, Oct. 2004.• G. Chen, et al, “Characterizing Diodes For RF ESD Protection”, IEEE Electron Device Letters, V25, N5, p.323, May 2004. , , g , , , , p , y• A. Wang, On-Chip ESD Protection For Integrated Circuits, Kluwer Academic Publishers, Boston, ISBN: 0-7923-7647-1,

2002.• A. Wang, et al, “ESD Protection Design for RF Integrated Circuits: New Challenges”, Invited, IEEE CICC, p.411, 2002. • A. Wang, “A Study of Parasitic Effects of ESD Protection on RF ICs”, IEEE Trans. Microwave Theory & Tech., V50, N1,

p.393, Jan. 2002.• H Feng et al “A Mixed-Mode ESD Protection Circuit Simulation-Design Methodology ” IEEE J Solid-State Circuits V38• H. Feng, et al, A Mixed-Mode ESD Protection Circuit Simulation-Design Methodology , IEEE J. Solid-State Circuits, V38,

No. 6, p.995, June 2003.• R. Zhan, et al “ESDExtractor: A New Technology-Independent CAD Tool For Arbitrary ESD Protection Device Extraction”,

IEEE Trans on CAD of Integrated Circuits and Systems, V22, N10, p.1362, October 2003. • A. Wang, et al, " An on-Chip ESD Protection Circuit with Low Trigger-Voltage in BiCMOS Technology", IEEE J. Solid-State

Circuits, V36, N1, p.40, January 2001.• A Wang et al "On a Dual Direction on Chip Electrostatic Discharge Protection Structure“ IEEE Trans Elec Devices• A. Wang, et al, On a Dual-Direction on-Chip Electrostatic Discharge Protection Structure , IEEE Trans. Elec. Devices,

V48, N5, p.978, May 2001.• R. Zhan, “ESDcat: a New CAD Package for Full-Chip ESD Protection Design Verification”, PhD Dissertation, IIT, 2005.• X. Xie, “3D Mixed-Mode Simulation-Design Methodology and Electro-Thermal Modeling for ESD Protection Circuits”, MS

Thesis, IIT, 2004.• G. Chen, “Design and Characterization of ESD Protection for RFICs”, MS Thesis, IIT, 2003.

H F “A Mi d M d Si l ti D i M th d l F O Chi ESD P t ti D i ” MS Th i IIT 2001


• H. Feng, “A Mixed-Mode Simulation-Design Methodology For On-Chip ESD Protection Design”, MS Thesis, IIT, 2001.• K. Gong, “ESD Protection in Copper Interconnect and ESD-to-Circuit Performance Influences”, MS Thesis, IIT, 2001.

Documents

ESD PROTECTION FOR RF/AMS ICs - IEEE @ UCR Laboratory for Integrated Circuits and Systems • RF/Mixed-Signal/Analog IC & SoC • On-Chip ESD Protection for ICs • IC CAD & Modeling