ES 244: Digital Logic Design Chapter 5

ES 244: Digital Logic Design Chapter 5

Chapter 5: Synchronous Sequential Systems

Uchechukwu Ofoegbu

Temple University


Sequential Logic NetworksSequential Logic Networks• Combinational logic networks

– Outputs at any given time depends only on the input at that time

– Each output is represented by an algebraic function of the inputs

• Sequential logic networks– Outputs depend on past and present inputs– Past inputs must be stored – memory!– Synchronous sequential network

• behavior determined by values of the signal at discrete instants of time (clock)

– Asynchronous sequential networks • behavior immediately affected by the inputs changes


Copyright © 2008 The McGraw-Hill Companies, Inc. Permission required for reproduction or display.

ClocksClocks• Frequency = ?



Sequential SystemsSequential Systems


DefinitionsDefinitions• State:

– what is stored in memory– stored in binary devices

• Timing trace: – a set of values for the input and output at consecutive

clock times– and sometimes the state or other variables of the

system, as well.• State table:

– shows for each input combination and each state, what the output is and what the next state is, that is, what is to be stored in memory after the next clock.

• State diagram – a graphical representation of the state table.


ExampleExample• A system with one input x and one output z such that z = 1

if x has been 1 at least three consecutive clock times.

Moore ModelMoore ModelOutput:Output:

• depends only on the depends only on the state of the systemstate of the system

• does not depend on does not depend on the present inputthe present input

• occurs after desired occurs after desired patternpattern


Mealy ModelMealy Model• Output depends on present state as well as present input

11


LatchesLatches• Simple binary storage device• Consist of two or more gates• Involves feedback

– Output of one gate is connected to input of another• Inputs respond to outputs immediately• Example: S-R Latch – Q holds the latch value

P = (S + Q)

Q = (R + P)

00

00

Q’Q’

P’P’

11

00

00

11

00

11

11

00

11

11

00

00inactiveinactive


Flip FlopsFlip Flops

• Clocked binary storage device

• Value normally changes on appropriate clock transitions (except for special circumstances)

• Could have one or two outputs – State of the flip flop– Complement of the state

• Output can be described as function of input and present state


D – Flip FlopsD – Flip Flops• Simplest Flip Flop• Stands for Delay

– Output = input delayed until next clock transition


Timing Diagram for D – Flip FlopsTiming Diagram for D – Flip Flops

Is this leading or trailing edge?Is this leading or trailing edge?


Two D – Flip FlopsTwo D – Flip Flops• Output of 1 is input of 2• Output of 2 is output of 1

delayed


• Clear forces the output to 1 immediately

• Preset forces the output to 0 immediately

• Both can’t be 0• Flip flop is normal when both

are 1

Clear and Preset InputsClear and Preset Inputs



Clear and Preset InputsClear and Preset Inputs


q* = S + Rq

• Sets or Resets the data• If both S and R are low, output

remains unchanged• Both can’t be high

S-R – Flip FlopsS-R – Flip Flops


S-R – Flip FlopsS-R – Flip Flops


q* = T q

• Changes state if input is 1

T – Flip FlopsT – Flip Flops


q* = Jq + Kq

J-K – Flip FlopsJ-K – Flip Flops• J Sets and K resets the data• If both J and K are low, output remains unchanged• If both J and K are high, state changes



J-K – Flip FlopsJ-K – Flip Flops


Group WorkGroup Work

4,6


Analysis of Sequential CircuitsAnalysis of Sequential Circuits



HomeworkHomework8,9,10,12, 13,


The Design of Synchronous Logic Systems

Uchechukwu Ofoegbu

Temple University


ExampleExample• A system with one input x and one output z such that z = 1

if x has been 1 at least three consecutive clock times.


1.1. Step 1:Step 1: From a word description, determine what needs to be stored From a word description, determine what needs to be stored in memory, that is, what are the possible states.in memory, that is, what are the possible states.

2.2. Step 2:Step 2: If necessary, code the inputs and outputs in binary. If necessary, code the inputs and outputs in binary.

3.3. Step 3:Step 3: Derive a state table or state diagram to describe the behavior Derive a state table or state diagram to describe the behavior of the system.of the system.

4.4. Step 4: Step 4: Use state reduction techniques to find a state table that Use state reduction techniques to find a state table that produces the same input/output behavior, but has fewer states.produces the same input/output behavior, but has fewer states.

5.5. Step 5: Step 5: Choose a state assignment, that is, code the states in binary.Choose a state assignment, that is, code the states in binary.

6.6. Step 6:Step 6: Choose a flip flop type and derive the flip flop input maps or Choose a flip flop type and derive the flip flop input maps or tables.tables.

7.7. Step 7:Step 7: Produce the logic equation and draw a block diagram (as in Produce the logic equation and draw a block diagram (as in the case of combinational systems).the case of combinational systems).

Design stepsDesign steps


General Design General Design

Derive the equations for the next Derive the equations for the next state and the outputstate and the output


D Flip Flop Design D Flip Flop Design


D Flip Flop Design D Flip Flop Design


J-K Flip Flop Design J-K Flip Flop Design


J-K Flip Flop Design J-K Flip Flop Design


S-R Flip Flop Design S-R Flip Flop Design



T Flip Flop Design T Flip Flop Design



Group ProblemGroup Problem

JK:JK:

A- 0 XA- 0 X

B- 1 XB- 1 X

C- X 1C- X 1

D- X 0D- X 0

SR:SR:

A- 0 XA- 0 X

B- 1 0B- 1 0

C- 0 1C- 0 1

D- X 0D- X 0

TA TB:TA TB:

A- 1 1A- 1 1

B- X XB- X X

C- 0 0C- 0 0

D- 1 0D- 1 0

E- 0 1E- 0 1


Group ProblemGroup Problem

In groups, obtain the other equations!In groups, obtain the other equations!

Which flip-flop has the least delay?Which flip-flop has the least delay?


HomeworkHomework16,18,20,55,56

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ES 244: Digital Logic Design Chapter 5