INTRODUCTION

The confluence of Moore’s law and the matura-tion of the art of analog integrated circuit (IC)design has created a flurry of recent researchand development work on digitally intelligentanalog circuits. Exploiting high-density on-chipdigital processing, the approach represents atrendy alternative to conventional hard-laboredanalog design methodology, in which theinescapable trade-off between linearity, circuitbandwidth, complexity, and power dissipationhas limited the scaling progress of precision ana-log circuits in the past.

This trend is most observable in the area ofanalog-to-digital converters (ADCs), in whichthe readily available output bits provide a conve-nient digital means to infer component errors ofthe constituent imperfect analog circuits, and todevise correction schemes to mitigate the effectof these imperfections, all performed naturallyin the digital domain [1]. On a parallel path,although treating a continuous-time radio fre-quency (RF) circuit is considerably more diffi-cult than treating a discrete-time basebandADC, the potential benefit and adaptability thatcan be harvested from such treatment seems towell offset the initial design effort involved. As aresult, similar design approaches are makingquick inroads in the RF and soon even millime-ter-wave sectors [2, 3].

This article reviews the latest progress inthese exciting areas of research. An analogy willfirst be drawn to relate analog circuit distortions

to the non-idealities of a communication chan-nel. Under certain assumptions, both impair-ments can be modeled as a transversal structure.It is then pointed out that a zero-forcing equaliz-er is sufficient to treat the linear/nonlinear ana-log distortions similar to receiver equalization incommunications. Two variants of this approach,the parallel-path and split-path equalizationtechniques, are presented next, followed by afew design examples. The approach is lastextended to treating RF transmitter nonlineari-ties and I/Q mismatches with an adaptive trans-mitter equalizer to obtain highly linear RFtransmission at low power consumption withhighly nonlinear analog circuit components.

COMMUNICATION CHANNEL VS.ANALOG CIRCUIT

In wireless communications, multipath signaltransmission results in a phenomenon calledintersymbol interference (ISI), in which succes-sive transmitted symbols arrive at the receiver atthe same time, causing difficulties in decodingthe information. In such a scenario, the impulseresponse of the wireless channel becomes non-ideal, as shown in Fig. 1a, where it is modeled asa simple transversal structure.

In analog circuits, it is often necessary torealize in solid-state technology certain analogbuilding blocks with precision (e.g., amplifica-tion), which is vital to the overall accuracy of theanalog system constituting such building blocks.Figure 1d shows one example of such applica-tions of an ADC that utilizes the pipeline con-version architecture. A pipelined ADC exploitsthe concurrency of pipelining to expedite theconversion process, in which multiple conversionstages operate in tandem to divide the job intosubtasks, with each stage responsible for onesubtask only. In the limiting case, an N-bit ADCcan be divided into N pipelined stages with eachstage resolving one bit. The unresolved part ofthe analog signal in a previous stage is passed onto the next one in the form of a residue signal,which needs to be provisioned and amplified tocertain precision along the pipeline. The gains ofthe successive amplifications are shown in Fig. 1as a1, a2, a3, …, which all have an ideal value ofexactly 2 in the 1-bit/stage architecture shown inthe diagram. When these residue gains are real-ized perfectly, the partial decision bits from each

IEEE Communications Magazine • April 2011132 0163-6804/11/$25.00 © 2011 IEEE

ABSTRACT

Technology advancement entails an analogdesign scenario in which sophisticated signalprocessing algorithms are deployed in mixed-mode and radio frequency circuits to compen-sate for deterministic and random deficiencies ofprocess technologies. This article reviews onesuch approach of applying a common communi-cation technique, equalization, to correct fornonlinear distortions in analog circuits, which isanalogized as non-ideal communication chan-nels. The efficacy of this approach is showcasedby a few latest advances in data conversion andRF transmission integrated circuits, whereunprecedented energy efficiency, circuit lineari-ty, and post-fabrication adaptability have beenattained with low-cost digital processing.

INTEGRATED CIRCUITS FOR COMMUNICATIONS

Yun Chiu, Texas Analog Center of Excellence, University of Texas at Dallas

Equalization Techniques forNonlinear Analog Circuits

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IEEE Communications Magazine • April 2011 133

stage can be assembled to form the overall quan-tization result of the input sample. The assemblyprocess is typically no more than a binary-weight-ed sum of all bits with latency accounted for. Inpractice, component mismatch and insufficientgain accuracy of analog circuits cause the residuegain to vary from its ideal value of 2. Althoughthis variation may not be as large and time-vari-ant as the impulse response of a wireless chan-nel, it can be significant for high-resolutionapplications. For example, if the target resolu-tion is 12-bit, the residue gain error in the firstpipeline stage must be controlled to within 2–11,or 0.05 percent, of its nominal value, which isdifficult to realize in monolithic forms withouttrimming.

While effort can be invested in the design ofanalog circuits to improve their raw accuracy inthe first place, a trend in mixed-signal design isto increasingly utilize the on-chip processingcapability readily available in nanometer comple-mentary metal oxide semiconductor (CMOS)technology to perform digital post-processing ofthe raw circuit outputs to remedy various deter-ministic and random analog impairments. Dueto the difficult trade-off between linearity, band-width, complexity, and power consumption inanalog design, the digital-oriented alternativeapproach embodies potential for power savingand improved scalability for conventional analogcircuits in scaled technologies. Thus, this designapproach has been in the limelight of academic(in some cases, as well as industrial) research inrecent years.

In the pipelined ADC example shown in Fig.1d, it has been shown in [1] that an ideal quanti-zation of an input sample can still be obtainedby a proper weighted sum of all bits, Σhj ⋅ dj, aslong as the bit weights h1, h2, h3, and h4 take thevalues 1, (a1)–1, (a1a2)–1, and (a1a2a3)–1, respec-tively. The transversal structure of this formula-tion resembles the impulse response of thewireless channel model introduced earlier. It waspointed out in [1] that, omitting quantization

noise, {dj} can be interpreted as a (non-)binarydecomposition of the input sample Vi. Undercertain conditions, even with non-ideal bitweights due to analog inaccuracies, the idealbinary code space of Vi is still fully spanned by{dj}; that is, {dj} constitutes sufficient statisticsof the ideal quantization of Vi. This argumentcan be related to a common principle in digitalcommunications, which states that the receivedsymbols in the presence of ISI form sufficientstatistics of the transmitted symbols under cer-tain conditions. Whereas the ISI in communica-tions is modeled as a time-domain transversalstructure, the interstage interference in apipelined ADC is represented by a (binary)code-domain transversal structure, with bothshown in Fig. 1. In addition, if the reversal of themultipath distortion in wireless receivers relieson estimating the impulse response of the chan-nel, the reversal of the effect of the residue gaininaccuracies in a pipelined ADC can be reducedto estimating the bit weights {hj}, which may beanalogized as the “impulse response” in the codedomain.

EQUALIZING A/D CONVERTERSA common technique to correct for the non-ideal channel response in a communicationreceiver is to perform receiver equalization, inwhich a known sequence of training symbols aretransmitted to assist the receiver to estimate thechannel. This inspires the parallel-path ADCarchitecture of digital background calibrationshown in Fig. 2a. Here, “calibration” means toestimate the error parameters such as the bitweights {hj} in Fig. 1d of a non-ideal analog cir-cuit and devise error-correction schemes accord-ingly to eliminate the resulting distortions. Inprinciple, conversion nonlinearities caused bycomponent mismatch, amplifier gain error andnonlinearity, and offset can all be treated. InFig. 2a, the main ADC under calibration is thecommunication “channel”; a digital post-proces-

Figure 1. Channel non-idealities in communications result in intersymbol interference in the time domain,whereas analog circuit non-idealities in multistep analog-to-digital converters lead to interstage interferencein the code domain.

Do=h1·d1+h2·d2+h3·d3+h4·d4

Model of wireless channel Model of pipelined ADC

TX RX

(a) (b)(c) (d)

Impulseresponse

h1

h2h4

n

h3

z-1

h2h1

x(n)

y(n)

y(n)=h1x(n)+h2x(n-1)+h3x(n-2)+h4x(n-3)

z-1

h3

z-1

h4 h4

v3

d4

Do

a3

h4 h3

d3

Stage 4(1-bit)

Stage 3(1-bit)

v2a2

h2

d2

Stage 2(1-bit)

v1vi a1

h1

d1

Stage 1(1-bit)

A common tech-

nique to correct for

the non-ideal chan-

nel response in a

communication

receiver is to perform

receiver equalization,

in which a known

sequence of training

symbols are transmit-

ted to assist the

receiver to estimate

the channel. This

inspires the parallel-

path ADC architec-

ture of digital

background

calibration.

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IEEE Communications Magazine • April 2011134

sor is the “equalizer” that attempts to eradicatethe conversion errors in the ADC digital outputstream, assisted by a parallel reference ADCthat provides a “training sequence” continuouslyat a significantly lower rate compared to themain path. The down-sampling of the referencepath is essential for this scheme in practice asotherwise the realization of the reference ADCwould pose an issue. From a circuit standpoint,this architecture can also be understood as aseamless integration of two parallel ADCs, onefast but crude and the other precise but slow, tosimultaneously accomplish speed and accuracy ina digitizing process. This approach was firstshown to be viable in [1]. Similar work was inde-pendently reported in [4].

With the back-end digital calibration logic totake care of the analog imperfections, the mainADC circuits can then be made simple, fast, andenergy efficient. As elucidated before, this wouldbe otherwise impossible with the conventionaldesign methodology of precision analog circuits.In contrast, while certain accuracy is required forthe reference ADC, its conversion speed is great-ly relaxed relative to the main path, and thus itcan be realized with ease using a variety of con-ventional techniques. Another aspect of thisdesign approach is related to the elevated vari-

ability in deeply scaled processes. It is knownthat analog circuits are typically orders of magni-tude more sensitive to process variations thantheir digital counterparts. With the conventionalverification methodology for analog design, apessimistic bound of performance must be set tomeet certain target yield specs in anticipation ofsevere process variations. Digital post-processingessentially mitigates the difficult trade-offbetween performance and yield by allowing self-healing or digital intelligence built into an other-wise inflexible analog circuit, resulting insuperior and reliable performance from unreli-able analog components with poor raw perfor-mance.

The efficacy of this technique can be betterappreciated by the example shown in Fig. 2c of acapacitive amplifier employing a digital inverteras the gain element, which is calibrated by a 9th-order polynomial. The open loop gain of theinverter, which consists of two short-channeltransistors biased in saturation in a 0.13-μmCMOS process, is no more than 20 dB. A SPICEsimulation of the closed-loop response reveals alinearity of no more than 25 dB, which upon cal-ibration is improved to over 72 dB, nearly suffi-cient for a 12-bit ADC. The zero-forcing natureof the equalization also results in swift adapta-

Figure 2. Parallel-path digital background equalization of high-speed data converters.

+

-

SampleTime offset 0400

-70

-100

e (d

BFS)

-60

-50

-40

-30

-80

-90

-20

20 60 80 1000%

100%

Performance

A/D

+

-

A/D

Equalization

Conventionalanalog circuits: complex,

power-/area-hungry

Digitally equalizedanalog circuits: simple,power-/area-efficient

Yiel

d0.13-μm CMOS

m

Training sequence

“Channel”

Ref.ADC

+ -

m

M2 M1,M2

L VDD

ViVo

0.15 μm 1.2 V

A

Equalized by a 9th-order polynomial

C

C

+

-

M1

(a)

(b)(c)

MainADC

Parallel-path ADC digital background calibration

Vi DoDigital adaptive

equalizer

“Equalizer”

40k samples

-72 dBFS

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IEEE Communications Magazine • April 2011 135

tion of the error correction logic to accomplishthe above-mentioned accuracy within merely40,000 samples. This speed contrasts to the mil-lions or even billions of training samplesrequired for convergence by alternative back-ground calibration techniques, such as the corre-lation-based schemes [5, 6].

A DIGITALLY EQUALIZEDPIPELINED ADC

As mentioned before, a pipelined ADC is proba-bly the most popular multistep converter used inpractice and has been identified as the firstdemonstration vehicle of the digital equalizationtechnique for nonlinear analog circuits [7]. Inswitched-capacitor technology, a pipelined ADCcan be realized by a compact circuit called themultiplier digital-to-analog converter (MDAC),

shown in Fig. 3a. In the prototype, a pipelinedADC utilized a 1.5-bit front-end stage, followedby five 2.5-bit intermediate stages and a 3-bit laststage. Simple cascode pseudo-differential invert-ers were employed as residue gain amplifiers ineach stage, resulting in a low gain of around 30dB with highly nonlinear closed-loop characteris-tics. The nonlinearity of the residue amplifiertranslates into the distortion of the ADC transfercurves shown in Fig. 3b. A 5th-order nonlinearpolynomial, illustrated in Fig. 3e, was identifiedas sufficient to treat the amplifier for 12-bit lin-earity due to the cascode gain stage used in thedesign, which compares to the example in Fig. 2cwherein a digital inverter was employed.

One practical issue emerges when a multi-stage equalization treatment is formulated for apipelined ADC, in which a straightforward real-ization of simultaneous multistage error correc-tion dictates geometrical complexity vs. the

Figure 3. Nonlinear adaptive digital equalization of high-speed pipelined ADCs and experimental results.

w/o EQ w/ EQ

10 bitsResolution

100 MS/sSample rate

28.1 dBSNDR @ 0.4 MHz 59.4 dB

29.4 dBSNDR @ 49 MHz 54.8 dB

-30 dBHD3 @ 0.4 MHz -72 dB

-32 dBHD3 @ 49 MHz -68 dB

Chip measurement results

Ideal

d=0 d=1 d=2VR

-VR

-VR /2

↓214D1

D1α1,1

μ1e

Stage 1(1.5-bit)

Vi=V1

V1

V2 V3 ...

...

......

......

...

-VR

V2

V2

V1

VR

0C1 C2

A

A/D

MUX

d

-+

φ1 φ1

φ2

φ2

φ1e

Stage 2(2.5-bit)

Pipelined ADC

Pipelined nonlinear EQ

Do = k=1

α1,k • D1k + β1 • d1

5

Analog

Digital

Stage 7(3-bit flash)

(a)

(c)

(e)

(b)

(d)

(f)

0VR

Stage 1Do

D1

d1 d2 d7

D2Stage2z-½ Stage

7z-½

↑214

↓214D12

D12

α1,2

μ2e

↑214

↓214D15

D15

α1,5

μ5e

↑214

↓214d1 Do

d1β1

μ6e

↑214

VR /2

VR /4-VR /4

Distorted

Σ

CHIU LAYOUT 3/22/11 11:10 AM Page 135

IEEE Communications Magazine • April 2011136

number of the pipelined stages under calibration[1]. A reversely pipelined (relative to the analogcircuits) nonlinear adaptive equalizer shown inFig. 3c was introduced to solve this issue in theprototype. In addition, the 5th-order polynomialcorrection was applied only to the first twostages; the rest of the stages all employ a linear(i.e., first-order polynomial) correction scheme.

In the 0.13-μm CMOS prototype chip, thereference ADC was implemented by a sigma-delta ADC; and the relative down-sampling fac-tor was 214 between the reference and mainpaths. In experiments, the 3rd-order harmonicdistortion (HD3) of the pipelined ADC clockedat 100 Msamples/s was measured to be –30 dBwith a low-frequency full-scale sinusoidal input.It was improved to –72 dB when the digitalequalizer was fully adapted within 50,000 refer-ence samples. The measured peak integral non-linearity (INL) was 34.6 least significant bits(LSBs) and 1.1 LSBs before and after equaliza-tion, respectively. This work was reported in [7].

“SPLIT-ADC” EQUALIZATIONParallel path equalization is proven to be effec-tive in treating nonlinear distortions in pipelinedADCs. However, the architecture exhibits twoundesirable features for practical applications:• The nearly opposite performance specs for

the main and reference ADCs dictate a sys-tem-level complexity in that two dramatical-ly different ADCs need to be designed.

• The large down-sampling factor that easesthe design of the reference path may turnout to be a limiting factor for the overalladaptation speed.To minimize design complexity and acceler-

ate convergence, the two ADCs in the parallelarchitecture can be made identical and clockedat the same speed. Although neither is ideal tobegin with, the difference between their outputscaptures the lumped effect of their individualconversion errors. A zero-forcing equalizer canagain be used to simultaneously treat bothADCs; when their characteristics become ideal,the difference in their output disappears and theadaptation halts. This technique has led to the“split-ADC” equalization of algorithmic ADC [8,9] and pipelined ADC [10]. Of course, the twoADCs under calibration can be wrong in exactlythe same way, and the difference still drops tozero. In practice, decision trajectories can beartificially mutated by offsetting the comparatorthresholds in the two ADCs incorporating archi-tectural redundancy, thereby lowering the proba-bility of convergence to the wrong states [8]. INLas high as 13 bits has been demonstrated in a2.5-V 0.25-μm CMOS algorithmic ADC usingthe split-ADC equalization approach [8].

Lastly, a self-equalization architecture [11]was reported during the writing of this article,wherein an offset double conversion scheme wasutilized to identify all capacitor mismatch errorsin a 12-bit successive approximation (SA) ADC.The absence of a reference path results in thesimplicity of this technique, yielding a highly effi-cient equalization treatment while avoiding apotential front-end mismatch issue in the split-ADC architecture [8, 11].

OTHER CONVERTER APPLICATIONS

Theoretically speaking, the advocated parallel-path equalization should work for any A/D con-version architectures including the flash type.However, more succinct and compact error mod-els can often be derived for a multistep ADCthan for a single-step one. This is mostlyattributable to the built-in redundancy in thesearchitectures to avoid a potential overflow/underflow problem due to circuit offsets in amultistep resolving process. Common multistepNyquist-rate conversion architectures includepipeline, algorithmic, SA, and subranging types.The SA architecture is of particular interest inscaled processes due to its switching nature, lowpower, and benign digital compatibility. The lin-earity-limiting component in an SA ADC is usu-ally its constituent DAC, especially forresolutions of 10 bits and above.

In [12], it was shown that the equalizationtechnique is applicable to an SA ADC to correctits conversion nonlinearities provided that a sub-radix-2 digital-to-analog converter (DAC) is uti-lized, which compares to the binary searchprocess realized by a conventional SA structure.Note that a sub-radix-2 conversion architectureimplements a sub-binary search algorithm of thequantization process, which can be regardedessentially as a form of redundancy. The circuitschematic of an SA ADC is shown in Fig. 4b,where the ratio between adjacent DAC capaci-tors is chosen to be slightly less than two (asopposed to two in a binary counterpart). Anexperimental prototype of an 8-bit SA ADC wasdemonstrated in [13], which achieved a mea-sured low-frequency spurious-free dynamicrange (SFDR) of 65 dB in testing.

While technology advancement helps toimprove the switching speed of digital as well asanalog circuits, with both proven advantageousto the operation of SA ADCs, the sequentialsearch process during which one bit is resolvedin each step still imposes an inherent limit onthe conversion throughput of the architecture.At high conversion speeds, time-interleaved SAADC arrays provide a viable way to achieve highthroughput with low power consumption. Unfor-tunately, it is well known that time-interleavedconverter arrays are highly sensitive to path-mis-match problems such as gain error, offset, non-linearity, and sampling aperture skew amongmany parallel analog signal paths that constitutethe interleaving. It turns out that the inherentdeficiencies of time interleaving can be mostlylifted when equalization is applied.

The block diagram of a prototype time-inter-leaved ADC array is shown in Fig. 4a, whichaggregates the throughputs of 10 parallel ADCs,each clocked at 60 Msamples/s and utilizing anenergy-efficient SA architecture. The raw outputof each path is post-processed by an adaptivedigital equalizer assisted by a single slow butaccurate reference ADC, which continuallyupdates the equalizers using a gradient-descentalgorithm to track ambient variations. A uniquefeature of this treatment is that upon training,the characteristics of the individual ADCs areuniformly aligned to that of the reference ADC,thus eliminating path-mismatch errors inherent

A unique feature of

this treatment is that

upon training, the

characteristics of the

individual ADCs are

uniformly aligned to

that of the reference

ADC, thus

eliminating path-

mismatch errors

inherent in time

interleaving.

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IEEE Communications Magazine • April 2011 137

in time interleaving. A front-end track-and-hold(T/H) stage is utilized to mitigate the samplingaperture skews among the 10 interleaved paths.The prototype chip was fabricated in a 0.13-μmCMOS process, and occupies an active area of1.1 mm2. All measurements were performed at600 MS/s with a 1.2-V supply. When a 7.8-MHzsinusoidal input was applied, equalization result-ed in a signal-to-noise plus distortion ratio(SNDR) improvement from 31.2 to 46.7 dB, andan SFDR improvement from 33.0 to 65.2 dB.The large spectral spurs due to path mismatcherrors were largely eliminated. The measuredpeak INL was 1.7 LSBs and 0.23 LSBs at 8-bitlevel before and after calibration, respectively.Figure 4c shows the measured SNDR and SFDRvs. the input frequency. The SNDR was main-tained above 40 dB up to 460 MHz. In the exper-iments, it took 200,000 reference samples (0.33s) to train all 10 interleaved ADCs. The arraySNDR during a typical adaptation process isshown in Fig. 4e. The peak-to-peak SNDR fluc-tuation was less than 0.5 dB in steady state dueto continuous background tracking. The totalpower consumption including analog, digital,and clock distribution was 28 mW. The digital

equalizers, which were implemented in softwarein the experiment, estimate to an additional 2.3mW in power and 0.08 mm2 in area. This workwas recently reported in [13]. It is interesting tonote that the split-ADC equalization scheme hasrecently been extended to treating time-inter-leaved ADC arrays as well [14].

DIGITALLY EQUALIZEDRF TRANSMITTER

Continuous-time analog circuits perhaps arearguably more difficult to compensate than theirdiscrete-time counterparts such as converters.However, if treating ADC conversion errorsresembles receiver equalization, certain continu-ous-time circuits, such as an RF transmit path,may well be compensated by transmitter equal-ization. This approach is illustrated in Fig. 5c,where a common direct-conversion CMOS RFtransmitter (TX) is augmented by a feedbackpath and an adaptive digital equalizer. The base-band in-phase (I) and quadrature-phase (Q) dig-ital data are preprocessed digitally to cancel outthe effects of any I/Q mismatch and memoryless

Figure 4. Equalization of time-interleaved ADC array to a single reference path results in automatic inter-ADC mismatch correction andpath alignment.

EQ1

Do

Samples

Equalizer learning curves

102

45

SND

R (d

B)

40

35

101 103 104 105

Samples10

Nor

mal

ized

tap

valu

es

1

1.1

1.2

1.3

0.92 3 4

x104Input frequency (MHz)

1000

250

SND

R/SF

DR

(dB)

30

35

40

45

50

55

60

65

70

200

Measured chip performance

300 400 500 600 700 800

SNDR w/o EQSNDR w/ EQSFDR w/o EQSFDR w/ EQ

C8 C1 C0

d8 d1 D1

V1

+VR

-VR

d0

C0

SAlogic

Mux

Successive approximation ADC

(a) (b)

(c) (d) (e)

T/H

“Channels”

1X

1X...

......

. . .

Ref.ADC

ADC1

ADC1

ADC10 EQ10

“Equalizers”

Mux

Dr

Vi

V1D1

D10

V10

φr(0.6M)

φ

φ10(60M)

φ1(60M)

φ(600M)

Training sequence

0.13-µm CMOS die photo

CHIU LAYOUT 3/22/11 11:10 AM Page 137

IEEE Communications Magazine • April 2011138

nonlinearities of the whole transmit path includ-ing the severe amplitude and phase distortionsof the RF power amplifier (PA). The digital pre-processor is fine-tuned by a least mean square(LMS) algorithm to precisely match to thepotentially time-varying characteristics of the RFcircuits. This tuning is performed continuously inthe background by comparing the original trans-mitted data with a downconverted version of theactual radiated signal off the antenna (via thefeedback path).

Digitally calibrated RF radios in CMOStechnology are trendy perhaps mostly due tothe fact that an efficient allocation of the spec-trum resource for modern communication sys-tems dictates the use of non-constant-envelopmodulations that exhibit a high peak-to-averagepower ratio (PAPR). High PAPR stresses theTX linearity requirement, constraining design-ers to use linear and therefore power-inefficientanalog/RF circuits, especially the most power-consuming component of a TX, the PA. A

viable linearity/efficiency enhancementapproach for highly integrated CMOS TX isbaseband digital equalization, also known asadaptive predistortion, which allows the use ofnonlinear PAs such as the Class-B type (aCMOS circuit schematic of a Class-B PA isshown in Fig. 5b) with superior peak and aver-age efficiency characteristics. Wide signal band-widths can be treated using digital equalizationthat is less susceptible to stability concerns incontrast to analog linearization schemes such asCartesian feedback [15].

In a prototype 3.5-GHz CMOS TX chipimplemented in a 0.13-μm CMOS technology, anintegrated Class-B PA measured 44 percentdrain efficiency (DE) and 22.8 dBm saturatedoutput power, which compare favorably to linearClass-A PAs that usually achieve a peak DE inthe range of 10–20 percent. However, the effi-ciency was achieved at the cost of a gross distor-tion to the transmitted signal shown in Fig. 5a,which displayed an in-band error vector magni-

Figure 5. Transmitter adaptive equalization demonstrates the potential of highly linear and power-efficient CMOS radios with fully inte-grated nonlinear power amplifiers.

D/A

Center: 3.55 GHz Span: 200 MHz

10 dB/

Pin (dBm) Pout (dBm)-15-20

-50

-5-10

P out

[dB

m]/

Gai

n (d

B)

AM

-PM

[°]

0

5

10

15

5

10

15

20

25

-10

Pout

Power gain

-5 0 5 10 -5

10

0

Dra

in e

ffic

ienc

y (%

)

20

30

40

50

60

0 5 10

Measured results ofstand-alone PA chip

15 20 25

Frommixer

M3 M4

M7

M5 M6

M8

M2M1

BondwiresChipboundary To

balun

Second-harmonic

termination

Integrated 0.13-μm CMOS RF TX

w/o EQ

Chip measurement results

w/ EQ

3.55 GHzCarrier frequency

22.8 dBmMax Pout

44%Max PA DE

39%Max PA PAE

9.0%EVM 3.3%

2.3 msecConvergence time

Adaptivedigital EQ

LO

D/A

TX equalizer CMOS direct-conversion RF TX CMOS Class-B PA

I

(a) (b)

(d) (f)(e)

(c)

w/ EQ

w/o EQ

802.11aspectrum

mask

0-dB PBO

Q

QI

QI

LMSupdate

A/D

A/D

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IEEE Communications Magazine • April 2011 139

tude (EVM) as high as 9.0 percent at 0 dB peakback-off (PBO) when a 20-MHz, 64-quadratureamplitude modulation (QAM), 64-subcarrierorthogonal frequency-division multiplexed(OFDM) signal with a 9.6-dB PAPR was trans-mitted. An RF transmitter that exhibits such lin-earity is normally of little practical value becausean indoor wireless LAN protocol (e.g., 802.11a/g)typically stipulates an EVM spec of –25 dB (5.6percent). In the experiment, an I/Q-addressedtwo-dimensional lookup table (2D LUT) wasdevised to compensate the TX distortions. Aunique advantage of employing a 2D LUT com-pensation scheme is that the I/Q mismatch andmemoryless TX nonlinearities, including thebaseband circuits (i.e., the DAC and low-pass fil-ter [LPF]) and RF signal paths (i.e., the upcon-version mixer and PA), are all uniformly treated.As a result, the EVM was improved significantlyto 3.3 percent when the equalizer convergedwithin 2.3 ms. A die photo of the prototype chipis illustrated in Fig. 5d, which integrates the TX,Class-B PA, and feedback path. The digitalequalizer was implemented in an Altera StratixII field programmable gate array (FPGA) thatwas clocked at 80 MHz. This work was recentlyreported in [2], and more details of the digitalequalizer can be found in [3].

One further remark on this work is about aknown side effect of digital preprocessing com-pensation in which the baseband signal band-width may be significantly broadened. In ourexperiment, a 34-MHz cutoff frequency of theTX LPF and an 80-MHz DAC sample rate werefound sufficient to satisfy the 802.11a spectrummask without additional oversampling. The mea-sured PA output spectra before and after equal-ization are shown in Fig. 5f. The 5th-orderfrequency response of the LPF is instrumentalhere to retain all desired spread spectrum andyet maintain the low oversampling ratio.

CONCLUSIONThe art of analog design has evolved such thatcircuit linearity may be more efficiently procuredusing system-level techniques rather than device-or component-level ones. Among variousresearch efforts inspired by this vision, a digitalequalization approach addressing analog circuitdistortions stemming from various physical ori-gins, including the process variability in deeplyscaled technologies, is presented. Several experi-mental chip results are showcased to demon-strate the efficacy of this approach and supportthe rationale behind the advocated researchtheme. Unprecedented analog linearity, energyefficiency, and scalability are likely outcomes ofthis approach in nanometer fabrication technolo-gies in the years to come.

ACKNOWLEDGMENTSThe data converter and RF transmitter projectshave been sponsored in part by ADI, Marvell,Agilent, and ITRI. Chip fabrications have beendonated by UMC, SMIC, and STMicroelectron-ics. Testing help from Dan Mast of the ECE

instructional laboratories at UIUC and of ITRIare acknowledged. Wenbo Liu, Dae Hyun Kwon,Hao Li, Richard Tseng, Pingli Huang, andSeung-Chul Lee from our research group havemade technical contributions at various stages ofthis research theme. Earlier contributions fromthe Berkeley team — Cheongyuen Tsang, JohanVanderhaegen, Sebastian Hoyos, BorivojeNikolic’, Robert Brodersen, and Paul Gray — arealso acknowledged.

REFERENCES[1] Y. Chiu et al., “Least-Mean-Square Adaptive Digital

Background Calibration of Pipelined Analog-to-DigitalConverters,” IEEE Trans. Circuits and Sys,. I, vol. 51, no.1, Jan. 2004, pp. 38–46.

[2] D.-H. Kwon et al., “CMOS RF Transmitter with IntegratedPower Amplifier Utilizing Digital Equalization,” Proc. IEEECustom Integrated Circuits Conf., Sept. 2009, pp. 403–06.

[3] H. Li et al., “A Fast Digital Predistortion Algorithm forRadio-Frequency Power Amplifier Linearization withLoop Delay Compensation,” IEEE J. Sel. Topics Sig.Proc., vol. 3, no. 3, June 2009, pp. 374–83.

[4] X. Wang et al., “A 12-Bit 20-MS/s Pipelined ADC withNested Digital Background Calibration,” Proc. IEEE Cus-tom Integrated Circuits Conf., Sept. 2003, pp. 409–12.

[5] E. J. Siragusa et al., “A Digitally Enhanced 1.8V 15b 40MS/sCMOS Pipelined ADC,” IEEE Int’l. Solid-State Circuits Conf.,Dig. Tech. Papers, Feb. 2004, pp. 452–53.

[6] Y.-S. Shu et al., “A 15b linear, 20MS/s, 1.5b/stagePipelined ADC Digitally Calibrated with Signal-Depen-dent Dithering,” IEEE Symp. VLSI Circuits, Dig. Tech.Papers, June 2006, pp. 218–19.

[7] C. Tsang et al., “Background ADC Calibration in DigitalDomain,” Proc. IEEE Custom Integrated Circuits Conf.,Sept. 2008, pp. 301–04.

[8] J. McNeill et al., “”Split ADC” Architecture for Deter-ministic Digital Background Calibration of a 16-bit 1-MS/s ADC,” IEEE J. Solid-State Circuits, vol. 40, no. 12,Dec. 2005, pp. 2437–45.

[9] J. Li et al., “Background Calibration Techniques for Mul-tistage Pipelined ADC’s With Digital Redundancy,” IEEETrans. Circuits and Sys. II, vol. 50, no. 9, Sept. 2003,pp. 531–38.

[10] I. Ahmed et al., “An 11-bit 45 MS/s Pipelined ADCwith Rapid Calibration of DAC errors in a MultibitPipeline Stage,” IEEE J. Solid-State Circuits, vol. 43, no.7, July 2008, pp. 1626–37.

[11] W. Liu et al., “A 12b 22.5/45MS/s 3.0mW 0.059mm2

CMOS SAR ADC Achieving over 90dB SFDR,” IEEE Int’l.Solid-State Circuits Conf., Dig. Tech. Papers, Feb. 2010,pp. 380–81.

[12] W. Liu et al., “An Equalization-Based Adaptive DigitalBackground Calibration Technique for SuccessiveApproximation Analog-to-Digital Converters,” Proc. IEEEInt’l. Conf. ASIC, Oct. 2007, pp. 289–92.

[13] W. Liu et al., “A 600MS/s 30mW 0.13μm CMOS ADCArray Achieving over 60dB SFDR with Adaptive DigitalEqualization,” IEEE Int’l. Solid-State Circuits Conf., Dig.Tech. Papers, Feb. 2009, pp. 82–83.

[14] J. McNeill et al., “”Split ADC” Calibration for all-DigitalCorrection of Time-Interleaved ADC Errors,” IEEE Trans. Cir-cuits and Sys. II, vol. 56, no. 5, May 2009, pp. 344–48.

[15] J. L. Dawson et al., “Automatic Phase Alignment for AFully Integrated Cartesian Feedback Power AmplifierSystem,” IEEE J. Solid-State Circuits, vol. 38, no. 12,Dec. 2003, pp. 2269–79.

BIOGRAPHYYUN CHIU [SM] (chiu.yun@utdallas.edu) is with the TexasAnalog Center of Excellence (TxACE) of the University ofTexas at Dallas, where he is an associate professor of theElectrical Engineering Department and holds the TxACEEndowed Professorship. He received the Jack Kilby Awardfrom the 2005 International Solid-State Circuits Conferenceand the ISSCC/DAC Student Design Contest Award in 2009.He is the author of the book Analysis and Design ofPipelined Analog-to-Digital Converters.

Several experimental

chip results are

showcased to

demonstrate the effi-

cacy of this

approach and to

support the rationale

behind the advocat-

ed research theme.

Unprecedented ana-

log linearity, energy

efficiency, and scala-

bility are likely out-

comes of this

approach in

nanometer fabrica-

tion technologies in

the years to come.

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