Equality Detector

Module M5.1

Section 6.1

Equality Detector

XNOR

X

YZ

Z = !(X $ Y)

X Y Z0 0 10 1 01 0 01 1 1

4-Bit Equality Comparator

A0

A1

A2

A3

B0

B1

B2

B3

A_EQ_B

C0

C1

C3

C2

FIELD A = [A0..3];FIELD B = [B0..3];FIELD C = [C0..3];

Bit Fields

FIELD A = [A0..3];FIELD B = [B0..3];FIELD C = [C0..3];

A represents [A0, A1, A2, A3]

B represents [B0, B1, B2, B3]

C represents [C0, C1, C2, C3]

Listing 6.1 eqcomp1.pld

Name eqcomp1;Partno OU0004;Revision 01;Date 7/26/91;Designer R. E. Haskell;Company Oakland University;Location Rochester, MI;Assembly CSE 171;Device G16V8;Format j;

/******************************************************//* *//* This is a 4-bit equality comparator *//* using the ANDing of 4 XOR gates *//* *//******************************************************//* Target Device: G16V8 *//******************************************************/

/* Inputs: */

Pin [2..5] = [A0..3];Pin [6..9] = [B0..3];

/* Outputs: */

Pin 19 = A_EQ_B;

/* Intermediate variables */

FIELD A = [A0..3];FIELD B = [B0..3];FIELD C = [C0..3];

/* Logic equations */

C = !(A $ B);

A_EQ_B = C0 & C1 & C2 & C3;

Listing 6.1 eqcomp1.pld

Name eqcomp1;Partno OU0004;Revision 01;Date 7/26/91;Designer R. E. Haskell;Company Oakland University;Location Rochester, MI;Assembly CSE 171;Device G16V8;Format j;

/******************************************************//* *//* This is a 4-bit equality comparator *//* using the ANDing of 4 XNOR gates *//* *//******************************************************//* Target Device: G16V8 *//******************************************************/

/* Inputs: */

Pin [2..5] = [A0..3];Pin [6..9] = [B0..3];

/* Outputs: */

Pin 19 = A_EQ_B;

/* Intermediate variables */

FIELD A = [A0..3];FIELD B = [B0..3];FIELD C = [C0..3];

/* Logic equations */

C = !(A $ B);

A_EQ_B = C0 & C1 & C2 & C3;

C = !(A $ B)

C0 = !(A0 $ B0)C1 = !(A1 $ B1)C2 = !(A2 $ B2)C3 = !(A3 $ B3)

A0

A1

A2

A3

B0

B1

B2

B3

A_EQ_B

C0

C1

C3

C2

Run WinCupl

.DOC File=============================================== Expanded Product Terms===============================================

A => A0 , A1 , A2 , A3

A_EQ_B => !A0 & !A1 & !A2 & !A3 & !B0 & !B1 & !B2 & !B3 # A0 & !A1 & !A2 & !A3 & B0 & !B1 & !B2 & !B3 # !A0 & A1 & !A2 & !A3 & !B0 & B1 & !B2 & !B3 # A0 & A1 & !A2 & !A3 & B0 & B1 & !B2 & !B3 # !A0 & !A1 & A2 & !A3 & !B0 & !B1 & B2 & !B3 # A0 & !A1 & A2 & !A3 & B0 & !B1 & B2 & !B3 # !A0 & A1 & A2 & !A3 & !B0 & B1 & B2 & !B3 # A0 & A1 & A2 & !A3 & B0 & B1 & B2 & !B3 # !A0 & !A1 & A2 & A3 & !B0 & !B1 & B2 & B3 # A0 & !A1 & A2 & A3 & B0 & !B1 & B2 & B3 # !A0 & A1 & A2 & A3 & !B0 & B1 & B2 & B3 # A0 & A1 & A2 & A3 & B0 & B1 & B2 & B3 # !A0 & A1 & !A2 & A3 & !B0 & B1 & !B2 & B3 # A0 & A1 & !A2 & A3 & B0 & B1 & !B2 & B3 # !A0 & !A1 & !A2 & A3 & !B0 & !B1 & !B2 & B3 # A0 & !A1 & !A2 & A3 & B0 & !B1 & !B2 & B3

B => B0 , B1 , B2 , B3

4-Bit Equality Comparator

A0

A1

A2

A3

B0

B1

B2

B3

A_EQ_B

C0

C1

C3

C2

D01

D23

The GAL 16V8

1

2

3

4

5

6

7

9

10 11

12

8

19

20

17

18

15

16

13

14

GND

Vcc I/CLK I I/O

I I

I

I

I

I

I

I/OE

I/O

I/O

I/O

I/O

I/O

I/O

I/O

GAL 16V8

Structure of the GAL 16V8 PLDX X X X X X X X

X X X X X X X X

X X X X X X X X

X X X X X X X X

X X X X X X X X

X X X X X X X X

X X X X X X X X

X X X X X X X X

Pin 2

Pin 3

Pin 19

X

Y

Z

GA L 16V8 Feedback

/* Inputs: */

Pin [2..5] = [A0..3];Pin [6..9] = [B0..3];

/* Outputs: */

Pin 19 = A_EQ_B;Pin 18 = D01; /* Intermediate pin output */Pin 17 = D23; /* Intermediate pin output */

/* Intermediate variables */

FIELD A = [A0..3];FIELD B = [B0..3];FIELD C = [C0..3];

/* Logic equations: */

C = !(A $ B);D01 = C0 & C1;D23 = C2 & C3;

A_EQ_B = D01 & D23;

=============================================== Expanded Product Terms===============================================

A => A0 , A1 , A2 , A3

A_EQ_B => D01 & D23

B => B0 , B1 , B2 , B3

C => C0 , C1 , C2 , C3

C0 => A0 & B0 # !A0 & !B0

C1 => A1 & B1 # !A1 & !B1

C2 => A2 & B2 # !A2 & !B2

C3 => A3 & B3 # !A3 & !B3

D01 => !A0 & !A1 & !B0 & !B1 # A0 & !A1 & B0 & !B1 # !A0 & A1 & !B0 & B1 # A0 & A1 & B0 & B1

D23 => !A2 & !A3 & !B2 & !B3 # A2 & !A3 & B2 & !B3 # !A2 & A3 & !B2 & B3 # A2 & A3 & B2 & B3

A_EQ_B.oe => 1

D01.oe => 1

D23.oe => 1

4-Bit Equality Comparator====================================-=============== Chip Diagram====================================================

______________ | eqcomp2 | x---|1 20|---x Vcc A0 x---|2 19|---x A_EQ_B A1 x---|3 18|---x D01 A2 x---|4 17|---x D23 A3 x---|5 16|---x B0 x---|6 15|---x B1 x---|7 14|---x B2 x---|8 13|---x B3 x---|9 12|---x GND x---|10 11|---x |______________|

End of .doc file

Question

Expand the following CUPL equation for F:

FIELD A = [A2..0];FIELD B = [B2..0];FIELD F = [F2..0];

F = !A & B;