eGaN® FET DATASHEET EPC2038

EPC – THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | | 1

EPC2038 – Enhancement Mode Power Transistor with Integrated Reverse Gate Clamp DiodeVDS , 100 VRDS(on) , 3300 mΩID , 0.5 A

EPC2038 eGaN® FETs are supplied only inpassivated die form with solder bumps. Die size: 0.9 mm x 0.9 mm

Applications Synchronous Bootstrap for:• High Speed DC-DC Conversion• Wireless Power Transfer• High Frequency Hard-Switching and Soft-Switching Circuits • Lidar/Pulsed Power Applications • Class-D Audio

Benefits• Ultra High Efficiency• Ultra Low RDS(on)

• Ultra Low QG

• Ultra Small Footprint

EFFICIENT POWER CONVERSION

HAL

D

S

G

Maximum Ratings

PARAMETER VALUE UNIT

VDSDrain-to-Source Voltage (Continuous) 100

VDrain-to-Source Voltage (up to 10,000 5 ms pulses at 150°C) 120

IDContinuous (TA = 25°C, RθJA = 100°C/W) 0.5

APulsed (25°C, TPULSE = 300 µs) 0.5

VGS Gate-to-Source Voltage 6 V

TJ Operating Temperature -40 to 150°C

TSTG Storage Temperature -40 to 150

Thermal Characteristics

PARAMETER TYP UNIT

RθJC Thermal Resistance, Junction-to-Case 27

°C/W RθJB Thermal Resistance, Junction-to-Board 91

RθJA Thermal Resistance, Junction-to-Ambient (Note 1) 100

Static Characteristics (TJ = 25°C unless otherwise stated)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITBVDSS Drain-to-Source Voltage VGS = 0 V, ID = 125 μA 100 V

IDSS Drain-Source Leakage VDS = 80 V, VGS = 0 V 20 100 μA

IGSSGate-to-Source Forward Leakage VGS = 5 V, TJ = 25˚C 0.0001 0.5

mAGate-to-Source Forward Leakage# VGS = 5 V, TJ = 125˚C 0.002 1

VF Source-Gate Forward Voltage IF = 0.2 mA, VDS = 0 V 2.7 V

VGS(TH) Gate Threshold Voltage VDS = VGS, ID = 0.1 mA 0.8 1.7 2.5 V

RDS(on) Drain-Source On Resistance VGS = 5 V, ID = 0.05 A 2100 3300 mΩ

VSD Source-Drain Forward Voltage IS = 0.1 A, VGS = 0 V 2.9 V

Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board.See https://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details.

All measurements were done with substrate connected to source.# Defined by design. Not subject to production test.

Gallium Nitride’s exceptionally high electron mobility and low temperature coefficient allows very low RDS(on), while its lateral device structure and majority carrier diode provide exceptionally low QG and zero QRR. The end result is a device that can handle tasks where very high switching frequency, and low on-time are beneficial as well as those where on-state losses dominate.

eGaN® FET DATASHEET EPC2038

EPC – THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | | 2

0.5

0.4

0.3

0.2

0.1

00 0.5 1.0 1.5 2.0 2.5 3.0

I D –

Dra

in Cu

rrent

(A)

Figure 1: Typical Output Characteristics at 25°C

VDS – Drain-to-Source Voltage (V)

VGS = 5 VVGS = 4 VVGS = 3 VVGS = 2 V

R DS(

on) –

Dra

in-to

-Sou

rce R

esist

ance

(mΩ

)

VGS – Gate-to-Source Voltage (V) 2.5 3.0 3.5 4.0 4.5 5.0

Figure 3: RDS(on) vs. VGS for Various Drain Currents

ID = 0.05 AID = 0.10 AID = 0.15 AID = 0.20 A

8000

6000

4000

2000

0

I D –

Dra

in Cu

rrent

(A)

VGS – Gate-to-Source Voltage (V) 1.00.5 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

Figure 2: Transfer Characteristics

25˚C125˚C

VDS = 3 V

I D –

Dra

in Cu

rrent

(A)

VGS – Gate-to-Source Voltage (V) 1.00.5 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

Figure 2: Transfer Characteristics

25˚C125˚C

VDS = 3 V

0.5

0.4

0.3

0.2

0.1

0

2.5 3.0 3.5 4.0 4.5 5.0

Figure 4: RDS(on) vs. VGS for Various Temperatures

25˚C125˚C

ID = 0.05 A

R DS(

on) –

Dra

in-to

-Sou

rce R

esist

ance

(mΩ

)

VGS – Gate-to-Source Voltage (V)

8000

6000

4000

2000

0

Dynamic Characteristics (TJ = 25°C unless otherwise stated)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITCISS Input Capacitance

VDS = 50 V, VGS = 0 V

7 8.4

pF

CRSS Reverse Transfer Capacitance 0.02

COSS Output Capacitance 1.6 2.4

COSS(ER) Effective Output Capacitance, Energy Related (Note 2)VDS = 0 to 50 V, VGS = 0 V

2.2

COSS(TR) Effective Output Capacitance, Time Related (Note 3) 2.7

RG Gate Resistance 4.8 Ω

QG Total Gate Charge VDS = 50 V, VGS = 5 V, ID = 0.05 A 44

pC

QGS Gate-to-Source Charge

VDS = 50 V, ID = 0.05 A

20

QGD Gate-to-Drain Charge 4

QG(TH) Gate Charge at Threshold 18

QOSS Output Charge VDS = 50 V, VGS = 0 V 134

QRR Source-Drain Recovery Charge 0All measurements were done with substrate connected to source.Note 2: COSS(ER) is a fixed capacitance that gives the same stored energy as COSS while VDS is rising from 0 to 50% BVDSS. Note 3: COSS(TR) is a fixed capacitance that gives the same charging time as COSS while VDS is rising from 0 to 50% BVDSS.

eGaN® FET DATASHEET EPC2038

EPC – THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | | 3

All measurements were done with substrate shortened to source.

Capa

citan

ce (p

F)

100

10

1

0.1

0.01

0.0010 20 40 60 80 100

Figure 5b: Capacitance (Log Scale)

VDS – Drain-to-Source Voltage (V)

COSS = CGD + CSD

CISS = CGD + CGS

CRSS = CGD

0.50 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

I SD –

Sour

ce-to

-Dra

in Cu

rrent

(A)

VSD – Source-to-Drain Voltage (V)

Figure 7: Reverse Drain-Source Characteristics0.5

0.4

0.3

0.2

0.1

0

25˚C125˚C

VGS = 0 V

Figure 9: Normalized Threshold Voltage vs. Temperature

Norm

alize

d Th

resh

old

Volta

ge

1.40

1.30

1.20

1.10

1.00

0.90

0.80

0.70

0.600 25 50 75 100 125 150

TJ – Junction Temperature (°C)

ID = 0.1 mA

Capa

citan

ce (p

F)

0 20 40 60 80 100

Figure 5a: Capacitance (Linear Scale)

VDS – Drain-to-Source Voltage (V)

COSS = CGD + CSD

CISS = CGD + CGS

CRSS = CGD

8

7

6

5

4

3

2

1

0

5

4

3

2

1

00 10 20 30 40 50

Figure 6: Gate Charge

V GS

– Ga

te-to

-Sou

rce V

olta

ge (V

)

QG – Gate Charge (pC)

ID = 0.05 AVDS = 50 V

Figure 8: Normalized On-State Resistance vs. Temperature

ID = 0.05 AVGS = 5 V

Norm

alize

d On

-Sta

te R

esist

ance

RDS

(on)

2.2

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.60 25 50 75 100 125 150

TJ – Junction Temperature (°C)

eGaN® FET DATASHEET EPC2038

EPC – THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | | 4

Figure 10: Transient Thermal Response Curves

tp, Rectangular Pulse Duration, seconds

Z θJC

, Nor

mal

ized T

herm

al Im

peda

nce

0.50.2

0.050.02

Single Pulse

0.01

0.1

Duty Cycle:

Junction-to-Case

PDM

t1

t2

10-5 10-4 10-3 10-2 10-1 101

1

0.1

0.01

0.001

0.0001

Notes:Duty Factor: D = t1/t2

Peak TJ = PDM x ZθJC x RθJC + TC

tp, Rectangular Pulse Duration, seconds

Z θJB

, Nor

mal

ized T

herm

al Im

peda

nce

0.5

0.1

0.020.05

Single Pulse

0.01

Duty Cycle:

Junction-to-Board

PDM

t1

t2

10-6 10-5 10-4 10-3 10-2 10-1 1

1

0.1

0.01

0.001

0.0001

Notes:Duty Factor: D = t1/t2

Peak TJ = PDM x ZθJB x RθJB + TB

Figure 11: Safe Operating Area

0.01

0.1

1

0.1 1 10 100

I D – Dr

ain Cu

rrent

(A)

VDS - Drain Voltage (V)

Limited by RDS(on)

Pulse Width 100 ms 10 ms 1 ms

eGaN® FET DATASHEET EPC2038

EPC – THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | | 5

DIE MARKINGS

Die orientation dot

Gate Pad bump is under this corner

Part Number

Laser Markings

Part #Marking Line 1

Lot_Date CodeMarking line 2

EPC2038 AD YYY

ADYYY

ADYYY

TAPE AND REEL CONFIGURATION4mm pitch, 8mm wide tape on 7” reel

7” reel

a

d e f g

c

b

EPC2038 (note 1) Dimension (mm) target min max

a 8.00 7.90 8.30 b 1.75 1.65 1.85

c (see note) 3.50 3.45 3.55 d 4.00 3.90 4.10 e 4.00 3.90 4.10

f (see note) 2.00 1.95 2.05 g 1.5 1.5 1.6

Note 1: MSL 1 (moisture sensitivity level 1) classied according to IPC/JEDEC industry standard.Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket, not the pocket hole.

Dieorientationdot

Gatesolder bar isunder thiscorner

Die is placed into pocketsolder bar side down(face side down)

Loaded Tape Feed Direction

eGaN® FET DATASHEET EPC2038

EPC – THE LEADER IN GaN TECHNOLOGY | WWW.EPC-CO.COM | COPYRIGHT 2019 | | 6

RECOMMENDEDLAND PATTERN (measurements in µm)

DIE OUTLINESolder Bump View

Side View

RECOMMENDEDSTENCIL DRAWING (measurements in µm)

Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others.

eGaN® is a registered trademark of Efficient Power Conversion Corporation.EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx

Pads 1 is Gate;

Pad 3 is Drain;

Pads 2, 4 are Source

The land pattern is solder mask definedSolder mask is 10 μm smaller per side than bump

Recommended stencil should be 4 mil (100 µm) thick, must be laser cut, openings per drawing.

Intended for use with SAC305 Type 4 solder, reference 88.5% metals content.

Additional assembly resources available at https://epc-co.com/epc/DesignSupport/AssemblyBasics.aspx

DIM MIN Nominal MAX

A 870 900 930B 870 900 930c 450 450 450d 450 450 450e 210 225 240f 210 225 240g 187 208 229

(625

)

Seating Plane

815 M

ax

165+

/- 17

B

A

ce

31

2 4

g

df

Pads 1 is Gate;Pad 3 is Drain;Pads 2, 4 are Source

900

900

450 225

42

1 3

200 +20 / - 10 (*)

X4

242

450

225

* minimum 190

450 225

250

900

900

450

225

R60

Information subject to change without notice.

Revised August, 2019