ENGS 116 Lecture 71 Scoreboarding Vincent H. Berk October 8, 2008 Reading for today: A.5 – A.6, article: Smith&Pleszkun FRIDAY: NO CLASS Reading for Monday:

ENGS 116 Lecture 7 1

Scoreboarding

Vincent H. Berk

October 8, 2008

Reading for today: A.5 – A.6, article: Smith&Pleszkun

FRIDAY: NO CLASS

Reading for Monday: A.7 – A.8


Scoreboard Implications (hardware ILP)

• Out-of-order completion WAR, WAW hazards?

• Solutions for WAR

– Queue both the operation and copies of its operands

– Read registers only during Read Operands stage

• For WAW, must detect hazard: stall until other write completes

• Need to have multiple instructions in execution phase multiple execution units or pipelined execution units

• Scoreboard keeps track of dependences, state, and operations

• Scoreboard replaces ID, EX, WB with 4 main stages

– The EX stage can be (sub-)pipelined


Figure A.50 The basic structure of a DLX processor with a scoreboard

Control/statusControl/status


Four Stages of Scoreboard Control: ISSUE

1. Issue: decode instructions & check for structural hazards (ID1)

If a functional unit for the instruction is free and no other active instruction has the same destination register (WAW), the scoreboard issues the instruction to the functional unit and updates its internal data structure. If a structural or WAW hazard exists, then the instruction issue stalls, and no further instructions will issue until these hazards are cleared.

Algorithm:

• Assure In-Order issue

• Multiple issues per cycle are allowed

• Check if Destination Register is already reserved for writing (WAW)

• Check if Read-Operand stage of Functional Unit is free (Structural)


Four Stages of Scoreboard Control:READ-OPERANDS

1. Read operands: wait until no data hazards, then read operands (ID2) – First Functional Pipeline Stage

A source operand is available if no earlier issued active instruction is going to write it, or if the register containing the operand is being written by a currently active functional unit. When the source operands are available, the scoreboard tells the functional unit to proceed to read the operands from the registers and begin execution. The scoreboard resolves RAW hazards dynamically in this step, and instructions may be sent into execution out of order.

Algorithm:

• Wait for operands to become available, Register Result Status (RAW)

• Operand Caching is allowed

• Forwarding from another WB stage is allowed


Four Stages of Scoreboard Control

3. Execution: operate on operands (EX)

– The functional unit begins execution upon receiving operands. When the result is ready, it notifies the scoreboard that it has completed execution. This stage can be (sub-)pipelined.

4. Write result: finish execution (WB)

– Once the scoreboard is aware that the functional unit has completed execution, the scoreboard checks for WAR hazards. If none, it writes results. If WAR, it stalls the instruction.

Algorithm:

• Delay write until all Rj and Rk fields for this register are marked as either cached or read.

– If caching of operands is done: forward answer right away.

– If not, wait until all operands are read before writing.

• Forward answers to units waiting for this write for their operand.


Three Parts of the Scoreboard

1. Instruction status: Indicates which of 4 steps the instruction is in.

2. Functional unit status: Indicates the state of the functional unit (FU). 9 fields for each functional unit Busy – Indicates whether the unit is busy or not Op – Operation to perform in the unit (e.g., + or -) Fi – Destination register Fj, Fk – Source-register numbers Qj, Qk – Functional units producing source registers Fj, Fk Rj, Rk – Flags indicating when Fj, Fk are available and not yet

read. (Alternatively: read and cached)

3. Register result status: Indicates which functional unit will write each register, if one exists. Blank when no pending instructions will write that register.


Instruction Issue ReadOperands

Executioncomplete

Writeresult

LD F6, 34 (R2)

LD F2, 45 (R3)

MULTD F0, F2, F4

SUBD F8, F6, F2

DIVD F10, F0, F6

ADDD F6, F8, F2

Instruction status

Functional unit status

F0 F2 F4 F6 F8 F10 F12 … F30

FU Mult1 Integer Sub Divide

Register result status

FIGURE A.52 Components of the scoreboard

Name Busy Op Fi Fj Fk Qj Qk Rj Rk

Integer Yes Load F2 R3 Yes

Mult1 Yes Mult F0 F2 F4 Integer No Yes

Mult2 No

Add Yes Sub F8 F6 F2 Integer Yes No

Divide Yes Div F10 F0 F6 Mult1 No Yes


Scoreboard Example Cycle 1Instruction status Read Execution Write

Instruction j k Issue operands complete Result

LD F6 34 R2 1LD F2 45 R3MULTD F0 F2 F4 Clock 1SUBD F8 F6 F2DIVD F10 F0 F6ADDD F6 F8 F2

Functional unit status dest S1 S2 FU for j FU for k Fj? Fk?

Name Busy Op Fi Fj Fk Qj Qk Rj RkInteger Yes Load F6 R2 YesMult1 NoMult2 NoAdd NoDivide No

Register result statusF0 F2 F4 F6 F8 F10 F12 ... F30

FU Int

R2 has not been read/cached until cycle 2!!!




LD F6 34 R2 1 2LD F2 45 R3MULTD F0 F2 F4 Clock 2SUBD F8 F6 F2DIVD F10 F0 F6ADDD F6 F8 F2




FU Int

Issue 2nd LD or MULT?




LD F6 34 R2 1 2 3 4LD F2 45 R3MULTD F0 F2 F4 Clock 4SUBD F8 F6 F2DIVD F10 F0 F6ADDD F6 F8 F2


Name Busy Op Fi Fj Fk Qj Qk Rj RkInteger Yes Load F6 R2 NoMult1 NoMult2 NoAdd NoDivide No


FU Int

Yes




LD F6 34 R2 1 2 3 4LD F2 45 R3 5MULTD F0 F2 F4 Clock 5SUBD F8 F6 F2DIVD F10 F0 F6ADDD F6 F8 F2




FU Int

SUPERSCALAR: Issue MULTD?




LD F6 34 R2 1 2 3 4LD F2 45 R3 5 6MULTD F0 F2 F4 6 Clock 6SUBD F8 F6 F2DIVD F10 F0 F6ADDD F6 F8 F2


Name Busy Op Fi Fj Fk Qj Qk Rj RkInteger Yes Load F2 R3 YesMult1 Yes Mult F0 F2 F4 Int No YesMult2 NoAdd NoDivide No


FU Mult1 Int




LD F6 34 R2 1 2 3 4LD F2 45 R3 5 6 7MULTD F0 F2 F4 6 Clock 7SUBD F8 F6 F2 7DIVD F10 F0 F6ADDD F6 F8 F2


Name Busy Op Fi Fj Fk Qj Qk Rj RkInteger Yes Load F2 R3 NoMult1 Yes Mult F0 F2 F4 Int No YesMult2 NoAdd Yes Sub F8 F6 F2 Int Yes NoDivide No


FU Mult1 Int Add

Read multiply operands? DIVD could have been issued on this cycle.


Scoreboard Example Cycle 8aInstruction status Read Execution Write


LD F6 34 R2 1 2 3 4LD F2 45 R3 5 6 7MULTD F0 F2 F4 6 Clock 8SUBD F8 F6 F2 7DIVD F10 F0 F6 8ADDD F6 F8 F2


Name Busy Op Fi Fj Fk Qj Qk Rj RkInteger Yes Load F2 R3 YesMult1 Yes Mult F0 F2 F4 Int No YesMult2 NoAdd Yes Sub F8 F6 F2 Int Yes NoDivide Yes Div F10 F0 F6 Mult1 No Yes


FU Mult1 Int Add Div


Scoreboard Example Cycle 8bInstruction status Read Execution Write


LD F6 34 R2 1 2 3 4LD F2 45 R3 5 6 7 8MULTD F0 F2 F4 6 Clock 8SUBD F8 F6 F2 7DIVD F10 F0 F6 8ADDD F6 F8 F2


Name Busy Op Fi Fj Fk Qj Qk Rj RkInteger NoMult1 Yes Mult F0 F2 F4 Yes YesMult2 NoAdd Yes Sub F8 F6 F2 Yes YesDivide Yes Div F10 F0 F6 Mult1 No Yes


FU Mult1 Add Div




LD F6 34 R2 1 2 3 4LD F2 45 R3 5 6 7 8MULTD F0 F2 F4 6 9 Clock 9SUBD F8 F6 F2 7 9DIVD F10 F0 F6 8ADDD F6 F8 F2




FU Mult1 Add Div

Issue ADDD?




LD F6 34 R2 1 2 3 4LD F2 45 R3 5 6 7 8MULTD F0 F2 F4 6 9 Clock 11SUBD F8 F6 F2 7 9 11DIVD F10 F0 F6 8ADDD F6 F8 F2




FU Mult1 Add Div




LD F6 34 R2 1 2 3 4LD F2 45 R3 5 6 7 8MULTD F0 F2 F4 6 9 Clock 12SUBD F8 F6 F2 7 9 11 12DIVD F10 F0 F6 8ADDD F6 F8 F2


Name Busy Op Fi Fj Fk Qj Qk Rj RkInteger NoMult1 Yes Mult F0 F2 F4 Yes YesMult2 NoAdd NoDivide Yes Div F10 F0 F6 Mult1 No Yes


FU Mult1 Div




LD F6 34 R2 1 2 3 4LD F2 45 R3 5 6 7 8MULTD F0 F2 F4 6 9 Clock 13SUBD F8 F6 F2 7 9 11 12DIVD F10 F0 F6 8ADDD F6 F8 F2 13


Name Busy Op Fi Fj Fk Qj Qk Rj RkInteger NoMult1 Yes Mult F0 F2 F4 Yes YesMult2 NoAdd Yes Add F6 F8 F2 Yes YesDivide Yes Div F10 F0 F6 Mult1 No Yes


FU Mult1 Add Div


Pipelining Functional Units

• Would add multiple ‘virtual’ FUs to scoreboard

• Lower hardware cost than multiple actual units

• Inherently avoids WAW

• Bubbles are inserted at Issue and Read-Op

• Works best with more actual registers

• Consider the example from the book:

– Mult 1&2 are a two stage pipeline


Superscalar: Multiple Issues per cycle

• Very tedious

• ENSURE in order issue to avoid hazards

– Issuing hardware has to have ‘look-ahead’ hardware

• Works best with multiple internally pipelined Fus

• Consider:

DIV.D F0, F2, F4

ADD.D F10, F0, F8

SUB.D F8, F8, F14


Exceptions

• Imprecise due to out-of-order execution

• Improved by keeping track of recently executed instructions:

– Instructions are ‘retired’ in order

– Synchronous exceptions raised at retirement

– Operating system responsible for recovery

• Non-fatal Asynchronous exceptions let pipeline and scoreboard run empty before context switch.

• Trap/INT instructions (system calls) require context switch.

• On context switch, pipeline and scoreboard is run empty.


Scoreboarding Summary

• Limitations of CDC 6600 scoreboard

– No forwarding hardware

– Limited to instructions in basic block (small window)

– Small number of functional units (structural hazards), especially integer/load/store units

– Do not issue if structural or WAW hazards

– Wait for WAR hazards

– Imprecise exceptions

• Key idea: Allow instructions behind stall to proceed

– Decode issue instructions and read operands

– Enables out-of-order execution out-of-order completion


Scoreboarding Summary

• Modern Day Improvements:

– All operands are cached as soon as available

– Forwarding

– Pipelining Functional Units

– Microcoding, eg. IA32 (widens execution window)

– More precise exceptions

– In order retirement

– Works best with tons of actual registers

• Tomasulo approach:

– Reservation stations vs. Forwarding and Caching

– Temporary Registers work as many virtual registers

Documents

ENGS 116 Lecture 71 Scoreboarding Vincent H. Berk October 8, 2008 Reading for today: A.5 – A.6, article: Smith&Pleszkun FRIDAY: NO CLASS Reading for Monday: