School of Engineering

Australian National University

ENGN3213

Digital Systems & Microprocessors

Reverse Polish Calculator Project

V1.1Copyright 2009-2010 ANU College of Engineering and Computer Science

1

Contents

1 Introduction 3

2 Reverse Polish Notation 4

2.1 History of Reverse Polish . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.2 Reverse Polish Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.3 The Memory Device in Reverse Polish . . . . . . . . . . . . . . . . . . . . 6

2.4 The HP-35 Reversal Polish Algorithm . . . . . . . . . . . . . . . . . . . . . 9

3 RPC Design and Specification 11

3.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.1.1 Spartan 3E Board Peripherals . . . . . . . . . . . . . . . . . . . . . 11

3.2 The PS/2 Keyboard Interface . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.3 The Liquid Crystal Display Interface . . . . . . . . . . . . . . . . . . . . . 13

3.4 RTL design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4 Project Details 16

4.1 Keyboard and LCD Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.2 Implementation Levels of the RP Engine . . . . . . . . . . . . . . . . . . . 17

4.2.1 RP Engine Level I . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.2.2 RP Engine Level II . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.2.3 RP Engine Level III . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.3 Project Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

A Frequenctly Asked Questions 23

2

1 Introduction

In this course I have emphasised the Register Transfer Level (RTL) description ofcomplex digital systems. An early example of the technique was demonstrated in thedesign and implementation of the MU0 microprocessor (described in detail in CLAB3).By now you should be familiar with the details of the operation of MU0 and ready toapply a similar approach to other problems. The design and operation of MU0 is the bestindicator so far of how you should approach the present project. In the labs, you havealso been learning how to implement designs in hardware and you are now ready for arather complex design of your own.

Both this project and the wireless terminal project involve a system design and buildcomponent based on either an RTL model or a datapath model and an interfacingcomponent. The keyboard is used in both projects and is provided in the course asan example of interfacing between an FPGA and an external peripheral using a serialprotocol. In the WT project the interfacing exercise involves a VGA monitor. Thisproject involves a Liquid Crystal Display (LCD).

The project will give you the opportunity to use the RTL technique for the design of asystem of modest complexity: a reverse polish calculator with 14 significant decimaldigits. The project has various milestones among the specifications to allow you to do atop-down design and to tackle the project at various levels of complexity with plenty ofscope for individual creativity. A major aspect of the project will be to explore differentapproaches to hardware block design in order to trade size and speed.

Additional information can be found on the course website:

http://engnet.anu.edu.au/DEcourses/engn3213/Documents/PROJECT_DOCUMENTATION/

3

2 Reverse Polish Notation

2.1 History of Reverse Polish

Reverse polish notation or RPN is an arithmetic notation introduced by the Polish math-emetician Jan Lukasiewicz in 1920. During the 1960s and 1970s, RPN was widely usedin scientific calculators. The Hewlett-Packard HP-35, shown in Figure 1 was the world’sfirst handheld scientific calculator (1972) and was based on RPN ([?]).

Figure 1: The HP 35 calculator.

The arrival of the HP-35 was a significant event given the market dominance of slide rulesand mechanical calculators for engineering computations. The HP-35 used a traditionalfloating decimal display that automatically switched to scientific notation. The fifteendigit LED display was capable of displaying a 10 digit mantissa plus its sign and a dec-imal point and a two digit exponent plus its sign. The display was unique in that themultiplexing was designed to illuminate a single LED segment at a time, rather than asingle LED digit, because HP research had shown that this method was perceived by thehuman eye as brighter for equivalent power.

Architecturally, the calculator was a bit-serial machine that processed 56-bit floating-pointnumbers, representing 14-digit BCD (Binary Coded Decimal) numbers. Figure 2 showsthe main board of the HP-35. As you can see, integrated dual in-line was the technologyof the day.

4

Figure 2: The HP 35 main board.

2.2 Reverse Polish Notation

RPN is a simpler and more practical alternative to the conventional procedure for per-forming arithmetic calculations that we learned in school. The latter method is relianton the use of parentheses and equals signs and is sometimes referred to as infix notation.RPN is also referred to as postfix notation.

RPN is easiest to explain by example. Consider the following simple operation,

4 + 5 =

In RPN this expression is written,

5

4 ENTER 5 +

There is just one operation key referred to as “ENTER”. Computations are performedincrementally and results are stored in memory as we proceed. Here is a more complexexample,

(4 + 5 × 2) / 7 =

In RP we would do,

4 ENTER 5 ENTER 2 × + ENTER 7 /

Note the logical manner in which the calculation proceeds and how parentheses and equalssigns are eliminated. To do the project, you will need to familiarise yourself withReverse Polish notation.

2.3 The Memory Device in Reverse Polish

RP calculations require some form of limited memory to store variables and results. TheRP algorithm is suited to a special memory device referred to as a stack. A stack is acomputer term for a memory in which data is stored on a pile of registers. A stack isanalogous to a filing system in which the latest document to be filed is placed on top ofthe document pile.

A stack is a Last In First Out (LIFO) memory. When a variable is stored, it is pushedonto the stack. When a variable is to be retrieved, variables higher on the stack have tobe popped until we reach the desired variable. The stack does not need to be very deepi.e. have many memory locations. The HP 35 stack has only four levels.

To see how the stack would be used in RP, consider the following examples,

Example 1

(4 + 2 × 5) / (1 + 2 × 3)

In RPN this is described by,

6

4 ENTER 2 ENTER 5 × + ENTER 1 ENTER 2 ENTER 3 × + /

In the following table the S1-S4 refer to the stack register levels. The register S4 is at thetop of the stack in the document filing analogy. Hewlett-Packard [?] referred to it as thebottom of the stack. From now on I refer to this as the input to the stack in order toavoid confusion.

In the following example it is convenient to introduce an additional register that werefer to as the KEY HOLDING register (KHR). Though the KHR has no role inRP per se, it has several practical purposes here. One is to provide a register wherefinal output from the keyboard can be temporarily stored. Keyboards only provide onedigit at a time. Operands will therefore have to be built from digits prior to arithmeticprocessing. Another application of the KHR is that it makes it easier to implement aboveRP algorithm.

Exactly how you handle input from the keyboard for RP processing is one ofthe design decisions you will have to make in your project. You do not haveto use the KHR approach

Input: KHR S4 S3 S2 S14 4 . . . .

ENTER 4 4 . . .2 2 4 . . .

ENTER 2 2 4 . .5 5 2 4 . .* 10 4 . . .+ 14 . . . .

ENTER 14 14 . . .1 1 14 . . .

ENTER 1 1 14 . .2 2 1 14 . .

ENTER 2 2 1 14. .3 3 2 1 14. .* 6 1 14 . .+ 7 14 . . ./ 2 . . . .

The effect of ENTER is to push numbers onto the stack while leaving the current digitin the KHR. Note that in RPN operators are never stored on the stack. In the algorithmdescribed here the effect of an operator is that the RP controller pops the stack, triggersthe operation and places the result in the KHR.

7

In this implementation of RP, the ENTER key has to be pressed wheneverthere is further input after an operator so that the last result is stored on thestack and not overwritten by new input to the KHR. As we shall see, this choiceof implementation is by no means unique: the HP-35 handles the storage of prior resultsin a different manner.

Example 2

(-4 + 54) / (1 + 3 × (7+1))

In RPN this is described by,

4 CHS ENTER 54 PLUS ENTER 1 ENTER 3 ENTER 7 ENTER 1+ × + /

Input: KHR S4 S3 S2 S14 4 . . . .

CHS -4 . . . .ENTER -4 -4 . . .

54 54 -4 . . .+ 50 . . . .

ENTER 50 50 . . .1 1 50 . . .

ENTER 1 1 50 . .3 3 1 50 . .

ENTER 3 3 1 50 .7 7 3 1 50 .

ENTER 7 7 3 1 501 1 7 3 1 50+ 8 3 1 50 .* 24 1 50 . .+ 25 50 . . ./ 2 . . . .

It should be clear from this example that in any RP calculation you will neverneed to access variables lower than the top level of the stack.

8

2.4 The HP-35 Reversal Polish Algorithm

The following discussion follows articles from the Hewlett-Packard journal describing theHP-35 calculator ([?], [?]). Fig. 3 shows the instructions sticker posted on the back ofthe calculator and Fig. 4 shows the HP-35 implementation of the RP algorithm.

Figure 3: The HP 35 instruction sticker.

As you can see the HP implementation differs in a couple of ways from the version pre-sented above. Firstly the KHR in a HP-35 is actually the input register to the stack,X (see Fig. 4) (the display being connected to this register). Secondly, after an op-eration is executed, results are pushed onto the stack without the need for an ENTERkey. Actually the HP-35 algorithm does allow the user to press the ENTER key after anoperator. However this has exactly the same effect as not pressing the ENTERN key: soit is probably ignored. The reason for this design decision appears to be to reduce thenumber of ENTER key strokes used in lengthy calculations. In my experience one of theweaknesses in the engineering of the HP RP calculators was the tendancy of keys to stickafter extended use.

9

Figure 4: The HP-35 RP implementation explained.

10

3 RPC Design and Specification

3.1 General

The overall block diagram of the project is shown in Figure 5.

Figure 5: Reverse polish calculator simplified block diagram

In addition to the reverse polish calculator RTL system (RP engine), the project alsoinvolves interfacing to a PS/2 AT keyboard and a liquid crystal display (LCD). Youshould treat the keyboard and LCD interfaces as separate design projects from the RTLdesign of the RP engine itself. In designing these three subsystems you will have to decidehow they will interface to each other. How you present data to the RP engine from thekeyboard affects the form and timing of the inputs to the RP engine. Similarly how youprocess data in the RP engine affects what type of decimal encoding has to be done beforethe LCD.

3.1.1 Spartan 3E Board Peripherals

Fig. 6 shows the Spartan 3E Starter board peripherals that will be used in the project.

I will leave it to you to decide how to deal with overflows. For example you may decideto display a row of 16 minus asterisks. Interestingly the HP-35 fails to handle over-flow properly. The HP-35 rounds overflowing results down to the maximum number9.999999999× 1099. Dividing any two numbers larger than this by each other produces a1.

The HP stack has four levels. The stack in the project (not including any KeyHolding Register) should be at least four levels deep.

11

Figure 6: S3E board showing the peripherals.

3.2 The PS/2 Keyboard Interface

The PS/2 keyboard has already been described in lectures. A good introduction to thePS/2 AT keyboard and its communications protocol can be found at

http://www.beyondlogic.org/keyboard/keybrd.htm

In the RPC project we will only use the numeric keypad shown in Figs 8 and 7.

The PS/2 keyboard interface involves two main parts.

1. A serial to parallel converter FSM that handles the PS/2 protocol.

2. An output buffer to make KEY data available in a suitable format to the RP engine.

A sample serial protocol and FSM is already available on the project website and youhave already used them in the labs. You are free to make use of these in the presentproject.

12

Figure 7: Keyboard showing the RP function keys.

Figure 8: Keyboard scan codes.

The form in which you provide the keyboard output influences the design of the RP RTLcontroller. For example we will provide the key identity in a coded format, KEY, (if a keyis pressed) or as a NOKEY symbol (if no key or a wrong key is pressed) on the posedgeof the RP system CLOCK. Using this technique, unused scan codes can be replaced withthe NOKEY code.

3.3 The Liquid Crystal Display Interface

The LCD driver will also include two parts.

1. A BCD (binary coded decimal) or other encoder to convert the RP engine’s chosennumber format into a form suitable for driving the display.

13

Figure 9: Keyboard serial protocol.

2. An LCD driver.

Dealing with the former issue is a big part of the project and the output format dependson the implementation level you are trying to achieve. You should already be familiarwith code capable of implementing the display anode and cathode driver.

Further descriptions of the keyboard and LCD interfaces can be found in the Spartan 3EStarter manual on the project website:

http://engnet.anu.edu.au/DEcourses/engn3213/Documents/FPGA/

Note that in the Spartan 3E Starter manual also contains a chapter on the VGA portwith further information relevant to the LCD.

3.4 RTL design

Given the implementation of the RP algorithm described above and following the RTLdescription of MU0, one may propose the RTL archotecture of the RP calculator shownin Fig. 10.

In this figure, the control path is a FSM (at the left) which has two inputs: the keyIDcode and a reset. The keyID and reset are synchronised to the RP engine system clock.From the above example of the KHR, exactly one keyID appears per positive clock edgefor each valid key. Otherwise a NOKEY is produced. The reset must be provided viaa separate input such as a PEGASUS board pushbutton and not from the keyboard sothat the calculator can be manually forced into the INIT state (commonly referred to as“switching on the calculator”).

The keyID inputs are analogous to the commands stored in memory in MU0. Thesedetermine the state transitions of the RP controller FSM.

The outputs of the controller are a bunch of enable and reset switches that control thehardware blocks of the data path. As is the case for MU0, there should no need tosend the data buses through the controller FSM (see Fig. 10.)

14

Key Holding Register (KHR)

Arithmetic Logic Unit

Stack OutStack In

FSM

Input

Output

ResetkeyID from KB interface

Display

Output

Output

Input

interface

Figure 10: Simplified RPN RTL control and data paths.

In addition, the data path consists of well defined hardware blocks. In thepresent example these are the key holding register, an arithmetic logic unit and astack.

15

4 Project Details

Now that we have an idea of what the project involves, let’s see what you have to do.The project will consist of a design and implementation of various RP calculators for theSpartan 3E Starter board with an XC3S500E FPGA (our target hardware). The aim willbe to design and implement a keyboard interface, a LCD interface and up to 3 designsand implementations of increasing complexity and functionality of the RP engine.

4.1 Keyboard and LCD Interfaces

These have to be fairly universal. The display interface must be capable of displayingdigits, decimal points and any other characters you think may be necessary at somelevel of RP engine implementation. The main requirement is that you meet theprecision standards specified so that the same outputs are produced for a givecombination of inputs to the calculator.

The KEY/NOKEY system is described in Fig. 11.

Keyboard interface

Keyboard data

Keyboard Clock

RP Sys Clk

KEY / NOKEY

NOKEYNOKEYKEY KEY

RP Sys Clk

Figure 11: Keyboard input and output formats. The timing diagram shows how thekeyboard interface outputs keys on the posedge of the RP system clock.

The following encodings may be used for the key IDs.

16

KeyID Representation

ZERO 5’h00ONE 5’h01TWO 5’h02

THREE 5’h03FOUR 5’h04FIVE 5’h05SIX 5’h06

SEVEN 5’h07EIGHT 5’h08NINE 5’h09

ENTER 5’h0ACHS 5’h1ACLX 5’h0BCLR 5’h1BPLUS 5’h0C

MINUS 5’h1CTIMES 5’h0D

DIV 5’h1DDP 5’h0E

NOKEY 5’h1E

4.2 Implementation Levels of the RP Engine

In the following sections different levels or versions of the RP engine are described. Thelevels correspond to increasingly complex implementations and improvements in function-ality of the calculator. The changes mainly affect the design of the arithmetic logic unit.It is not compulsory to attempt to design and implement each of these in the project, butlevel I is compulsory and levels II and III do attract 12 additional marks out of 40.

Make sure that you implement either the direct or the HP Reverse Polishalgorithm previously described. You must STRICTLY ADHERE to the key-board keys suggested as the hardware performance will be assessed by an RPcalculator test jig that sends keyboard commands in PS/2 protocol to yourcalculator via the PS/2 port on the S3E board (see section on assessment).

In short these levels are

1. A signed decimal integer calculator that does addition and subtraction.

2. A fixed point signed decimal calculator that also does multiplication and division.

3. A floating point signed decimal calculator that also does multiplication and division.

17

In order to obtain full marks in the project it will be necessary to completeboth of the more complex fixed and floating point implementations of theALU. Much of this requires a good understanding of number systems andrepresentations. Those who have not done the COMP2300 course may findthe following lecture notes useful.

http://cs.anu.edu.au/student/comp2300/lectures/

4.2.1 RP Engine Level I

This is the simplest level. We confine ourselves to decimal integer addition and subtrac-tion. Key functions will be entered from the PS/2 keyboard and will be displayed on theLCD display. To illustrate the functionality at this level consider Figure 12 showing thefront panel of a HP-35 calculator. The relevant keys are shown inside the yellow square.

Figure 12: HP-35 functionality for the level I system.

The large blue key on the top left is the ENTER key. The operator keys − and + are inblue at the left. The CHS button changes the sign of the current number on the displayand CLX clears the display to a 0. The CLR key clears the stack. At this level we willnot implement the keys that have a red cross through them. These include, among many

18

others, the EEX key which converts a number to scientific notation, the PI key whichstores the number π and the decimal point key.

The following table shows the meaning and AT keyboard designations of the HP-35 keysof Figure 12.

RP FUNCTION KEYBOARD DESIGNATION Result

ENTER Enter Key Store on stack

−′′−

′′ Subtract

+ ′′+′′ Add

CHS “Num” Change sign of last number entered

CLX “Del” Clear the display to 0.

CLR “Ins” Clear all stack levels to 0.

At this level you develop your basic RTL design. This is the most importantproject milestone. Try to make it extensible to the more complex designs.The precision is to be the full 14.0.

4.2.2 RP Engine Level II

The aim is to implement fixed point arithmetic with fractional decimals: a very commonfunctionality in digital systems such as data radios and MPEG codecs. Fig. 13 showsthe HP-35 keys.

At this level we include multiplication, division and a fixed decimal point inthe middle of the display. The precision is 7.7.

The following table shows the meaning and keyboard designations of the HP-35 keys ofFigure 13.

19

Figure 13: HP-35 functionality for the level II and III systems.

RP FUNCTION KEYBOARD DESIGNATION Result

ENTER Enter Key Store on stack

−′′−

′′ Subtract

+ ′′+′′ Add

×′′∗′′ Multiply

/ ′′/′′ Divide

. “.” Decimal point

CHS “Num” Change sign of last number entered

CLX “Del” Clear the display to 0.

CLR “Ins” Clear all stack levels to 0.

20

4.2.3 RP Engine Level III

We aim to implement floating point arithmetic (without scientific notation). The float-ing decimal point in the result adjusts itself to the appropriate position on the display.Floating point will allow us to multiply decimal numbers with larger dynamic range thanfixed point.

The precision is 14 digits maximum before the decimal point and 13 digitsmaximum after the decimal point.

Since we will not implement exponents, the HP-35 functionality is the same as in Fig. 13followed by the same table above showing the keyboard designations.

4.3 Project Rules

This project leaves plenty of scope for individual creativity. You do not have to followthe exact procedure described above for the RTL design. If you do choose to be creativein your coding style then I expect a solid justification in terms of theory and synthesisedhardware.

The following are the project rules.

1. You must work alone.

2. You must follow the design conventions introduced in this document and the VER-ILOG coding style introduced in the course.

3. The length of the report should be < 20 pages. There is no pressure to produce abig report and there will be no penalties for exceeding the limit.

4. For testing purposes we do not require your bit files. We will need a folder containingthe VERILOG modules in a suitable form for loading directly into ISE WebPACK9.2i. The design flow should execute continuously and free of errors. We should nothave to do any PIN assignments. Consequently you must provide a suitable UserConstraints File (UCF) in each of your source folders. You must check that thedesign flow works from scratch in each new project in ISE WePACK 9.2i BEFORE

you upload your code.

5. Hand in separate project source code and UCF files in separate folders for each oflevels I,II and III ready for design flow implementation.

6. Upload to WATTLE the report in PDF format and the code in ZIP format. Use thefollowing naming conventions: RPC-REPORT-UXXXXXX-NAME-ENGN3213-2010.pdfand RPC-CODE-UXXXXXX-NAME-ENGN3213-2010.zip

21

7. You may not use any third party code. All VERILOG code is to bethe original work of the student save code offered for general use in thecourse. You cannot use PICOBLAZE. If you think you need a Xilinx IP-core thencheck with me first.

8. The project is worth 40% of the final mark and must be handed in to meby C.O.B Friday June 4.

9. 20% off per day for late submissions.

22

A Frequenctly Asked Questions

1. Am I allowed to use Xilinx IP-Cores in the project? No. The project is restrictedto student and lecturer posted VERILOG code.

2. Am I allowed to use PICOBLAZE?

The course document states that OPEN source code is not permitted.

3. What version of ISE will the RPC tests use.

ISE WebPACK Version 9.2i

4. Fixed-point. How do you want us to enter values? If we left-justify everything asthe HP-35 did, then what happens if someone enters ”1.2”? Should the point bemoved (so it’s no longer in the middle, but the number remains left-justified) orshould the display automatically change to show ”01.2”?

Fixed point in the doc spec says XX.XX. When you press ”2.1” you get ”02.10”on the display. When you press ”2 ENTER” you get ”02.00” on the display. Thedecimal point key would need to be used, as described in the project specification.

5. You mentioned earlier that if someone does a calculation on the one you wroteand then presses a number key, the result of the previous calculation is lost. HPautomatically push that value onto the stack instead. Which one do you want?

Since the project specification allows for the enter key to be pressed to chain calcu-lations (the direct algorithm), the HP algorithm with digit induced stack pushingwill not be tested.

6. Leading/trailing zeros, depending on left or right justification. Mine always displaystrailing zeros in floating-point mode (so 25 will be shown as 25.00) and both trailingand leading zeros in fixed-point mode (so 2.5 gets shown as 02.50).

This is fine, as long as the specified precision is displayed.

7. Rounding. Should the calculator perform rounding in any specific way?

Not specified, not tested.

8. Overflow handling. Should we follow HP’s example and display 9999 or just show—-?

Not specified, not tested.

9. Minimum stack size. The HP-35 had four including the Key Holding Register (andone more for permanent storage). The size required for testing needs to be de-fined, as well as information on whether that size includes the Key Holding Regis-ter/accumulator.

23

This has now been specified. You must use greater than or equal to four levels inaddition to any Key Holding Register. For example the following must give theresult 150.

50 ENTER 40 ENTER 30 ENTER 20 ENTER 10 + + + +

10. Do we have to handle negative zero in any particular way?

Once you derive zero its sign is irrelevant.

11. 0/0 handling. Does 0/0 = 1 (because anything divided by itself is 1), 0 (because 0divided by anything is 0), or error?

0/0 does not equal 1

12. Additional key presses once the Key Holding Register (if implemented) is full.Should typing 1234567890 result in only 1234 being stored, or only 7890 beingstored, or an error?

Not specified, not tested.

13. Key repeats. If a key is held down for a few seconds, should that fill up the displayas it does on a computer? Or should it just enter the key once? My HP-38G onlyenters a number once for each key press, so I’ve followed that.

One digit per key press.

14. Keyboard speed. Mine will refuse to accept keys closer than a few milliseconds apart(due to debouncing).

Explain it well in your project document.

15. Precision. Binary calculators will lose precision with certain values (eg. 0.01 in base10). Exactly what precision is required?

This is explicitly specified by the project document.

16. ”Unknown” key presses. A lot of people seem to be planning to implement mul-tiply/divide in the integer calculator. If the user sends a ”/” or ”*” key to thecalculator, should it do nothing at all (ie unknown key) or perform the operation?If the user just follows the exact assignment specification then it should do nothingbecause the assignment doesn’t require multiplication or division, but it seems sillyto ignore perfectly good operations.

Either would be fine, the document specified ”friendly”. But why waste time im-plementing something not assessed?

17. Does the ’clear stack’ key remove errors, or can that only be done with the resetbutton?

Error flags are not specified in the project document because error detection is notnecessary.

24

18. I heard that execution speed would be tested, but I can’t see how.

Execution speed is not being assessed.

19. Can I enter numbers that I cannot see on the display?

No

20. Are we correct in thinking that since the seven segment displays only have 4 digits,all our code should only bother working with 15 bits (214 = 16384, the lowest powerof 2 greater than 9999, and one bit for the sign?)

Not necessarily. The precision refers to the display. Thus 4.3 means up to foursignificant digits before the dp and up to 3 after the dp. Obviously you cannotachieve these independently. However for fixed point you can of course as you musthave two before and two after the dp under all conditions.

I think that the answer to your question depends on how you do your arithmetic. Ifyou work in BCD you will naturally be working with more bits due to its inefficientrepresentation . e.g. 0 (base 2) = 0000 (BCD).

In anycase division and multiplication will have other implications as well.

This is an important aspect of the project and I am supposing that projects willexhibit signifcant creativity and science in the solutions. I cannot wait to see youranswers!

21. Are we meant to hand in separate code for the levels 1, 2, and 3? Because the fixedand floating points implementations are mutually exclusive.

You must hand in three separate sets of source code and their UCF files. Thisfacilitates testing. The project rules now make this clear and also specify that UCFfiles should be provided so that the projects can be built from scratch. We do notwant your bit files.

25