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THE ENORMOUS SUCCESS IN increas-ing the speed and functionality ofelectronic devices over the past threedecades has been largely due to thegeometric scaling down of silicon (Si)complementary metal-oxide semicon-ductor (CMOS) transistors. Moore’sLaw, which states that the number oftransistors on a chip doubles every 18months, has, until now, held true,increasing both circuit complexity andfunctionality with each new genera-tion. The power consumption of achip decreases as the transistors getsmaller. At the same time, scaling hasreduced the cost per unit chip dramat-ically, and this economy of scale hasenabled microelectronics to be avail-able to all.

The basic functional relationship forCMOS is given in the equation below.The transistor performance can beimproved in three major ways: increas-ing the CMOS gate capacitance (Coxide),improving the carrier mobility (µ), ordecreasing the channel length (L). All ofthese methods increase the transistordrive current, which in turn improvesthe device’s speed

Idrive ∼ β

2∗ (Vg s − Vt )

2,

where

β = µ ∗ Coxide ∗ WL

Idrive = MOS current in saturationVgs = voltage from gate to sourceVt = threshold voltageµ = carrier mobilityCox = gate capacitanceW = channel widthL = channel length.Until recently, the main method of

increasing speed was by decreasing thechannel length (L) and gate thickness;this is called geometric scaling of transis-tors. However, for sub-100–nm channellengths, the physical and cost limitations

of scaling further have begun to takea toll on CMOS devices. Withsmaller transistors, the gateoxide becomes so thin thatcurrent begins to leakacross the gate evenwhen there is noapplied voltage. Inaddition, the cost ofmaking transistorssmaller and faster isbecoming prohibi-tive for chip manu-facturers. The explo-sive increase in com-puter applications,such as streamingvideo and digital movies,has raised the demand for

high-speed processing chips with lowerpower consumption. With geometric scal-ing of Si facing serious cost and technicalchallenges, the microelectronics industryhas been looking for alternate methods tocontinue the improvement of CMOSdevice performance. Carrier mobilityimprovement has been seen as one of thebest alternatives for faster devices atlower power levels. Strained Si is a tech-nology that involves physically stretchingor compressing the silicon crystal latticevia various means, which in turn increas-es carrier mobility and enhances the per-formance of the transitors without havingto make them smaller. Strained Sienhances the performance of CMOSdevices by increasing carrier mobilitywithout having to make them smaller. Asthe benefits to be gained from scalingtransistors continue to decrease, the com-mercial interest in using strained Si forCMOS devices has spiked. Additionally,strained Si still retains its integratability inCMOS manufacturing processes, unlikeany other semiconductor material.

The purpose of this article is toexplain the basics behind straining andreport on the current process technolo-gies available to strain CMOS devices.

How strained Si worksIn simple terms, a metal-oxide semi-

conductor field-effect transistor (MOS-FET), as shown in Fig. 1, is composed ofa conducting channel of n-type or p-typesemiconductor material (Si) controlledby an electrode called the gate and sepa-rated from the channel by a thin layer ofdielectric. A voltage applied to the gatecreates an electric field in the underlyingsilicon channel. The polarity of theapplied voltage on the gate turns theelectric field on or off and allows thecharge carriers (holes or electrons) totravel through the channel. Carriermobility describes the ease by whichcharge carriers drift through this channel.

At the molecular level, the channelresembles a crystal lattice. The speed atwhich charges move through this channelis dependant on this crystal structure.Straining Si involves ways of manipulatingthe silicon channel so as to improve itscarrier mobility. Putting a strain on a semi-conductor crystal can alter the structure,which in turn can alter the speed in a posi-tive way. Straining the lattice reduces theresistance to conduction of charge carriers.Charge carriers are thus allowed to flowmore easily through the crystal, increasingthe drive current of the transistor for thesame applied voltage. Drive current refersto the amount of current flowing fromsource to drain in a transistor. Higher drivecurrent makes the transistors switch faster,which translates to higher clock frequencyin integrated circuits (ICs).

Engineering strained silicon�looking back and into the futureTony Acosta and Sumant Sood

© STOCKBYTE

32 IEEE POTENTIALS

The change in carrierspeed depends on thedirection of strain as wellas the type of channel. Thetwo major types of inducedstrain are biaxial and uniax-ial. Biaxial strain was thefirst method to be investi-gated. The informationavailable on charge-carrierresponse to any givenstrain, biaxial or uniaxial, invarious directions is stillunder investigation. Muchof the science is in disputefrom research group toresearch group. A recentaccount of the effects ofstrain directionality is givenin Table 1. Here we seethat for nMOS devices, lon-gitudinal tensile strain(strain along the channel,making it longer) allowselectrons to move morequickly and smoothly,increasing the drive currentand thus improving transis-tor-switching speed. In thecase of pMOS devices,compressive strain alongthe channel (making itshorter) is the best way toenhance mobility.

Strain influences eachtype of charge carr ier(holes and electrons) differently. Inbiaxial tensile strain, the interatomicdistances in the silicon crystal arestretched, generally increasing themobility of electrons making n-typetransistors faster. P-type transistors, inwhich holes are the main charge carri-ers, are not significantly enhancedwith tensile stress and, in some cases,their mobility can be reduced. How-ever, the mobility of holes can beincreased dramatically by compressivestress; here the interatomic distancesare shortened.

Strain technologiesThe main challenge in straining Si

lies in the ability to successfully inte-grate it into current CMOS manufactur-ing processes while minimizing anydrastic increases in processing costs.An array of technologies used to strainSi has been developed for the produc-tion environment, and there are otherswith promise for the future. Of all thestrain technologies, uniaxial strain hasreceived the most attention since it out-

shines biaxial strain for the CMOS tran-sistors in terms of overall chip perfor-mance and yield. Pure biaxial strain hasyet to be introduced into CMOS-basedICs because the substrates are not yetproduced with tolerable defect densi-ties; hence yield problems restrict itscommercialization. Recent develop-ments have enabled the simultaneousuniaxial straining of both n- and p-channels on CMOS ICs by modifyingcurrent processing techniques.

Substrate strainSubstrate strain refers to incorporating

strain in Si prior to any device fabrication.The most established substrate strainmethod involves the use of a SiGe (Si-germanium) alloy. Amberwave Systems

pioneered the fabrication ofstrained Si substrate technolo-gy back in the 1990s andpresently conducts majorresearch in this area. In thismethod, an alloy of SiGe isfirst deposited onto a tradition-al Si substrate. The interatomicdistances of this layer are larg-er than those for a pure crystalof Si due to bigger lattice sizeof germanium as compared toSi. A very thin film of Si isthen grown on top of the SiGelayer. As the Si atoms settle,they take on the pattern of thealloy layer, and their latticedistance becomes larger thanit would be in pure Si,“stretching” the Si and thusincreasing the carrier mobility.A biaxially strained transistorschematic is shown in Fig. 2.The arrows show the directionof strain along the Si channeland perpendicular to it.Amberwave has reported thattransistors fabricated onstrained-Si substrates exhibit a17% increase in speed and a34% reduction in power con-sumption compared to circuitsfabricated with traditional Si.Despite this, defects and sub-sequent processing difficulties(Ge moves around the lattice

at normal IC processing temperatures)have prevented biaxial straining frombecoming a viable technology in main-stream IC manufacturing.

Process-induced strainSeveral approaches have been

attempted by IC manufacturers to incor-porate uniaxial strain into their currentfabrication processes. This method isknown as process-induced strain. Themost successful techniques includeshallow-trench isolation (STI), silicida-tion processes, Si nitride (Si3N4) caplayer, and embedded SiGe in thesource/drain regions of the transistor.

STI technology is normally used forlateral isolation between devices on theSi substrate. The STI etch process is

Fig. 1 Basic MOS transistor structure. L is the gate channel length,and Tox is the gate oxide thickness.

L

Tox

Channel

DrainSource

Gate Dielectric

Fig. 2 Traditional approach to biaxially strained silicon using SiGe

Biaxially Strained SiDrainSource

Bulk Si Substrate

Graded SiGe

Gate

Table 1. Type of stress needed for enhanced carrier mobility.

Direction nMOS pMOS

Longitudinal (along length of channel) Tension CompressionTransverse (along width of channel) Tension TensionOut of Plane Compression Tension

JULY/AUGUST 2006 33

used to create shallow trenches in theSi substrate, which are subsequentlyfilled with dielectric material to formisolation barriers between device ele-ments. Interestingly, decreasing the dis-tance between the STI edge and thetransistor region creates a compressivechannel between two trench structuresas shown in Fig. 3(c). This particulartechnique is used to increase the mobil-ity of pMOS devices.

Metal silicides like nickel silicide(NiSi2) can also be used to obtain com-pressive stress in the pMOS channel asa shown in Fig. 3(b). Silicides have ahigher thermal coefficient of expansionthan Si, and patterning them on the topof the pMOS transistors structuresqueezes the Si channel underneath,leading to higher hole mobility.

Intel introduced strained Si to its 90-nm process (used to manufacture Pen-tium IV and Centrino processors) vialocally straining nMOS and pMOSdevices using two separate techniques. Aselectively deposited SiGe source/drainstructure induces compression in thechannel in pMOS devices, improvinghole mobility. The larger lattice constant

of SiGe alloy at the source and drainsqueezes the pMOS channel creatingcompressive stress. On the other hand, atensile Si3N4 cap layer bonds compres-sively to the source and drain andstretches the nMOS channel, improvingelectron mobility relative to nonstraineddevices. A tensile Si nitride-capping layerused to create a stretched nMOS channelis shown in Fig. 3(a). Figure 3(d) showsan embedded SiGe source/drain processto create a compressive strain.

Another innovative way to introduceprocess-induced strain is the dual-stressliner (DSL) announced jointly by IBMand AMD for their current processes. Ituses deposited layers of Si nitrideinstead of SiGe source/drain regions. Sinitride (Si3N4) is a widely known mater-ial in the semiconductor industry andcan be used to produce either tensile orcompressive strain depending on itsdeposition conditions. In the processflow for this method, a highly tensile Sinitride layer is first deposited using ther-mal chemical vapor deposition over theentire wafer. The nitride layer is etchedaway from the areas containing p-typetransistors. A highly compressive Si3N4

layer is then deposited over the waferusing plasma-assisted chemical vapordeposition. This time, the nitride layeron the n-type transistors is etched away.The final result is a CMOS wafer wherethe n-type devices are stretched and thep-type devices are squeezed under com-pressive strain. An overall 24% improve-ment in transistor speed has beenreported using the DSL process.

Post-processing strain A third method of inducing stress in

CMOS devices advanced by BelfordResearch, Inc. involves straining the Silattice after the IC chips have been com-pletely processed. The process startswith thinning the processed wafer toultra thin dimensions of less than 10 µm,transferring it to a polymer film andthen mechanically straining the Si mem-brane. Membrane mechanics is some-what different to bulk behavior. In thesame way that optical fibers can be pro-duced from brittle glass, single crystal Sican be stretched without inducingdefects. Keeping within the elastic limit,the wafer can safely be mechanicallystrained and then bonded to a final

Fig. 3. Schematic features of various process straining technologies: (a) silicon nitride capping layer to create tensile strain innMOS, (b) silicide for compressive strain in pMOS, (c) Shallow Trench Isolation to create compressive strain in pMOS, and (d)embedded SiGe source/drain process for compressive strain in pMOS. (Used with permission, W. Chee et al., “Mobility-enhancement technologies" IEEE Circuits and Devices Magazine, May/June 2005.)

Gate Gate

GateGate

Silicide Silicide

Silicide

STI

STIStrained

ChannelStrainedChannel

StrainedChannel

StrainedChannel

SiGe SiGe

Si3N4

(a) (b)

(c) (d)

34 IEEE POTENTIALS

substrate using an adhesivewhere it is held in tension.The wafer is then diced intochips, each one of themunder biaxial strain as seenin Fig. 4. The arrows in the Xand Y direction show thedirection of strain. Themethod can be used foreither uniaxial or biaxialstrain. Device performanceimprovements in excess of100% via different strain vari-ations have been demonstrat-ed using this method. Thisstraining technique lookspromising and cost effective,but before it can be used forfull-scale IC manufacturing,yield and reliability issueswill need to be investigatedand resolved.

In addition to the aforementionedtechniques, orientation of the transistorson the Si substrate can also be used toimprove the overall performance ofstrained-Si transistors. The currentmicroelectronics industry standard is tofabricate CMOS chips on (100) orientat-ed Si. There is ongoing research by IBMinvestigating other crystallographic ori-entations to enhance transistor outputcharacteristics. Also called hybrid-orien-tation technology, the use of mixed-crystal orientation takes advantage ofthe fact that pMOS transistors operatebest when fabricated on Si with a (110)orientation, while nMOS transistorsoperate best with a (100) orientation.By combining strained Si transistorswith hybrid orientation, IBM researchershave shown an overall 22% perfor-mance gain.

ConclusionsStrained Si has emerged as a viable

technology to continue the historicalimprovement in CMOS devices. Anincrease in device speed of 50% by strain-induced enhancement equates to almostthree generations in alternative develop-ment in IC technology including scaling.Straining enhances the mobility of chargecarriers in the gate channel without theneed for scaling. Strained Si is still a verynew technology, and much will be doneto improve its implementation. The realtest for engineers lies in the ability to cost-effectively develop and apply strained Sitechnology into current CMOS processes.It is true that wafers incorporated withstrained Si generally have higher levels ofdefects than ones without strain. There-

fore, achieving higher levels of strainwithout compromising overall yield willbe a future challenge. Several strainingtechniques such as substrate strain,process-induced strain, and post-process-ing strain have already been developed toanswer this challenge. New andimproved methods for straining Si will beintegrated into IC manufacturing as indus-try interest in this technology continues togrow. This will ensure the increase inspeed, performance, and functionality ofCMOS ICs for future chip generations.

AcknowledgmentsThe authors would like to thank Dr.

Rona Belford, at Belford Research Inc., forher input and critical review of this article.

Read more about it• N. Mohta and S.E. Thompson,

“Mobility enhancement,” IEEE CircuitsDevices Mag., vol 21, no. 5, pp. 18–23,Sept.–Oct. 2005.

• W. Chee, S. Maikop, and C.-Y. Yu,“Mobility-enhancement technologies”IEEE Circuits Devices Mag., vol 21, no. 3,pp. 21–36, May-June 2005.

• “Strained Silicon yields transistorperformance gains,” [Online]. Available:http://www.intel.com/technology/sili-con/si12031.htm

• Amberwave Systems, presentationon strained silicon substrates [Online].Available: http://www.amberwave.com/resources/presentations.php

• T. Ghani, M Armstrong, C. Auth,M. Bost, P. Charvat, G. Glass, T. Hoff-man, K. Johnson, C. Kenyon, J. Klaus,B. McIntry, K. Misty, A. Murthy, J. Sand-ford, M. Silberstein, S. Silvakumar, P.

Smith, K. Zawadzki, S.thompson, and M. Bohr,“A 90nm high volumemanufacturing logic tech-nology featuring novel45nm gate length strainedsilicon CMOS transistors,”in Proc. IEDM, 2003, pp.978–980.

• B.M. Haugerud, L.A.Bosworth, and R.E.Belford, “Mechanicallyinduced strain enhance-ment of metal-oxide-semi-conductor field effect tran-sistors,” J. Appl. Phys., vol.94, no. 6, pp. 4102–4107,Sept. 15, 2003.

• C.H. Ge, C.C. Lin,C.H. Ko, C.C. Huang, Y.C.Huang, B.W. Chan, B.C.Perng, C.C. Sheu, P.Y.

Tsai, L.G. Yao, C.L. Wu, T.L. Lee, C.J.Chen, C.T. Wang, S.C. Lin, Y.C. Yeo,and C. Hu,“Process-strained Si (PSS)CMOS technology featuring 3D strainengineering,” Electron Devices Meeting,2003, Tech. Dig., Dec. 8–10, 2003, pp.3.7.1–3.7.4, .

• H.-S.P. Wong, “Beyond the conven-tional transistor,” IBM J. Res. Develop., vol.46, pp. 133–168, 2002 [Online]. Avail-a b l e : h t t p : / / w w w . r e s e a r c h .ibm.com/journal/rd/462/wong.html

About the authorsTony Acosta received his B.S. degree

in electrical engineering from the Geor-gia Institute of Technology in May 2005.While at Georgia Tech, he worked asan undergraduate research assistant forhis final three semesters at the Centerfor Organic Photonics and Electronics.Since May 2005, he has been a researchengineer at Belford Research, Inc.where his work primarily involvesdeveloping new processes for mechani-cally strained CMOS devices. Hisresearch interests include the researchand development of next-generationmicroelectronic devices.

Sumant Sood received his B.Tech. inelectrical engineering from PunjabTechnical University, India, in 2001 andM.S. in microelectronics from the Uni-versity of Central Florida in 2003. Hecurrently leads the National ScienceFoundation project team at BelfordResearch Inc. His research interestsinclude strained silicon, semiconductorwafer bonding, and strained silicon onInsulator (sSOI) devices. He is a Mem-ber of the IEEE.

Fig. 4 Mechanical straining of entire integrated circuit: uniaxial orbiaxial controlled strain is applied to ultrathin ICs attached to apolymer substrate

Chip

Polymer Substrate

Y

X