Energy Efficient Signaling in Deep-submicron Technology*

IMED BEN DHAOUa,†, KESHAB K. PARHIb,‡ and HANNU TENHUNENa

aDepartment of Electronics, Electronics System Design Laboratory, KTH-Electrum, Electrum-229 Royal Institute of Technology, SE-16440 Kista,Sweden; bDepartment of ECE, VLSI-DSP Lab, University of Minnesota, Minneapolis, MN 55455, USA

(Received 15 March 2001; Revised 30 January 2002)

In deep-submicron technology, global interconnect capacitances have started reaching several orders ofmagnitude greater than the intrinsic capacitances of the CMOS gates. The dynamic power consumptionof a CMOS gate driving a global wire is the sum of the power dissipated due to (dis)charging (i) theintrinsic capacitance of the gate, and (ii) the wire capacitance. The latter is referred to as on-chipsignaling power consumption.

In this paper, a scheme has been proposed for combating crosstalk noise and reducing powerconsumption while driving the global wire at an optimal delay. This scheme is based on reducedvoltage-swing signaling combined with buffer-insertion and resizing. The buffers are inserted andresized to compensate for the speed degradation caused by scaling the supply voltage and eradicatingthe crosstalk noise. A new buffer insertion algorithm called VIJIM has been described here, along withaccurate delay and crosstalk-noise estimation algorithms for distributed RLC wires.

The experimental results show that the VIJIM algorithm inserts fewer buffers into non-critical netsthan does the existing buffer-insertion algorithms. In a 0.25 mm CMOS process, the experimental resultsshow that energy savings of over 60% can be achived if the supply voltage is reduced from 2.5 to 1.5 V.

Keywords: Deep-submicron; Low-power design; Crosstalk noise; Interconnection delay; On-chipsignaling; Low swing signaling

INTRODUCTION

It is widely accepted that in deep-submicron CMOS

technology interconnects are a limiting factor for

achieving higher integration levels. This is because

transistor feature size is getting smaller, which results in

a lower parasitic capacitance (gate, drain and bulk

capacitances). Whereas, because of the decreasing spacing

between metal layers and the increasing number of

metalization levels, interconnect parasitics are increasing

as the technology scales down. Furthermore, as the

integration levels increase, the average wire length is

increasing steadily over time. In addition, the supply

voltage Vdd and the threshold voltage Vth of the transistor

are being aggressively scaled down. This results in a

lowering of the power dissipation of the CMOS gates

without degradation in speed. However, due to the effect

of the technology scaling, power and delay caused by

interconnect capacitance have begun to reach several

orders of magnitude larger than those attributed to

the intrinsic capacitance of the gates. Moreover, as a result

of the reducing Vdd and Vth, the noise margin, NM, of the

gates is decreasing as reported in Table I and in Ref. [19].

In Table I the parameters H and W represent the height and

width of the metal layer, respectively, where the spacing

between metal layers is assumed to be equal to W.

Due to the increasing integration density per standard

die size and the increasing metalization levels, noise in

DSM is increasing because of factors such as high number

of switching devices, high current density per unit area

and the increasing coupling noise between adjacent cells.

This is due to the decreasing spacing between metal layers

as shown in Table I. As a result it is expected that the

magnitude of crosstalk noise escalates as the technology

advances [2].

DSM noise has two negative impacts: (i) it causes

functional failure of the circuits by, e.g. inverting logic

levels or false switching of a quiet line which tends to

increase the glitch power consumption [12]; and (ii) it

increases the delay in the critical path of the circuits.

ISSN 1065-514X print/ISSN 1563-5171 online q 2002 Taylor & Francis Ltd

DOI: 10.1080/1065514021000012192

*Manuscript received March 30, 2001; revised October 31, 2001; edited November 19, 2001. This research work was supported by the SwedishFoundation for Strategic Research, SSF, under contract number PCC-1001-04.

†Corresponding author. Tel.: þ46-8-970-4137. Fax: þ46-8-751-1793. E-mail: imed@ele.kth.se‡E-mail: parhi@ece.umn.edu

VLSI Design, 2002 Vol. 15 (3), pp. 563–586

Thus, performing noise analysis and avoidance earlier

began to become crucial in insuring a functionally correct

and low-cost design. Noise avoidance can be addressed in

hierarchical fashion, i.e. that is from algorithm, archi-

tecture, and circuit down to the layout level [15–17,19].

In Ref. [15] Algorithmic Noise Tolerance (ANT)

scheme that allows for low-energy implementation of

frequency selective filters in the presence of DSM noise is

proposed. This concept is very efficient, however, its chief

drawback is that it is only applicable to a class of DSP

algorithms, namely FIR filter.

In Ref. [19], circuit technique that enhances the noise

immunity of dynamic circuits was reported. This

technique permits a lowering of the supply voltage

without comprising the circuit invulnerability from DSM

noise. This is indeed a very appealing technique for

dynamic CMOS, however, the energy saving scheme

addresses only gate power consumption.

In Ref. [11] it was demonstrated that the power needed

for sending the signal over global wires had started to

reach several orders of magnitude greater than the power

consumed by the signaling gate. In Refs. [11,12], a

signaling scheme has been described based on low-voltage

signaling combined with buffer insertion. Buffer insertion

techniques have three ultimate goals: (i) to combat

crosstalk noise; (ii) to decrease the interconnection delay;

and (iii) to reduce the power consumption while driving

the interconnect at an optimum or a given delay budget.

In Ref. [11], these power-consumption problems were

thoroughly studied. The advantage of buffer insertion in

its ability to combat the speed loss caused by lowering the

supply voltage has been shown. These studies have been

extended to include inverter chains.

In Ref. [12], the potential of buffer insertion to combat

crosstalk noise has been shown and an heuristic algorithm

for buffer insertion that drives the interconnect at very

low-energy while still meeting the noise budget has been

derived.

This paper is a continuation of our previous works

[11,12]. The main contributions to the research field

contained in this paper are outlined below:

1. An accurate delay-estimation algorithm has been

presented for global wire modeled as a distributed

RLC network.

2. An accurate crosstalk-noise estimation algorithm has

been described.

3. Two buffer-insertion algorithms have been proposed,

one for delay optimization, and the other for noise

optimization.

The rest of the paper is organized as follows. In the

second section, the problem is formulated and our work is

put into perspective with existing approaches. In the fourth

section, an interconnection delay model is described and a

buffer insertion algorithm for delay optimization is

presented. This is followed by the derivation of a crosstalk

noise estimation model and then the description of buffer

insertion algorithm for noise optimization. Subsequently,

an heuristic algorithm for robust buffer insertion that

allows to drive the interconnect at reduced voltage swing

while meeting the delay and noise budgets is reported. In

the fifth section, the experimental results are described.

Finally, the sixth section concludes our paper.

ENERGY EFFICIENT ON-CHIP SIGNALING

Given two inverters, INV1 and INV2 communicating

through a wire of length d as shown in Fig. 1. Without loss

of generality, we approximate the wire by a lumped

capacitance of value Cw ¼ Cd; where C is the per-unit

value of the wire capacitance. According to [26] the load

seen by the driving inverter, INV1, can be given by

CL ¼

Cw

dC|{z}þCintr

Cdp1þ Cdn2

þ Cgp1þ Cgn2|fflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflffl{zfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflffl}; ð1Þ

where Cdp and Cgp are the drain and gate capacitance of

the PMOS transistor, respectively. The dynamic power

consumed by the driving inverter is given by

Pdriv ¼

Pðd;f Þ

af V2dddC|fflfflfflfflffl{zfflfflfflfflffl}þ

Pintr

af V2ddCintr|fflfflfflfflfflffl{zfflfflfflfflfflffl}; ð2Þ

where a is the switching probability, Pintr is the intrinsic

power consumption, and P(d, f ) is the power consumed

due to signaling over a wire of length d at a given

frequency f. The latter is referred to as on-chip signaling

power consumption [11].

Similarly to the expression for the dynamic power

consumption, the expression for the propagation delay is

TABLE I Projected technology parameters for DSM designs, asreported in Ref. [18], and the projected noise margin of an unloadedsymmetrical inverter

Tech. (mm) Vdd (V) Vth (V) H/W (mm) NM

0.25 2.5 0.625 0.5/0.3 1.090.18 1.8 0.450 0.46/0.23 0.780.13 1.5 0.375 0.34/0.17 0.650.10 1.2 0.3 0.26/0.13 0.520.07 0.9 0.225 0.2/0.1 0.390.05 0.7 0.175 0.14/0.07 0.3

FIGURE 1 Problem formulation for energy-efficient signaling in DSM.

I.B. DHAOU et al.564

found to be

tp ¼

tðdÞ

bCw

2Vdd|ffl{zffl}þtðintrÞ

bCintr

2Vdd|ffl{zffl}; ð3Þ

where b is given by Eq. (4) below.

b ¼Ltr

Wtr

1

k0nþ

1

3k0p

!; ð4Þ

and k 0n and k 0

p are, respectively, the transconductance of

the PMOS and NMOS transistor. Wtr and Ltr are,

respectively, the channel width and length of the NMOS

transistor, where it is assumed that the PMOS transistor is

three times wider than the NMOS transistor [26].

As the transistor feature sizes are decreasing, Cw is

getting higher than Cintr. Under these circumstances the

first-order approximation of power consumption and delay

of the driving inverter reduces to

Pdriv < a f V2dddC

tp < bdC2Vdd

8<: ð5Þ

Four important observations come into light from Eq. (5):

(i) the dynamic power consumption is proportional to the

square of the signaling voltage Vdd; (ii) the dynamic power

consumption is linearly proportional to the wire-length d;

(iii) the delay is inversely proportional to the size of the

inverter; and (iv) the delay is linearly proportional to the

wire-length, d and to Vdd when the interconnect is

modeled as lumped capacitance. In the case of an RC

interconnect, the interconnection delay is proportional to

the square of the wire length. However, for the case of

RLC transmission line, in Ref. [14], it was found that the

interconnection delay was linearly proportional to the

wire-length.

These observations reveal that the most efficient way of

saving power while driving the interconnect at the

optimum delay is to reduce the supply voltage Vdd.

However, this comes at the expense of an increased

propagation delay and reduced noise margin of the gate. In

order to tackle these problems, a buffer with an

appropriate size must be inserted. This problem is

formally described in the next section.

Problem Formulation

Consider a CMOS gate, referred to as a transmitter, that

sends signals to another CMOS gate situated at a distance

d from the transmitter. The medium used for signaling

between the transmitter and the receiver is the On-Chip

Interconnect (OCI). In order to define the efficiency of the

communication (signaling) between the transmitter and

the receiver, the following definition has been adopted.

Definition 1 Let st(t ) denote a transmitted signal, sr(t )

denote the received signal and d denote the propagation

delay of the signal st(t ) sent over a distance d, where d is

the distance between the receiver and the transmitter. The

communication between the transmitter and the receiver is

said to be perfect if and only if at the instant of time t the

received signal sr(t ) sent by the transmitter at t 2 d is

within the noise margins of the receiver, thereby satisfying

the following inequalities: jstðt 2 dÞ2 srðtÞj # NMH if

stðt 2 dÞ is a logic high or jstðt 2 dÞ2 srðtÞj # NML if

stðt 2 dÞ is a logic low [25].

If j ðd;DÞ is used to denote the energy required to send

the data over a distance d under a specific delay D then the

power saving in DSM can be formally described as the

optimization problem depicted in Fig. 2.

Related Work

A lot of effort has been recently devoted to addressing

the problem of “optimum” signaling over global wires.

The techniques addressing the problem are rigorously

reviewed below.

In Ref. [3], two buffer insertion algorithms that

minimize the power consumption while driving an

interconnect at a given delay budget have been described.

These algorithms compute the optimum inverter sizes,

{w1;w2; . . .;wn} such that the total energy consumption

(dynamic and static) is minimized and constrained by a

given delay budget. The first algorithm discussed is used

in semi-custom design, where the buffers are selected

from a buffer-library. The second algorithm is used in full-

custom design, where the buffer sizes are computed using

an optimization algorithm, based on the Lagrange

multiplier. It has been found that the non-constant tapper

buffer chain consumes less energy than the buffer chain

FIGURE 2 Parasitic capacitances of two inverter pairs communicating through a capacitive interconnect.

DEEP-SUBMICRON TECHNOLOGY 565

with a constant tapper factor equaling e. These buffer

insertion algorithms are very efficient for signaling over

capacitive interconnects.

In Ref. [4], the short-circuit power consumption for

signaling over resistive interconnect has been addressed,

and the following three different schemes for driving re-

sistive inter-connect were compared: (i) uniform repeaters

(ii) tapered buffers and (iii) tapered repeater buffers. It was

found that the uniform repeaters are more efficient than the

others. In order to save power, the approach proposed by

Adler et al. is to trade speed for power, and a maximum of

15% power saving has been saved at the expense of a 4%

increase in the propagation delay.

The aforementioned reports suffer from several

limitations. Firstly, the interconnect has been inadequately

modeled (e.g. lumped RC or purely capacitive inter-

connect). Secondly, locations of the buffers have been

computed without considering crosstalk noise. Lastly, the

power savings approach is to optimally select the number

and sizes of the repeaters.

The second problem in the last paragraph above has

been addressed in Ref. [5], where three algorithms for

buffer insertion have been described. The first algorithm

inserts buffers for delay optimization, the second

algorithm inserts buffers for noise optimization, finally,

the third algorithm, which a dynamic programming

algorithm, inserts buffers for both delay and noise

optimization. The third algorithm is an improvement of

the Van Ginneken’s algorithm [8]. The buffer insertion

algorithm for noise optimization uses the Devgan’s

crosstalk noise prediction algorithm [27], whereas the

buffer insertion algorithm for delay optimization is based

on the traditional Elmore delay. In addition, the wires have

been modeled as a lumped RC network. This work is the

first of its kind to address noise and delay optimization

based on buffer insertion. However, power-savings have

not been addressed. In addition the Devgan’s noise

estimation algorithm has been found in Ref. [28] to be

inefficient for some interconnect benchmark.

The buffer insertion algorithm for noise optimization

based on inaccurate crosstalk noise prediction algorithm

can have two negative impacts. If the noise prediction

algorithm is pessimistic then the buffer insertion algorithm

inserts more buffer than needed. This will certainly result

in an increased propagation delay, power consumption and

silicon area. On the contrary, if the noise prediction

algorithm is optimistic, then the buffer insertion algorithm

inserts less number of buffers than needed. Consequently,

the design will suffer from the presence of the noise.

Indeed, the experimental results reported in Ref. [5]

show that for some interconnect benchmarks, Devgan’s

algorithm is pessimistic which results in identifying 37

more nets with noise violations than the actual case.

In Refs. [9,10], the dynamic power consumed by a

driver while driving a global wire has been reduced by

scaling the supply-voltage. While a sizable power

reduction has been achieved, the speed degradation

caused by voltage scaling has not been properly addressed.

In addition, the scheme does not guarantee a perfect

communication, because the buffer locations (i.e. wire

segmenting) are computed without accounting for the

crosstalk noise.

In order to efficiently address the aforementioned

problems, in Ref. [12] an algorithm that solves the

optimization problem shown in Fig. 2 was described. The

cornerstone of the scheme is the reduced swing signaling

combined with repeaters insertion and resizing. The

estimation of the location of the buffers that takes into

account both crosstalk noise and delay is computed using

a heuristic algorithm called VIJIM. The interconnect has

been modeled as lumped RLC, and an algorithm for delay

estimation has been described. VIJIM uses the crosstalk

noise estimation described in Ref. [28]. However, the

deployed crosstalk noise estimation algorithm does not

take into account the inductive effect of the wire. In

addition, the wire in Ref. [11] is modeled as lumped RLC.

OPTIMUM SIGNALING OVER AN ON-CHIP

INTERCONNECT

The expression of D and j ðd;DÞ must be derived in order

in turn to be able to derive an algorithm for solving the

optimization problem OPT-SIG shown in Fig. 2. These

expressions depend on the interconnect parameters (R, L,

and C ) and the interconnect model (capacitive versus

distributed RLC versus lumped RLC). It also depends on

the number and sizes of the buffers used to drive the

interconnect at a given delay budget. The number and size

of the buffers are estimated based on the delay budget D.

In order to minimize the quantity j ðd;DÞ; the approach in

this work has been based on reduce voltage-swing

signaling. This, however, comes at the expense of an

increased propagation delay and decreased noise margin

of the buffer. As was explained earlier on, in order to

restore the speed, the approach adopted here has been to

properly resize the inverter. The optimum number of

inverter stages and the size of each inverter are computed

using the algorithm described in Ref. [11]. In order to

assess the efficiency of our proposed scheme, the

following signaling schemes have been implemented in

0.25mm, 2.5 V CMOS process using full-custom design;

(i) S1: full swing (2.5 V) [3,5]; (ii) S2: reduced swing

(1.5 V) [9,10]; and (iii) S3 reduced swing signaling (1.5 V)

driven by a buffer which is four times larger than the

minimum-sized buffer.

For each scheme, j (d ) and tp have been measured using

HSPICE simulator. The transistor is the BSIM3v3 MOS

model from UC Berkeley. The results are reported in

Table II. The comparison of energy-savings of S2 and S3

against S1 are given by z M15 and z R

15; respectively. The

delay reported by HSPICE for the three signaling schemes

S1, S2, and S3 is tabulated in Table III, where tpM25; tpM

15 and

tpR15; are, respectively, the delay of S1, S2 and S3. The

comparison of the speed degradations of S2, and S3 against

S1 are given by, respectively,h M15 andh R

15:Tables II and III

I.B. DHAOU et al.566

clearly show that our method achieves, on average, over

70% of energy savings without substantial speed

degradation.

In this section it has been shown by using closed-form

equations that the power consumed by an inverter (or

buffer) is the sum of the on-chip signaling power

consumption and the intrinsic power dissipation. It was

also found that the delay is the summation of the delay

caused by the intrinsic capacitance of the driver and the

delay caused by the wiring capacitance. Consequently, it

was argued that the most efficient way to reduce the on-

chip signaling power consumption under a given delay

constraint is to reduce the supply voltage that must be

combined with buffer resizing. The buffer resizing

compensates for the delay degradation caused by scaling

the supply voltage. The technique proposed in this section

is very efficient for signaling over capacitive wire in the

absence of crosstalk noise. However, this model may not

be that valid for contemporary and future technologies,

because the wire needs to be modeled as distributed RLC.

Additionally, after the detailed place and route, or even

after global routing, the OCI will be coupled to adjacent

wires. This suggests that a more robust buffer insertion

scheme that solves SIG-OPT must be developed. This is

the goal of the following sections.

ROBUST BUFFER INSERTION: THE VIJIM

ALGORITHM

The aim in this section is to provide answers to the

following questions: (i) what is the optimal wire-

segmenting strategy for delay optimization if the wire is

modeled as a distributed RLC network?; (ii) what is the

optimal buffer locations to suppress the crosstalk noise for

non-critical nets?; and (iii) what is the optimal locations,

number and sizes of the buffers that would allow voltage

scaling for critical nets that suffer from the presence of

crosstalk noise? In order to answer these questions, the

problem must be described in a mathematical way.

Consider a wire E of length d surrounded by Ne wires,

and denote this by Ee; i¼1;...;Ne: Let S0 and SI denote the

source and the sink nodes of the wire E. Without losing

generality, assume that S0 and SI are minimum sized

inverters. The optimum signaling scheme is an application

(function), denoted by M similarly to the notation used in

Ref. [5], that takes as input E and its surrounding wires

(Ee,i), delay constraint, D, the supply voltage Vdd, and the

noise margin h. Given these parameters, the algorithm

returns, as a result, the locations, number, and sizes of the

buffers. Thus, the application M is the solution of the

optimization problem OPT-SIG, shown in Fig. 2. In order

to solve the OPT-SIG, the first task is to derive a closed

form expression for j ðd;DÞ and for the interconnection

delay d.

Let Nb be the number of buffers to be placed on the

wire. Each buffer, bi, ;i [ {1; . . .;Nb} is located at a

distance db,i from the source node and has a width Wb, i.

Without loss of generality, we assume that the noise

margin of the buffers is constant. However, our approach

can be easily extended to handle the case of buffers with

different noise margins. The number of buffers Nb

depends on the wire-length, the crosstalk noise induced

into the wire and the delay budget D. Based on the alpha-

power-law-model, two delay constrained optimization

cases for computing the optimum number and sizes of

the buffers have been reported in Ref. [3]. In the next

section, we follow the same formulation, however, the

TABLE III Delay comparison of the signaling schemes S1, S2 and S3

Wire length (d ) in mm

Param. 0.1 0.5 0.8 1 1.5 2

tpM15ðnsÞ 0.31 1.02 1.5 1.89 2.75 3.48

tpR15ðnsÞ 0.18 0.41 0.57 0.67 0.94 1.2

tpM25ðnsÞ 0.16 0.53 0.79 0.97 1.42 1.86

hM15 83% 92% 93% 94% 93% 87%

hR15 8% 223% 228% 230% 233% 235%

TABLE II Energy efficiency of S1, S2 and S3

Wire length (d ) in mm

Param. 0.1 0.5 0.8 1 1.5 2

S3jM15ðfJÞ 0.18 2.44 5.79 8.92 21.33 38.36

S2jR15ðfJÞ 0.17 1.13 2.34 3.39 6.84 11.46

S1jM25ðfJÞ 0.3 3.87 9.12 13.84 29.9 52.35

zM15 241% 237% 236% 235% 228% 226%

zR15 242% 271% 274% 275% 277% 278%

DEEP-SUBMICRON TECHNOLOGY 567

long-channel model is used. In addition, a closed-form

expression for the short-circuit power consumption

described in Ref. [20] is utilized.

If we assume that Nb buffers have the same switching

activity a and work at the same clock speed f then the

power needed to send the signal from S0 to SI is accurately

modeled using Eq. (6)

Pðd;DÞ ¼ aCmin f V2dd

XNb

i¼1

Wb;i þ f t ðVdd

2 2VthÞ39XNb

i¼1

1

Wb;i; ð6Þ

where Cmin is the gate capacitance of the minimum sized

inverter, t is the slope of the input voltage, Vth is the

threshold voltage and 9 ¼ Ltr½ð1=k0nÞ þ ð1=3k0pÞ� (Cf.

Eq. (4)).

There are two solutions for OPT-SIG. The first solution

is to search for the optimum sizes of the buffers from a

given buffer library. This is a discrete non-linear

optimization problem that can be solved by, e.g.

exhaustive search if the number of buffers is reasonably

small, or can be further transformed into an ILP

optimization problem. This is the solution used in semi-

custom design. In full-custom design, OPT-SIG is solved

using Lagrange multipliers or heuristic algorithms, where

the buffer is designed based on the optimum value after it

is obtained.

The first task towards solving the OPT-SIG optimi-

zation problem is to partition the wire into an optimum

number of segment. Each wire-segment is then driven by a

buffer with an appropriate size. By using the Elmore delay,

it has been shown that in order to drive an interconnect at

an optimal delay the interconnect needs to be partitioned

in Nb þ 1 equally spaced segments if the buffer, the source

and the sink have the same electrical parameters. The

value of Nb is computed using a closed form expression

[6]. The algorithm described in Ref. [6] guarantees

optimum solution if the interconnect is modeled as a

distributed RC and the library contains one type of buffers.

However, this technique suffers from the following

limitations:

1. As was proved in Ref. [5] and experimentally shown

in Ref. [12] buffer insertion based on delay

optimization does not guarantee a perfect communi-

cation.

2. This results is not necessary true for the case of an

RLC interconnect.

3. It has been found in many published reports that

tapered buffer repeaters are more optimal than

uniform repeaters [3,7,11].

In the semi-custom design, the last point made above is

irrelevant, because the choice of the buffer sizes is limited

by the size given in the library.

In the work done here, the interest has been focused on a

full-custom design solution where the sizes of the buffers

are computed using the algorithm described in Ref. [13].

In order to derive the algorithm for buffer insertion

that solves OPT-SIG, accurate crosstalk noise and delay

estimation algorithms have been presented in the

subsequent sections. After that, two buffer insertion

algorithms for delay or noise optimization are described.

Interconnection Delay

If the interconnect is modeled as a distributed RLC circuit

is based on the two-poles approximation of the transfer

function of the RLC transmission line. The derivation

steps and the delay models are described in Appendix

A. The steps undertaken to obtain a closed form

expression of the interconnection delay are similar to

those used in Ref. [29].

The two main closed-form expressions for the

interconnection delay are given by Eqs. (7) and (9).

td ¼ 2Kr

b2

b1 2

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffib2

1 2 4b2

q ; ð7Þ

where Kr is given by

Kr ¼ log 1 þb1ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi

b21 2 4b2

q0B@

1CA: ð8Þ

td ¼fþ arccosðeÞ2 p

2l: ð9Þ

The selection of the appropriate equation for estimating

the interconnection delay is done in the following way. If

b21 $ 4b2 then the interconnection delay must be estimated

using Eq. (7); otherwise Eq. (9) must be used. In fact, in

the interconnect benchmarks used in this paper it was

found that b21 $ 4b2: Thus, in the sequel our objective is to

derive a buffer insertion algorithm for delay optimization

based on Eq. (7).

Problem 1 Given a wire of length d and a non-inverting

buffer that has a resistance Rb an intrinsic capacitance Cb

and an intrinsic delay Kb, provide a necessary and

sufficient condition that when the buffer is inserted, the

interconnection delay decreases.

Similarly, to the conditions given in Ref. [6], what is of

interest here is finding the conditons when it is worthwhile

inserting a buffer to reduce the interconnection delay. In

Ref. [6], the Elmore delay has been exercised to obtain

conditions for buffer insertion.

As mentioned above, the interconnect is assumed to

have real poles, thus, Eq. (7) is the best-suited model for

delay estimation. The problem is that Eq. (7) is a non-

linear equation and thus an approximated linear and

closed-form equation is needed in order to derive an

algorithm for buffer insertion.

I.B. DHAOU et al.568

An inspection of Eq. (7) reveals that in order to achieve

this goal, a simple expression must be found for Kr. In

Appendix A, an empirical value for Kr has been found to

be equal to 0.69 and therefore, Eq. (7) can be reduced to

Eq. (10).

td ¼1:38b2

b1 2

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffib2

1 2 4b2

q : ð10Þ

Once the approximated quasi-linear equation for Eq. (7)

was found, the goal is to obtain a linear relation between

the delay and the interconnect length. For that, the

following Lemma is needed.

Lemma 1 Given a wire of length d which is modeled as a

distributed RLC circuit. Assuming that the poles of its

approximated transfer function are real and that Eq. (10)

accurately estimates the interconnection delay, then its

delay can be reduced to

td ¼ 0:69b1: ð11Þ

Proof Consider the denominator given in Eq. (10). As s1

and s2 are real, b1 and b2 are positive defined real numbers,

then, b21 . 4b2;

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffib2

1 2 4b2

q¼ b1

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi1 2 4b2=b2

1

q; we know

that the first order polynomial approximation for the

function f ðxÞ ¼ffiffiffiffiffiffiffiffiffiffiffi1 þ x

p< 1 þ x=2 if 21 , x , þ1:

Thus,

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffib2

1 2 4b2

q¼ b1 2 2ðb2=b1Þ: If we substitute

this in Eq. (10), we obtain Eq. (11). This concludes the

proof. A

Theorem 1 Consider a wire E of length d driven by a

source that has a resistance R0. Let us assume that E is

terminated with a capacitance CL and let us further assume

that Eq. (11) accurately predicts the interconnection delay,

then the buffer b must be inserted whenever the inequality

(12) holds.

d .2RbC þ RCb 2 R0C þ

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi24R0RbC 2 þ 5R2

bC 2 þ 4RbRCCb þ S

qRC

;

ð12Þ

where S ¼ R2C2L 2 4RR0CLC þ 6RbRCCL þ 4KbRC; Kb,

Cb, Rb are, respectively, the intrinsic delay, capacitance,

and resistance of b.

Proof Let us assume that the buffer is located at a

distance x from the source (distance d 2 x to the sink), and

that the sink has an input capacitance denoted by CL as

shown in Fig. 3. The intrinsic delay of the source and sink

are denoted by Kb and Ks, respectively. The delay before

and after buffer insertion is, respectively, denoted by

tb and t, where the subscript b means “after” buffer

insertion. The expression for tb and t are given by,

respectively, Eqs. (13) and (14).

tb ¼ 0:69�x2 RC

2þ xðR0C þ RCbÞ þ R0Cb

þ Ks þ ðd 2 xÞ2RC

2þ 0:69ððd 2 xÞðRbC þ RCLÞ

þ RbCL þ KbÞ�: ð13Þ

t ¼ 0:69 d 2 RC

2þ dðR0C þ RCLÞ þ R0CL þ Ks

� �: ð14Þ

The optimum value for x, denoted by xopt is obtained by

solving ›tb=›x ¼ 0: The expression for xopt is given by

Eq. (15).

xopt ¼dRC þ RbC þ RCL 2 ðR0C þ RCbÞ

2RC: ð15Þ

If we substitute x by xopt in the expression of tb, the

condition tb . t is true if and only if the length of the

interconnect satisfies the inequality given by Eq. (16).

d .2RbC þ RCb 2 R0C þ

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi24R0RbC 2 þ 5R2

bC 2 þ 4RbRCCb þ S

qRC

;

ð16Þ

where S ¼ R2C2L 2 4RR0CLC þ 6RbRCCL þ 4KbRC:

This concludes the proof. A

Theorem 2 Consider a wire connecting two identical

buffers (source and sink). If the buffer is identical to the

source then it must be inserted half-way between the

source and the sink.

Proof If we replace CL by Cb and R0 by Rb in Eq. (15),

we obtain xopt ¼ d=2: This concludes the proof. A

In fact if the source, the sink and that buffers satisfy the

conditions given in Lemma 2, then given Nb buffers, the

optimum way to reduce the interconnection delay is to

place the buffer equidistant at xopt ¼ d=Nb þ 1:Based on the Elmore delay, in Ref. [6] it was shown that

the buffer b must be inserted along the wire E to reduce the

interconnection delay if the length of E satisfies the

following relation

d .Rb 2 R0

Rþ

Cb 2 CL

Cþ 2

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiRbCb þ Kb

RC

r: ð17Þ

If the wire E satisfies Eq. (17), then as in Ref. [6] it was

shown that the buffer must be placed at the optimum

location given by Eq. (18).

xA ¼d

2þ

Rb 2 R0

2Rþ

CL 2 Cb

2C; ð18Þ

FIGURE 3 Buffer insertion for delay optimization.

DEEP-SUBMICRON TECHNOLOGY 569

where the subscript “A” is used to refer to the buffer

location computed using Alpert’s algorithm.

Careful examination of Eqs. (15) and (18) shows that

indeed the two equations are identical. However, Eq. (15)

was obtained by finding an approximation of the

interconnection delay given in Eq. (18). The resulting

approximated equation is independent of the inductance.

This suggests that for certain interconnect topology, the

error between Eqs. (7) and (10) can be unacceptably high.

Figure 4 shows the impact of the inductance on the

interconnection delay. A rigorous analysis of the impact of

the inductance on the buffer insertion scheme and the

interconnection delay is reported in Ref. [14].

Under this circumstance, the buffer insertion algorithm

based on Eq. (15) (or Eq. (18)) can lead to a non-delay

optimized design. In order to tackle this problem, Eq. (7)

must be used to find xopt.

To summarize, ideally for a given wire of length d

modeled as a distributed RLC circuit, if the source and

the sink on the wire have different characteristics than the

buffer, then Eq. (16) must be recursively used to place the

buffers for delay optimization. Otherwise, the buffers

must be inserted equidistant onto the wire.

The chief drawback of the proposed buffer insertion is

that the placement of the buffer has been computed under

the assumption that the noise at the buffer locations

satisfies the perfect communication requirements. How-

ever, in order to guarantee a hazard free circuit, at each

buffer location the crosstalk noise must be checked. This

should be done with the help of the crosstalk noise

estimation algorithm. In the sequel, an efficient crosstalk

noise estimation algorithm is derived.

Efficient Crosstalk Estimation

The crosstalk noise is referred to as the noise induced by

an active line (called aggressor) into a quiet line (referred

to as victim). Over the last decade many efficient

algorithms for crosstalk noise estimation have been

reported, e.g. Refs. [24,27,28,30,31].

The crosstalk noise algorithm described in Ref. [28],

which is an improved version of the algorithm described in

Ref. [27], has been used in Ref. [12] to estimate the

location of the buffers. While the algorithms published

in Refs. [27,28,30,31] are very efficient when the

interconnect is modeled as distributed RC network, the

efficiency of these algorithms has not been assessed when

the interconnect is modeled as distributed RLC network.

Thus, the aim of this section is to quantify the impact of

the inductance on the crosstalk noise, then based on this,

derive a new efficient crosstalk noise estimation. The

derivation steps are described in Appendix B.

Consider two coupled interconnects of length d shown

in Fig. 5. Each wire is modeled as distributed RLC

network. Two adjacent wires are coupled via a coupling

capacitive. In Ref. [32], the validity of this model has been

experimentally checked using measured data from a

manufactured VLSI chip implemented in 0.25mm 2.5 V

CMOS process. The measured data has been compared

against HSPICE and the results showed a good agreement

between the HSPICE model and the measured data.

However, in Ref. [32] HSPICE has been used to

characterize the crosstalk noise for technology that has a

feature size below 0.25mm. A closed form expression for

the crosstalk noise is very useful for interconnect-driven

optimization such as routing and buffer insertion [21].

In order to quantify the effect of the inductance L on the

peak crosstalk noise, the interconnect shown in Fig. 5 has

been approximated by 10 ladder RC (referred to as M0)

and 10 ladder RLC (referred to as M1) network. The PUV

of L, C, Cc and R are, respectively, 0.321 nH/mm,

1.59V/mm, 0.156 and 0.156 pF/mm. The values of

the parameter were obtained using a field-solver as

described in [11]. By using VRCMAX and VRLCMAX to

FIGURE 4 Impact of the on-chip inductance (L ) on the crosstalk noise as a function of the wire-length d [ ½1 mm; 10 mm�: The upper curve plotsVRCMAX as a function of d, whereas the lower one plots VRLCMAX as a function of d.

I.B. DHAOU et al.570

denote the maximum crosstalk noise for M0 and M1,

respectively. Figure 6 shows a plotting of these

parameters as a function of the wire-length. The curves

for VRCMAX and VRLCMAX clearly show that in this

particular case the inductance increases the crosstalk

noise, consequently, the prediction model that does not

account for the on-chip inductance is an optimistic

estimator. The error of the prediction model can be

unacceptably high.

In Appendix B, the closed-form for the normalized

crosstalk noise, assuming that the aggressor and the victim

line are of same length (See Fig. 5), was found to be

VNðtpeakÞ ¼ 0:5 sþesþ1

tpeak 2 s2es21

tpeak

� �; ð19Þ

where tpeak is given by Eq. (20).

tpeak ¼ logsþ1 s

þ

s21 s2

� �1

sþ1 2 s21; ð20Þ

s21;2; and sþ1;2 are, respectively, the solution for the DFEs

given by Eqs. (37) and (38) in Appendix A.

If the net has multiple aggressors, the superposition

Theorem can be used to compute the maximum crosstalk

noise induced into it.

The chief advantage of Eq. (19) is that it accounts for

the driver’s resistance R0, the wire parasitics, i.e. R, L

and C, and the loading capacitance CL. In order to derive

a practical formula, the parameter b given by Eq. (21) has

been neglected.

b ¼ 22:3

Tr

; ð21Þ

where Tr is the rise time of the aggressor’s voltage.

In Ref. [27], Devgan derived a closed form equation for

the current induced by the aggressor coupled to the victim

net, which hereafter will be referred to as Devgan’s model.

Devgan’s noise model is given by Eq. (22).

IN ¼ dClm; ð22Þ

where d is the wire length, C is the per-unit value of the

wire capacitance, l is the ratio of the coupling to the wire

capacitance, and m is the slope of the aggressor net defined

as

mD¼

Vdd

Tr

; ð23Þ

where Tr is the rise-time of the signal.

It is clear from Eq. (22) that the induced current depends

on the wire length. This suggests that for a given net, which

is coupled to one or several aggressors, the magnitude of

the crosstalk noise can be unacceptably high that may

cause serious functional failure or increases the glitch

power consumption. In order to bring the noise under

control, in Ref. [5], a buffer insertion algorithm, named

BuffOpt, for noise optimization has been proposed.

FIGURE 6 Schematics of two coupled transmission lines.

FIGURE 5 Impact of the on-chip inductance (L ) on the interconnection delay. The interconnect is of length d ¼ 1 mm and has PUV C ¼ 5:16 pF=cm;R ¼ 35V=cm and L [ ½0; 156:15mH=cm�: The interconnect is driven by a source that has an output resistance of R0 ¼ 200V and terminated at acapacitance of CL ¼ 1 pF:

DEEP-SUBMICRON TECHNOLOGY 571

The idea behind BuffOpt is that for a given net which is

coupled to one or any aggressors, there is an optimal wire-

length beyond which the level of crosstalk noise becomes

larger than the noise margin of the circuit (h ). For the case

of a single net coupled to one aggressor, the necessary and

sufficient condition that the wire length must satisfy in

order to insert a buffer to wipe up the crosstalk noise is

given by Eq. (24).

d $ 2R0

Rþ

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiR0

R

� �2

þ2h

RClm

s; ð24Þ

where R0 is the driver’s resistance.

The advantage with Devgan’s noise model is that the

noise is linear on the interconnect length d. However, the

risk of using Eq. (22) is that for some interconnect

benchmarks the estimated crosstalk noise is several orders

of magnitude higher than the actual case. Which will

result in over buffering the net.

Indeed, in Ref. [28] it was found that using a 5 mm

length of wire that if the rise-time of the aggressor’s

voltage is 20 ps then the value of the crosstalk noise

estimated using Devgan’s algorithm is 55.82 V, whereas

the correct value is only 0.39 V. Although the authors of

Ref. [28] have proposed a more efficient crosstalk noise

estimation algorithm, since, the maximum error defined in

FIGURE 7 Pseudo-code for efficient buffer insertion algorithm for noise optimization.

I.B. DHAOU et al.572

Eq. (25) can be as high as 51%.

h ¼ 100wc 2 we

wc

; ð25Þ

where wc is the correct value and we is the estimated value.

Based on the p model of the interconnect a more accurate

formula for the crosstalk noise has been reported in

Ref. [30].

Robust and efficient buffer insertion for noise

optimization using our model, given by Eq. (19), is

based on a binary searching technique. The binary

searching algorithm works in the following way. Consider

a quiet wire Eq driven by source So and a sink Si that has an

input capacitance Csi. Consider also an aggressor wire Ea

driven by a source S0 that has a resistance R0 coupled to Eq

through a coupling capacitance that has an PUV denoted

by Cc. Given these conditions, denote the noise margin of

the sink placed on Eq by h. In order to insert the buffer

onto the quiet line, the estimated crosstalk noise using Eq.

(19), which will be denoted by vsi should be larger than h;

otherwise there is no need for buffer insertion. Let us

assume that the buffer has an input capacitance denoted by

Cb, the task of the buffer insertion algorithm is to find a

suitable location dopt for inserting the buffer. By letting

dmin be the length of the wire such that the estimated

crosstalk noise is less than h, and letting dmax be the

maximum distance such that the estimated noise is more

than h, then obviously dmin and dmax should satisfy the

relationship given by:

dmin # dmax þ L; ð26Þ

where L is a very small parameter that represents the

minimum distance between two buffers. If g is a

displacement parameter such that g , 1 and at the

initialization step, dmin is set to zero and dmax is set to d.

The crosstalk noise at dmin (dmax) is computed using

Eq. (19) by replacing d by dmin (dmax) and Csi by Cb. Let

vdmin and vdmax be, respectively, the noise at dmin and

dmax. If vmax . h and vmin , h then dmax ¼ dmax 2

g ðdmax 2 dminÞ: If vmax , h and vmin , h then dmax ¼

dmax þ g ðdmax 2 dminÞ and dmin ¼ dmax: These steps are

repeated until Eq. (26) becomes invalid. The pseudo-code

that inserts buffer for noise optimization, named efficient

BuffOpt is depicted in Fig. 7.

FIGURE 8 Pseudo-code for VIJIM algorithm.

DEEP-SUBMICRON TECHNOLOGY 573

VIJIM Algorithm

In the previous subsections, two algorithms for buffer

insertions were described. The first algorithm described in

section “Interconnection Delay” inserts buffers for delay

optimization, whereas the second algorithm described in

section “Efficient Crosstalk Estimation” inserts buffers for

noise optimization. For critical nets, an algorithm for

buffer insertion that optimizes both delay and noise

optimization must be used. That means, given a delay

budget D, if the buffer must be inserted at a location

dopt,time to satisfy the delay requirements then it may

happen that the level of the noise at dopt,time is more than

the noise margin of the buffer. In this case, the buffer must

be shifted to a distance dopt,noise which is smaller than

dopt,time.

In the “Energy Efficient On-chip Signaling” section it

was found that the power needed for signaling, which is

the power needed to transmit the signal over the wire of

length d, is proportional to the wire-length and

proportional to the square of the supply voltage. It was

suggested that the supply voltage must be reduced in order

to satisfy the delay budget while minimizing the power

dissipation. The potential of buffer resizing has been

shown in compensating for the delay degradation. The

closed form expression described in “Energy Efficient

On-chip Signaling” section are only valid for signaling

over capacitive wires. Therefore, the proposed delay and

buffer resizing algorithm cannot be efficient for signaling

over distributed RLC wire. The most efficient way to drive

a distributed RC wire at an optimal delay is hence reduced

to the problem of selecting an appropriate resizing

algorithm. In the following paragraph two popular

resizing algorithms are reviewed.

The concept of geometric ratio sizing is a well known

design technique for choosing buffer sizes. In Ref. [26],

a technique for choosing the number and sizes of

inverters to drive an interconnect wire at an optimal

delay has been demonstrated. By using simplified

inverter charging/discharging models, it was concluded

in Ref. [26] that successive inverters driving the

interconnect line should be sized up in a geometric

progression. According to this technique, assuming an

inverter of size (S ) is to drive a load of capacitance

CL, then the first driver/inverter of size say (S ) is

followed by uniformly spaced inverters of size

eS; e2S; e3S; . . .; enS: Where n ¼ log2ðCL=SCgÞ; and Cg

is the gate capacitance of a minimum sized inverter. It

was later proved in Ref. [13] that this technique cannot

achieve an optimal delay. By taking into account the

slope of the input signal as well as the RC interconnect

models and more exact behavior of inverter charging/

discharging equations, in Ref. [13] it was found that in

order to achieve an optimal delay, the inverters need to

be sized with a pseudo-fixed ratio. The pseudo ratio

should be of the form a £ ð1 þ eÞi for sizing stage i. This

implies that the inverter sizes will vary as, S; að1 þ eÞS;a2ð1 þ eÞ3 S; . . .; anð1 þ eÞnðnþ1Þ=2S: If the length of the

interconnect is d then the inverters need to be located

with uniform spacing d=n: In Ref. [13], a detailed

technique was then developed for minimal powered

chained-driver configuration for achieving a specified

delay. While this is our objective in this paper, we note

that the inductive effects and noise for buffer insertion

have been totally ignored in Ref. [13]. A robust

algorithm for buffer insertion that solves the optimiza-

tion problem given in Fig. 2 is described in Fig. 8

FIGURE 9 Comparison between VIJIM and BuffOpt of Ref. [5] for the case of normalized h ¼ 0:2; D ¼ 1; R ¼ 35V=cm; L ¼ 3:47 nH=cm; andC ¼ 5:16 pF=mm: These parameters are chosen from Table V where it is assumed that CL ¼ 153fF; Cc ¼ 2 £ C; R0 ¼ 2000; Cb ¼ 153fF; andd ¼ 1 mm: VIJIM algorithm inserts a buffer at 0.344 mm from the source, whereas BuffOpt inserts a buffer at 0.13 mm from R0. Before the buffer isinserted, the amplitude of the normalized crosstalk noise is ca. 0.24. After VIJIM and BuffOpt the amplitude of the normalized crosstalk noise has beenreduced to, respectively, 0.20 and 0.14.

I.B. DHAOU et al.574

The VIJIM algorithm relies on a well characterized

interconnect, an accurate delay estimation and an accurate

crosstalk noise estimation algorithms. These functions

are given as an argument to the VIJIM algorithm:

f-computeðdelay;OCI; a; bÞ and f-computeðnoise;

OCI; bÞ:

The VIJIM algorithm works as follows. At the ith

iteration, VIJIM algorithm uses a fast searching technique

to locate the “best” position of the ith buffer such that

the received signal from the ði 2 1Þ buffer Vi21 satisfies

the perfect communication and delay constraints

(see Definition 1). The location of the buffer is determined

within a given precision (s ) which can be set at the onset

of VIJIM. The convergence speed, which is the time

needed to locate bopt given a, of VIJIM depends on the

value of g. In other words, for a small value of steps VIJIM

estimates the location of the ith buffer with faster

convergence time provided the location of bopt is closer to

the initial position of b than to a. Given N possible

locations of a buffer to be placed on a net of length d,

VIJIM algorithm (and efficient BuffOpt) seeks the optimal

buffer location (dopt) in log2(N ) steps.

EXPERIMENTAL RESULTS

In the experiments carried out in this paper, the wire

resistance, capacitance and inductance (R, L and C ) are

obtained from the measurement results published in

Ref. [33]. A closed-form expression has been obtained

based on least-square estimation for R, L, and C as a

function of the wire-width (W ) is obtained. The results are

shown in Figs. 9–11. The expression for R, L and C are

given, respectively, by Eqs. (27)–(29).

R ¼ 53:93W 21:1048ðV=mmÞ: ð27Þ

L ¼ 0:728W 20:558ðnH=mmÞ: ð28Þ

C ¼ 43e24W þ 0:0165ðpF=mmÞ: ð29Þ

The second interconnect benchmarks are the PUV of R, C

and Cc of two adjacent M3 interconnect used in a real

microprocessor designed in 0.25mm CMOS process [30].

In order to estimate the on-chip inductance, we used a

practical formula that relates the capacitance to the

inductance which is described in Ref. [1]. The PUV

interconnect parameters are reported in Table IV. The third

FIGURE 10 Measured and estimated interconnect resistance as a function of the wire width.

FIGURE 11 Measured and estimated interconnect inductance as a function of the wire width.

DEEP-SUBMICRON TECHNOLOGY 575

interconnect benchmarks are the one published in Ref. [34]

and are presented in Table V.

Accuracy of the Delay Model

The delay estimation algorithm has been implemented in

Cþþ . Each interconnect of length dp ¼ 10mm is

approximated by an RLC circuit of value Rp ¼ Rdp; Lp ¼

dpL and Cp ¼ Cdp: The delay estimation algorithms

given by Eqs. (7) and (9) have been compared to the delay

obtained (measured) using HSPICE simulator and the

Elmore delay. In addition, the delay models developed

here (Eqs. (7) and (9)) have been compared against

the delay model proposed by Ismail et al. referred to as

Yehea’s model [14]. For each delay model, the error is

computed using

Error ¼ 100jtspice 2 tj

tspice

; ð30Þ

where t is the estimated delay using Elmore, Yeheas’ or our

delay mode, and jxjmeans the absolute value of x. Table VI

compares our delay model (denoted by td) to Elmore delay

(denoted by tE) and HSPICE delay (denoted by tspice). The

interconnect parameters were the one reported in Ref. [33]

(see Eqs. (27)–(29). Tables VII and VIII compare the three

models: (i) Elmore delay, (ii) the delay model developed

here (given by Eq. (10)) and (iii) Yeheas’ delay model

(denoted by tY) to HSPICE delay.

In the interconnect benchmarks developed here, it was

found that b21 $ 4b2; which means that the interconnection

delay is given by Eq. (7). In order to compare Yehea’s

delay model and our model given by Eq. (9) to HSPICE, it

is important to find an interconnect benchmark such that

b21 , 4b2: Table IX reports the comparison of the three

delay model to HSPICE for the case when b21 , 4b2:

TABLE IV First interconnect benchmarks

Cases Width in mm Spacing in mm Length in mm R V C in fF Cc in fF L in fH

1 0.49 0.46 1000 122.9 63.2 115.2 0.6863 1 0.46 10000 605.63 983.97 1187.03 0.444 0.49 1.30 1000 122.9 109.3 46.2 0.397

TABLE V Typical per-unit-values of R, L, and C for 0.25mm CMOStechnology

Wire Width (mm) R (V/cm) L (nH/cm) C (pf/cm)

W1 0.9 494 4.75 1.73W2 1.8 248 3.70 1.85W3 2.4 76 5.3 2.6W4 7.5 35 3.47 5.16

Those interconnect parameters are published in Ref. [34].

TABLE VI Accuracy of the derived delay model for different interconnect parameters and CL ¼ 12fF

Source Res. R0 (in V) Wire width W (in mm) Int. length d in mm HSPICE delay tspice in ps Eq. (56) td in ps Elmore delay tE in ps

200 1.2 0.5 6.1 7.2 4.942000 1.2 0.5 36 32 46200 1.2 1 8.8 5.8 7.732000 1.2 1 52 47 68200 1.6 0.5 6.2 4.3 52000 1.6 0.5 38 33 47200 1.6 1 8.8 8.5 7.832000 1.6 1 54 49 71200 1.72 0.5 6.2 4.2 5.052000 1.72 0.5 38 33 48

The interconnect parameters are obtained from measurement results reported in Ref. [33].

TABLE VII Comparison between our delay estimation model andElmore’s delay model with the delay reported by HSPICE for aninterconnect that belongs to Case3 in Table IV

R0

(V) CL tspice in pstd

(Eq. (56))in ps tE in ps tY in ps

100 15fF 309.56 317.72 406.94 301.13100fF 354.47 363.27 466.92 345.52153fF 382 390.68 504.31 373.19

200 15fF 381.5 387.81 506.83 375.06100fF 432.4 439.82 575.31 425.73153fF 463.3 471.36 618 457.33

1000 15fF 938.83 939.36 1306 966.45100fF 1037 1039 1442 1067.4153fF 1099 1100 1527 1130.4

TABLE VIII Comparison of Yehea’s, Elmore’s, and our delay model tothe delay obtained using the HSPICE simulator

Wire R0 (V) tspice in ps td (Eq. (56)) in ps tE in ps tY in ps

W1 100 16.38 12.51 17.82 13.191000 122.22 120.09 171.09 126.61

W2 100 16.16 12.28 17.55 12.981000 122.82 119.17 171.9 127.2

W3 100 16.51 12.65 18.02 13.331000 128.21 124.17 179.12 132.55

W4 100 16.9 14.32 20.52 15.181000 133.63 141.8 204.66 151.45

The interconnect paramters are those given in Table V.

I.B. DHAOU et al.576

Finally, Table X reports a statistical comparison

between Elmore delay, Yehea’s and the model proposed

here. From the results presented in the aforementioned

table we found that our delay model has the lowest average

prediction error. However, Yehea’s delay model has the

lowest maximum prediction error.

Accuracy of the Crosstalk Noise Estimation Algorithm

In order to evaluate the accuracy of our noise model, the

crosstalk noise, denoted by VN is obtained using HSPICE

simulator. The interconnect is modeled as a distributed

RLC network. Each interconnect of length dp ¼ 10mm

is approximated by an RLC circuit of value Rp ¼ Rdp;Lp ¼ dpL and Cp ¼ Cdp: The resulting error between the

estimated crosstalk noise and the correct value, i.e. VN is

computed using Eq. (31).

hmodel ¼VN 2 Vmodel

VN

; ð31Þ

where “model” refers to as the crosstalk noise model and

Vmodel is the predicted crosstalk noise using “model”. Let

VN, VABK, and Vour be, respectively, the crosstalk noise

algorithm reported by HSPICE, the crosstalk noise

estimated using Kahng’s algorithm [30], and the crosstalk

noise estimated using our algorithm. The maximum

crosstalk noise occurs at some specific time. This time is

referred to as the peak time. Let tpeak, tABK and tour be,

respectively, the reported peak time obtained via HSPICE

simulator, the estimated peak time using Kahng’s

algorithm, and the peak time estimated using our

algorithm. Tables XI–XIII report the comparison between

Kahng’s and our crosstalk noise estimation algorithm

against HSPICE.

TABLE IX Comparison of Yehea’s, Elmore’s, and our delay modelagainst HSPICE delay, when s1 and s2 are complex numbers, as afunction of the loading capacitance and the driver’s resistance

R0

(V)CL

(pf/mm) tspice in nstd

(Eq. (9)) in ns tE in ns tY in ns

10 1e 2 3 0.155 0.141 0.025 0.16220e 2 3 0.156 0.142 0.025 0.163

2 0.21 0.226 0.045 0.21720 1 0.19 0.18 0.07 0.19

2 0.219 0.22 0.214 0.22112 0.457 0.447 0.29 0.388

30 1 0.199 0.183 0.105 0.1882 0.227 0.221 0.135 0.214

12 0.498 0.475 0.437 0.42

The parameters for the interconnect are the following: d ¼ 0:1 mm; R ¼ 2V=mm;L ¼ 0:1mH=mm; C ¼ 25 pF=mm; R0 ¼ 20V; and Tr ¼ 2 ns: Those are the sameparameters used to obtain Fig. 15.

TABLE X Statistical comparison of Elmore’s, Yehea’s, and our delaymodel

Delay model Min (ht) max (ht) mean (ht)

Our 0.056% 26.77% 6.42%Elmore’s 0.66% 83.97% 36.02%Yehea’s 0% 26.48% 6.6%

TABLE XI Comparison between the estimated normalized crosstalk reported in Ref. [30] and our model against HSPICE for the case of aninterconnect that belongs to Case1 in Table IV

R0 (V) CL VN VABK Vour hABK hour tpeak ( ps ) tABK ( ps ) tour ( ps )

100 15fF 0.258 0.128 0.261 50.21% 21.10% 22.25 18.21 21.48100fF 0.152 0.081 0.155 46.91% 21.87% 42.2 29.29 38.71153fF 0.122 0.066 0.124 45.75% 21.86% 47.2 35.68 47.88

200 15fF 0.249 0.09 0.25 63.62% 20.46% 37.2 23.32 35.8100fF 0.154 0.058 0.155 61.9% 20.93% 67.25 36.32 63.79153fF 0.125 0.048 0.126 61.27% 20.96% 82.25 43.79 79.15

1000 15fF 0.237 0.028 0.237 87.88% 20.12% 152.25 39.63 150.72100fF 0.155 0.019 0.156 87.45% 20.41% 262.25 60.11 260.74153fF 0.128 0.016 0.129 87.31% 20.50% 322.2 71.71 323.47

TABLE XII Comparison between the estimated normalized crosstalk reported in Ref. [30] and our model against HSPICE for the case of aninterconnect that belongs to Case3 in Table IV

R0 (V) CL VN VABK Vour hABK hour tpeak ( ps ) tABK ( ps ) tour ( ps )

100 15fF 0.26 0.197 0.276 24.20% 26.18% 597.25 586.41 565.21100fF 0.241 0.184 0.256 23.57% 26.12% 657.25 635.39 621.43153fF 0.231 0.178 0.245 23.17% 26.08% 687.2 665.26 653.73

200 15fF 0.253 0.168 0.263 33.44% 23.94% 752.2 710.89 726.55100fF 0.237 0.158 0.246 33% 23.95% 822.2 762.19 794.19153fF 0.228 0.153 0.237 32.74 23.97% 862.25 793.56 833.86

1000 15fF 0.227 0.083 0.228 63.18% 20.44% 2092 126 2088100fF 0.216 0.079 0.217 63.11% 20.46 2247 1329 2242153fF 0.21 0.077 0.211 63% 20.46% 2342 1372 2336

DEEP-SUBMICRON TECHNOLOGY 577

Robust Buffer Insertion

Buffers are inserted in a given net and its aggressors such

that the constraints depicted in Fig. 2 are met at the lowest

possible signaling power consumption. From the previous

experiments it is known that the crosstalk and inter-

connection delay estimation algorithms proposed here are

very accurate. Before we proceed into the description of

the results of energy efficient signaling, this would be an

appropriate moment to discuss the robustness of the

buffer-insertion scheme proposed here in the presence of

crosstalk noise without delay constraints that is with the

setting D ¼ 1 in VIJIM algorithm.

In the case of non-critical nets (i.e. D ¼ 1), there is no

need for buffer resizing which means the buffer resizing

algorithm must be halt. As a result, the VIJIM algorithm is

reduced to the efficient BuffOpt depicted in Fig. 7. For this

special case, the comparison between VIJIM and BuffOpt

of Ref. [5] is reported in Table XIV. Figure 12 shows the

impact of buffer insertion on the crosstalk noise using both

VIJIM and BuffOpt.

The following definition has been used to measure the

efficiency and robustness of the buffer-insertion algo-

rithms for noise estimation.

Definition 2 Consider the two algorithms denoted A1

and A2 that insert buffers for noise optimization. A1 is said

to be more efficient than A2 (or vice-versa) if A1 inserts

buffer at the optimal location, denoted by dopt such that

after buffer insertion the noise at dopt is equal or slightly

less than h.

From the results presented in Table XIV and Fig. 12 and

for large R0, we see that VIJIM is more efficient than

BuffOpt. This is because the noise metric used by BuffOpt

is too pessimistic. Thus, for special nets, this technique

would lead to a design that would suffer from an over

buffering. Which would unquestionably increase the cost

(silicon area and power dissipation) of the IC and may also

increase the power supply noise. For example, where R0 ¼

1000 or 2000 and if d ¼ 200mm and h ¼ 0:2 then the net

satisfies the noise budget requirements (see Table XIV).

That means there is no need for buffer insertion.

However, BuffOpt inserts buffer at the location where

dopt ¼ 130mm:The results described earlier in the evaluation of the

crosstalk noise estimation proposed here, reveal instead

TABLE XIII Comparison between the estimated normalized crosstalk reported in Ref. [30] and our model against HSPICE for the case of aninterconnect that belongs to Case4 in Table IV

R0 (V) CL VN VABK Vour hABK hour tpeak ( ps ) tABK ( ps ) tour ( ps )

100 15fF 0.111 0.06 0.112 245.9% 1.67% 27.25 16.76 23.9100fF 0.065 0.03 0.066 244.66% 1.94% 42.25 26.85 38.57153fF 0.051 0.028 0.052 243.92% 1.82% 47.25 32.89 46.95

200 15fF 0.107 0.042 0.107 260.86% 0.55% 42.25 21.05 40.03100fF 0.065 0.026 0.066 260.44% 0.95% 67.25 33.045 64.07153fF 0.052 0.021 0.053 260.09% 0.99% 77.25 40.13 78.18

1000 15fF 0.102 0.013 0.102 287.11% 0.12% 167.25 34.94 169.58100fF 0.066 0.008 0.066 287.06% 0.43% 262.25 54.05 264.63153fF 0.054 0.007 0.054 287.02% 0.52% 322.25 65.10 322.41

TABLE XIV Comparison of VIJIM against BuffOpt at the case when D ¼ 1 and the interconnect parameters are given by the column W1 in Table V

R0 (V) d (in mm) VN Vour hour VVIJIM VBuffOpt dVIJIM (in mm) dBuffOpt (in mm)

100 100 0.13 0.127 22.82% 0.13 0.13 – –200 0.179 0.171 24% 0.179 0.151 – 130500 0.238 0.219 27.8% 0.211 0.151 328 130

1000 0.255 0.242 25.29% 0.211 0.151 327 1301000 100 0.125 0.125 20.54% 0.125 0.125 – –

200 0.171 0.17 20.84% 0.171 0.143 – 130500 0.217 0.216 20.197% 0.2 0.143 344 130

1000 0.239 0.239 20.135% 0.2 0.143 344 1302000 100 0.126 0.1258 20.27% 0.126 0.126 – –

200 0.17 0.17 20.149% 0.17 0.143 – 130500 0.216 0.216 20.041% 0.2 0.143 344 130

1000 0.239 0.239 20.037% 0.2 0.143 344 130

The results are obtained by fixing CL and Cb to 0.135fF and the normalized h ¼ 0:2: The cell that contains “–” means that no buffer is inserted by the correspondingalgorithm.

FIGURE 12 Measured and estimated interconnect capacitance as afunction of the wire width.

I.B. DHAOU et al.578

that this underestimates the crosstalk noise. The maximum

of this estimation error is less than 10% (9.9%). Let us

denoted by hour the maximum under estimation error

which means that in our case hour ¼ 210%: If we assume

that the normalized noise margin is h, then VIJIM does

not insert a buffer if the estimated crosstalk noise, vmax

satisfies Eq. (32).

h # vmax # hð1 þ hourÞ: ð32Þ

From the results tabulated in Table XIV, we found that for

R0 ¼ 100 and for d ¼ 500mm or d ¼ 1000mm; VIJIM

inserts buffers at a non-optimal location, as the amplitude

of the crosstalk noise is still higher than h after buffer

insertion. In order to tackle this problem, the value of h in

the VIJIM algorithm is reduced from 0.2 to 0.18. The

results after this correction is reported in Table XV.

In order to minimize j ðd;DÞ; our approach is to select

the optimum supply voltage from a given set of possible

supply voltages. In our experiments, we are given three

supply voltages: 2.5 (full swing), 1.8 and 1.5 V. For each

wire length, the optimum location and sizes of the buffers

are computed using VIJIM. The resizing algorithm used in

this version of the VIJIM is the one proposed in Ref. [13].

The results, given in Table XVI, show that 1.5 V has the

lowest jðd;DÞ: This observation rises the following

question: why not just use the lowest supply voltage that

guarantees a perfect communication? In order to answer

this question, we have conducted the same experiments

using supply voltage equal to 1 V. The results, tabulated

in Table XVI, show that j15 is very close to j1. This is

because in order to compensate for the delay caused by

over scaling the supply voltage then more buffers are

needed if the supply voltage equals 1 V compared to the

case if the supply voltage is 1.5 V.

CONCLUSION

In this paper a scheme has been proposed for combating

crosstalk noise when driving an RLC wire at an optimal

delay or a given delay budget while reducing the on-chip

signaling power consumption. The core of this scheme is

low-voltage signaling combined with buffer insertion and

resizing. The buffer insertion algorithm inserts a properly

resized buffer at an appropriate location to achieve the

following goals: (i) compensate for the delay degradation

caused by lowering the supply voltage; (ii) reduce the

interconnection delay; and (ii) eradicate the crosstalk

noise.

An accurate delay and crosstalk noise model for

coupled distributed RLC wires has been presented here.

A fast algorithm VIJIM that inserts buffers for delay and

noise optimization at a reduced voltage swing signaling

has been presented.

The experimental results for a set of interconnect

benchmarks show that the proposed delay model has a

comparable performance to Yehea’s algorithm [14]. The

average error of our delay estimation algorithm is 6.42%,

whereas the average error of Yehea’s algorithm is 6.6%.

TABLE XV Comparison of VIJIM to BuffOpt at the case when D ¼ 1 and the interconnect parameters are given by the column W1 in Table V

R0 (V) d (in mm) VN Vour hour VVIJIM VBuffOpt dVIJIM (in mm) dBuffOpt (in mm)

100 100 0.13 0.127 22.82% 0.13 0.13 – –200 0.179 0.171 24% 0.179 0.151 – 130500 0.238 0.219 27.8% 0.189 0.151 229 130

1000 0.255 0.242 25.29% 0.189 0.151 229 1301000 100 0.125 0.125 20.54% 0.125 0.125 – –

200 0.171 0.17 20.84% 0.171 0.143 – 130500 0.217 0.216 20.197% 0.180 0.143 237 130

1000 0.239 0.239 20.135% 0.180 0.143 237 1302000 100 0.126 0.1258 20.27% 0.126 0.126 – –

200 0.17 0.17 20.149% 0.17 0.143 – 130500 0.216 0.216 20.041% 0.18 0.143 237 130

1000 0.239 0.239 20.037% 0.18 0.143 237 130

The results are obtained by fixing CL and Cb to 0.135fF and the normalized h ¼ 0:18 to fix some noise violations reported in Table XIV for the case VIJIM algorithm. The cellthat contains “–” means that no buffer is inserted by the corresponding algorithm.

TABLE XVI Energy-saving based on reduced swing signaling

Param.Wire length (d in mm)

d 1 mm 2 mm 6 mm 8 mm 10 mm 15 mm

j25 ( pJ ) 0.76 1.84 5.75 10.6 13.8 29.3j18 ( pJ ) 0.37 1.03 3.89 5.66 9.84 15.6j15 ( pJ ) 0.25 0.75 2.96 3.7 4.94 10.3j1 ( pJ ) 0.42 0.63 1.84 3.83 4.26 10.1z18 251% 244% 232% 246% 228% 246%z15 267% 260% 294% 265% 264% 264%

DEEP-SUBMICRON TECHNOLOGY 579

More importantly, with the proposed delay model it is

possible to obtain a condition for buffer insertion and the

optimal buffer location for delay optimization.

The results also show that the proposed crosstalk noise

is very accurate with respect to HSPICE results and more

accurate than state of the art published algorithms. In

on-chip signaling in 0.25mm CMOS process, and in the

presence of crosstalk noise, VIJIM algorithm was found to

be more efficient than state of the art algorithm that inserts

buffer for noise optimization [5]. In order to save power

while driving the interconnect at an optimal delay and to

satisfy the noise requirements, the experimental results

show that over 60% of energy-saving can be achieved if

the supply voltage is reduced from 2.5 V down to 1.5 V.

Acknowledgements

The authors would like to thank Mr Woonghwan,

the author of the paper Ref. [33], for providing the

measurement results for R, L and C.

References

[1] Dally, W.J. and Poulton, J.W. (1998) Digital Systems Engineering(Cambridge University Press, ISBN 0521 59292 5.

[2] Wang, J.M., Yu, Q. and Kuh, E.S. (1999) “Coupled noise estimationfor distributed RC interconnect model”. Proceedings of the DesignAutomation and Test in Europe Conference.

[3] Caufape, S. and Figuera, J. (1996) “Power optimization of delayconstrained CMOS bus drivers”. Proceedings of the DesignAutomation and Test in Europe Conference.

[4] Adler, V. and Friedman, E.G. (1998) “Repeater design to reducedelay and power in resistive inter-connect”, Transactions on Circuitand System 45(5), 607–616.

[5] Alpert, C.J., Devgan, A. and Quay, S.T. (1999) “Buffer insertion fornoise and delay optimization”, Transactions on Computer AidedDesign 18(11), 1633–1645.

[6] Alpert, C. and Devgan, A. “Wire segmenting for improved bufferinsertion”. Proceedings of the Design Automation Conference, June1997.

[7] Ma, S. and Franzon, P. (1994) “Energy control and accurate delayestimation in the design of CMOS buffers”, Journal of Solid-StateCircuits 29(9), 1150–1153.

[8] Van, L.P.P.P. (1990) “Buffer placement in distributed RC-treenetworks for minimal Elmore delay”. Proceedings of theInternational Symposium on Circuit and System.

[9] Pangjun, J. and Sapatnekar, S.S. (1999) “Clock distribution usingmultiple voltages”. Proceedings of the International Symposium onLow Power Electronic and Design.

[10] Zhang, H. and Rabaey, J. (1998) “Low-swing interconnect interfacecircuits”. Proceedings of the International Symposium on LowPower Electronic and Design.

[11] Ben Dhaou, I., Sundararajan, V., Tenhunen, H. and Parhi, K.K.(2001) “Energy efficient signaling in deep submicron CMOStechnology”. Proceedings of the International Symposium onCircuit and System.

[12] Ben Dhaou, I., Sundararajan, V., Tenhunen, H. and Parhi, K.K.(2001) “Energy efficient signaling in deep submicron CMOStechnology”. Proceedings of the International Conference onQuality Electronic Design.

[13] Zhou, D. and Liu, X.Y. (1995) “Optimal drivers for high-speed lowpower ICs”. Proceedings of the International Journal of High SpeedElectronics.

[14] Ismail, Y.I. and Friedman, E.G. (2000) “Effects of inductance onthe propagation delay and repeaters insertion in VLSI circuits”,Transactions on Very Large Scale Integrated Circuits 8(2), 195–206.

[15] Hegde, R. and Shanbhag, N.R. (1999) “Energy-efficient signalprocessing via algorithmic noise-tolerance”. Proceedings of theInternational Symposium on Low Power Electronic and Design.

[16] Lin, L. and Redinbo, G.R. (1993) “Block implementation of fault-tolerant LMS adaptive FIR filters”. Proceedings of the InternationalWorkshop on Defect and Fault Tolerance in VLSI Systems.

[17] Ben Dhaou, I., Akopian, D., Kuosmanen, P. and Astola, J. (1996)“Fault detection in stack filter circuits based on sample selectionprobabilities”. Proceedings of the International Conference onImage Processing.

[18] Sylvester, D. and Keutzer, K. (1998) “Getting to the bottom of deepsubmicron”. Proceedings of the International Conference onComputer Aided Design.

[19] Balamurugan, G. and Shanbhag, N.R. (1999) “Energy-efficientdynamic circuit design in the presence of crosstalk noise”.Proceedings of the International Symposium on Low PowerElectronic and Design.

[20] Veendrick, H. (1988) “Short-circuit power dissipation of staticCMOS circuitry and its impact on the design of buffer circuits”,Journal of Solid-State Circuits SC-19, 468–473.

[21] Sapatnekar, S.S. (2000) “A timing model incorporating the effect ofcrosstalk on delay and its application to optimal channel routing”,Transactions on Computer Aided-Design 10(5).

[22] Dworsky, L.N. (1979) Modern Transmission Line Theory andApplications (Wiley, New York).

[23] Afken, G. (1970) Mathematical Methods for Physicists (AcademicPress Publishers, New York).

[24] Kawaguchi, H. et al. “Delay and noise formulas for capacitivelycoupled distributed RC lines”. Proceedings of the Asian and SouthPacific Design Automation Conference, February 1998.

[25] Shoji, M. (1992) Theory of CMOS Digital Circuits and CircuitFailures (Princeton University Press, Princeton, NJ).

[26] Rabaey, J.M. (1996) Digital Integrated Circuits: A DesignPerspective (Prentice-Hall, Englewood Cliffs, NJ), ISBN 0-13-178609-1.

[27] Devgan, A. (1997) “Efficient coupled noise estimation for on-chipinterconnects”. Proceedings of the International Conference onComputer Aided-Design.

[28] Kuhlmann, M., Sapatnekar, S. and Parhi, K.K. (1999) “Efficientcrosstalk estimation”. International Conference on ComputerAided-Design.

[29] Kahng, A.B. and Muddu, S. (1997) “An analytical delay model forRLC interconnects”, Transactions on Computer Aided-Design Dec.,1507–1514.

[30] Kahng, A.B., Muddu, S. and Vidhani, D. (1999) “Noise and delayuncertainty studies for coupled RC interconnects”. Proceedings ofthe ASIC/SOC Conference.

[31] Sakurai, T. (1993) “Closed-form expressions for interconnectiondelay, coupling, and crosstalk in VLSIs”, Transactions on ElectronDevices 40(1), 118–120.

[32] Werner, C. et al. “Crosstalk noise in future digital CMOS circuits”.Proceedings of the Design Automation and Test in EuropeConference, March 2001.

[33] Woonghwan, R., et al., (2000) “Embedded microstrip interconnec-tion lines for GigaHertz digital circuits”, Transactions on Packagingand Manufacturing Technology 23(3), 495–503.

[34] Deutsch, A., et al., (1997) “When are transmission-line effectsimportant for on-chip interconnections?”, Transactions on Micro-wave Theory Technology 45, 1836–1846.

APPENDIX A: CLOSED FORM EXPRESSION FOR

THE INTERCONNECTION DELAY

The objective in this Appendix is to derive a closed-form

expression of the interconnect delay. The outline of the

derivation is as follows. Firstly, the differential equations

(DFE) for two coupled transmission lines is rigorously

derived. Secondly, solutions of the DFEs in Laplacian

domain are described. After this, approximated time-

domain solutions of the DEFs are elaborated. Finally, a

closed form expression for the interconnection delay is

deduced.

From Fig. 5, we can see that the problem is symmetric

because the two transmission lines (TML1 and TML2) are

I.B. DHAOU et al.580

assumed to be homogeneous with the same electrical

parameters R, L and C. Thus, it is enough to just derive the

DFE for TML1.

Let us consider the node ðNx1; Nxþdx

1 ; N0Þ; where N0 is

used to refer to the ground. If we apply Kirchhoff’s

voltage law, we obtain the following equations

›v1ðx; tÞ

›x¼ 2 Ri1ðx; tÞ þ L

›i1ðx; tÞ

›t

� �; ð33Þ

›i1ðx; tÞ

›x¼ 2

›v1ðx; tÞ

›tðCc þ CÞ2

›v2ðx; tÞ

›tCc

� �; ð34Þ

where C, L, R, CC are, respectively, the PUV of the wire

capacitance, inductance, resistance, and crosstalk

capacitance.

If i1 is substituted in Eq. (33) by its expression given by

Eq. (34), the following equation is obtained:

›2v1ðx; tÞ

›x2¼ RðC þ CcÞ

›v1ðx; tÞ

›t2 RCc

›v2ðx; tÞ

›t

þ LðC þ CcÞ›2v1ðx; tÞ

›t 2

2 LCc

›2v2ðx; tÞ

›t 2: ð35Þ

By using the symmetrical property of the coupled

transmission line, the DEF for TML2 is found to be

›2v2ðx; tÞ

›x2¼ RðC þ CcÞ

›v2ðx; tÞ

›t2 RCc

›v1ðx; tÞ

›t

þ LðC þ CcÞ›2v2ðx; tÞ

›t 2

2 LCc

›2v1ðx; tÞ

›t 2: ð36Þ

In order to derive the Telegraph equation for TML1 and

TML2, let us first define the following entities:

v2ðx; tÞD¼v1ðx; tÞ2 v2ðx; tÞ and vþðx; tÞ

D¼v1ðx; tÞ þ

v2ðx; tÞ: By using Eqs. (35) and (36), we obtain the

following DEFs

›2v2ðx; tÞ

›x2¼LðC þ 2CcÞ

›2v2ðx; tÞ

›t 2

þ RðC þ 2CcÞ›v2ðx; tÞ

›t; ð37Þ

›2vþðx; tÞ

›x2¼ LC

›2vþðx; tÞ

›t 2þ RC

›vþðx; tÞ

›tð38Þ

By doing this useful transformation, we can see that the

problem of computing v1(t ) and v2(t ) of the two coupled

transmission line is simply reduced to the problem of

solving two independent Telegraph equations for two

transmission lines, T1 and T2 driven by, respectively, v 2

and v þ.

Closed Form Expression for the Output Voltage of atransmission Line

From the derivation described in Ref. [22] we know that

the transfer function for a transmission line of length d,

shown in Fig. 13, is given by

HðsÞ ¼VdðsÞ

ViðsÞ¼

1

cos hðdffiffiffig

pÞ þ Zs

Z0sin hðd

ffiffiffig

pÞ

h iþ 1

ZLZ0 sin hðd

ffiffiffig

pÞ þ Zs cos hðd

ffiffiffig

pÞ

� � ;ð39Þ

where Zs is the source impedance, g ¼ ðR þ LsÞCs; ZL is

the load impedance Z0 ¼ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiðR þ sLÞ=sC

pis the character-

istic impedance for the transmission line, and s is the

Laplace variable.

Consider a case of a source of impedance Zs ¼ R0

driving an interconnect of length d terminating at an

impedance of value ZL ¼ 1=sCL; and letting r ¼ Rd;l ¼ Ld and c ¼ Cd; the expression for the transfer

function then becomes

1

HðsÞ¼ ZðsÞ ¼

X1n¼0

d 2ngn

ð2nÞ!1 þ R0sCL½ �

þX1n¼0

d 2nþ1gn ffiffiffig

p

ð2n þ 1Þ!

R0

Z0

þ Z0sCL

! "ð40Þ

Let FðsÞ ¼ Lðf ðxÞÞ be the Laplace transform of f(x ) as

defined [23]

FðsÞD¼

ð1t¼0

f ðtÞe2stdt; ð41Þ

In order to derive the time domain expression for

vdðtÞ ¼ L21Vðd; sÞ; Eq. (40) must be expressed as

follows

HðsÞ ¼PðsÞ

QðsÞ¼XN0

i¼1

Ai

s 2 si

; ð42Þ

where Ai ¼ PðsiÞ=Q 0ðsiÞ and N0 is the approximation

order.

Now, our objective is to express the transfer function

H(s ) given by Eq. (40) in a polynomial form as given by

Eq. (42).

Let us define G as

G ¼ dg ¼ ðr þ lsÞcs: ð43Þ

DEEP-SUBMICRON TECHNOLOGY 581

Eq. (40) is then reduced to

1

HðsÞ¼ YðsÞ ¼

D1ðsÞ

X1n¼0

Gn

ð2nÞ!1 þ R0sCL½ �

þ

D2ðsÞ

X1n¼0

GnffiffiffiG

p

ð2n þ 1Þ!

R0

Z0

þ sCLZ0

! " ð44Þ

If only the second-order polynomial of s, is considered,

approximate expressions for D1(s ) and D2(s ) are obtained.

The second-degree polynomial for s that approximates

H(s ) is given by:

HðsÞ ¼1

1 þ b1s þ b2s2; ð45Þ

where b1

b1 ¼rc

2þ R0ðCL þ cÞ þ rCL ð46Þ

and b2 is given by

b2 ¼R0rc2

6þ CLl þ

r 2cCL

6þ

cl

2þ

r 2c2

24þ

R0CLrc

2ð47Þ

Given b1 and b2, the transfer function can be factorized as

HðsÞ ¼1

b2ðs 2 s1Þðs 2 s2Þð48Þ

where s1 and s2 are the solutions of the following equation

gðsÞ ¼ 1 þ b1s þ b2s2 ¼ 0: ð49Þ

In order to solve Eq. (49), the first step is to compute the

discriminator D ¼ b21 2 4b2: The inspection of Eq. (48)

reveals that there are three cases to consider. (i) case

number one: s1 and s2 are real and s1 – s2; this is

equivalent to the condition D . 0; (ii) case number two:

s1 ¼ s2; or alternatively D ¼ 0; (iii) case number three: s1,

s2 are complex numbers, this corresponds to the condition

D , 0; and thus, s1 is the complex conjugate of s2.

Mathematically this means that s1 ¼ �s2:

In order to derive a time-domain expression for the

output voltage vdðtÞ ¼ L21ðHðsÞViðsÞÞ; let us assume that

the input voltage follows an exponential function, which

means that viðtÞ ¼ Vddð1 2 e2tð2:30=TrÞÞ: The expression

for Vi(s ) is then given by Eq. (50).

ViðsÞ ¼1

s2

1

s þ b; ð50Þ

where b ¼ 22:3=Tr; and Tr is the rise-time of the input

voltage.

The predicted output voltage for the case number

one is given by

vdðtÞ ¼Vdd

b2

1

s1s2

1 2s2es1t

s2 2 s1

þs1es2t

s2 2 s1

� �

2ðs2 2 s1Þe

2bt þ ðbþ s2Þes1t 2 ðs1 þ bÞes2t

ðbþ s1Þðs2 2 s1Þðbþ s2Þ

ð51Þ

An approximated equation for vd(t ) under a step input

was derived by Kahng et al. (referred to as ABK

formula) in Ref. [29] and found to be

vdðtÞ < Vdd 1 2 es1t s2

s2 2 s1

þ es2t s1

s2 2 s1

� �; ð52Þ

Figure 14 shows the plot of vd(t ) given by Eq. (51)

versus the measured vd(t ) given by HSPICE simulator.

Figure 15 shows that vd(t ) computed using the method

proposed in this paper behaves better than ABK formula.

However, in many situations, the value of Tr is very

unlikely to be higher than few nano-seconds, thus in the

rest of the derivation, the ABK formula given in Eq. (52)

is used as an approximation for vd(t ) if s1 and s2 are real

valued, such that s1 – s2:Using the expression given by Eq. (52), our next goal

is to derive the equation for vd (t ) if s1 and s2 are

complex numbers (case2). Mathematically it means that

s1 ¼ aþ jl ¼ �s2; where x̄ means the complex conjugate

of x. If s1 and s2 are substitute for by their expressions

given in Eq. (51), we obtain the following expression

vdðtÞ < Vdd 1 þ eat a

lsinðltÞ2 cosðltÞ

� �� �� �ð53Þ

Using the well known trigonometric transform, Eq. (53) is

further written in a compact form which is given in

Eq. (54).

vdðtÞ < Vdd 1 þ eatr cosðlt 2 fÞ� �

; ð54Þ

where r ¼ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi1 þ ða=lÞ2

p; and f ¼ pþ arctanð2l=aÞ:

Figure 15 plots vd(t ) computed using Eq. (53) versus

the one obtained via HSPICE simulator.

FIGURE 13 A two port model of a transmission line driven by a source of impedance Zs, terminated by an impedance ZL.

I.B. DHAOU et al.582

If s1 ¼ s2 ¼ s (that means, case number 3 is true) then

the approximated expression for vd(t ) becomes

vdðtÞ ¼ Vddð1 2 estÞ: ð55Þ

Figure 16 plots vd(t ) computed using Eq. (55) versus the

one obtained using HSPICE simulator.

In summary, the output voltage, vd(t ), of the

transmission line can have three possible expressions.

These expressions are presented in Table XVII.

Closed Form Expression for the Interconnection Delay

Given the expression for the output voltage, vd(t ), the

delay is defined as {tdjvdðtdÞ ¼ vth}; where vth ¼ Vdd=2:From the closed-form expressions for vd (t ) given in

Table XVII, we see that the delay td may take on one of

the three forms given in Table XVII. A closed form delay

expressions for the three different cases have been derived

by Kahng et al. in Ref. [29] (Referred to as ABK delay

model). In the sequel, ABK delay models are reviewed.

FIGURE 15 Comparsion of Eq. (53) to HSPICE. The interconnect parameters are the following: d ¼ 0:1 mm; R ¼ 2V=mm; L ¼ 0:1mH=mm;C ¼ 25 pF=mm; R0 ¼ 20V; CL ¼ 25 pF; Tr ¼ 2 ns and Vdd ¼ 1 V:

FIGURE 14 Comparsion of Eq. (51) and ABK formula (see Eq. (52)) to HSPICE. The interconnect parameters are the following: d ¼ 0:1 mm;R ¼ 2:5V=mm; L ¼ 1 nH=mm; CL ¼ 1fF; C ¼ 2:5 pF=mm; R0 ¼ 2000V; Tr ¼ 20 ns and Vdd ¼ 1 V:

DEEP-SUBMICRON TECHNOLOGY 583

However, only the two first cases given in Table XVII

have been considered.

If s1 and s2 are real then the approximated expression

for td, is reduced to

td ¼ 2Kr

b2

b1 2

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffib2

1 2 4b2

q ; ð56Þ

where Kr is given by the following equation

Kr ¼ log 1 þb1ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi

b21 2 4b2

q0B@

1CA: ð57Þ

Kahng et al. have found that Kr is constant for a wide

range of interconnect models used in their experiments.

Then, a least-square estimation (linear regression) has

been applied to obtain an empirical value of Kr. In their

interconnect benchmarks, Kr has been found to be equal to

2.3. This expression is appropriate for the 90% delay

threshold. In this work, we are interested in the 50% delay

model. In order to derive the interconnect delay for the

50% delay threshold, we fix vth ¼ 0:5: Thus, the

expression for Kr becomes in the form of logð1 þ xÞ

where x ¼ b1=ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffib2

1 2 4b2

q: The function logð1 þ xÞ <

x 2 0:5x2: Thus, the approximated expression for the td

given by Eq. (56) is reduced to Eq. (58).

Kr ¼2b2b1

b1

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffib2

1 2 4b2

q2 ðb2

1 2 4b2Þ

2b2b2

1

ðb21 2 4b2Þðb1 2

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffib2

1 2 4b2

qÞ

ð58Þ

An empirical value for Kr has been found to be equal to

0.69. Thus, the expression for the interconnection delay

given by Eq. (58) becomes

td ¼1:38b2

b1 2

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffib2

1 2 4b2

q ð59Þ

If s1 and s2 are complex number then the 50% delay must

be computed using Eq. (53). Computing the delay for this

case requires some approximations in order to find a linear

expression of the delay as a function of the wire-length.

The approach undertaken in Ref. [29] was to substitute t

by the Elmore delay in the exponential function, then the

sine function is approximated by its first order Taylor

series. In the case here, we have used a second order

Taylor series for the function td given by Eq. (53).

TABLE XVII Closed form expressions for vd(t )

Cases Case 1 Case 2 Case 3

Condition b21 . 4b2 b2

1 , 4b2 b21 ¼ 4b2

vd(t ) Vdd

b2

1s1s2

1 2 s2e s1 t

s22s1þ s1e s2 t

s22s1

� �� �Vddð1 þ e atr cosðlt 2 fÞÞ Vddð1 2 e stÞ

FIGURE 16 Comparison of Eq. (55) to HSPICE. The interconnect parameters are the following: d ¼ 10 mm; R ¼ 0:25V=mm; L ¼ 0:1 nH=mm;C ¼ 0:25 pF=mm; R0 ¼ 20V; CL ¼ 1:719 pF; Tr ¼ 10 ns and Vdd ¼ 1 V:

I.B. DHAOU et al.584

The expression for the delay is found to be

td ¼fþ arccosðeÞ2 p

2l: ð60Þ

where e ¼ 1=2r:

APPENDIX B: CLOSED FORM EXPRESSION FOR

THE CROSSTALK NOISE

The objective in this Appendix is to derive a closed-form

expression for the crosstalk noise.

From Appendix A, we know that there are three

possible cases for the output voltages vþðd; tÞ and

v2ðd; tÞ: Those cases are summarized in Table XVII.

This means that the expression of the crosstalk noise can

have six different cases. However, in this paper we assume

that TML1 and TML2 belong to the same class. In other

words, if the poles of TML1 belong to Case1 then TML2

belongs to Case1 (see Table XVII). In this model, only the

expression for the crosstalk noise if TML1 and TML2

belong to Case1 is elaborated.

Let us denote by E1 and E2 the DC voltage for v1(t ) and

v2(t ), respectively. Following the same techniques used

by Sakurai et al. to derive the crosstalk noise estimation

model [31], if we set E1 equals zero, we obtain the

normalized peak noise which is given by

VNðtpeakÞ ¼ 0:5 sþesþ1

tpeak 2 s2es21

tpeak

� �; ð61Þ

where

sþ ¼sþ2

sþ2 2 sþ1; s2 ¼

s22s22 2 s21

;

tpeak ¼ logsþ1 s

þ

s21 s2

� �1

sþ1 2 s21;

s21;2 and sþ1;2

are, respectively, the solution for the DFEs given by

Eqs. (37) and (38).

Imed Ben Dhaou (S’97) was born in 1972 in Bizerte,

Tunisia. He received his Masters degree with distinction

from the signal processing Laboratory at Tampere

University of Technology in May 1997. Since October

1997, Mr Ben Dhaou is a Ph.D. student in Electronic

System Design Laboratory at the Royal Institute of

Technology, Sweden. He is expected to earn his Ph.D.

degree in 2002. His research interests are in the area of

interconnect optimization, low-power circuit design, high-

level power estimation, robust estimation, and VLSI for

DSP and wireless systems. He authored and co-authored

more than 20 journals and conference papers in these

areas. He serves as a reviewer for the PhD forum at DAC,

Transactions on Multimedia, IEEE Sensors Journal, IEEE

Signal Processing Letters, and Design Automation

Conference since 2001.

Mr Ben Dhaou received the Best Paper Award from the

1997 Finnish Symposium on signal processing and a travel

grant from the PhD forum at DAC, Los Angeles in 2000.

Mr Ben Dhaou is a student member of IEEE and ACM. He

was the guest editor for the special issue of on-chip

signaling in deep-submicron technology, JOURNAL OF

ANALOG INTEGRATED CIRCUITS AND SIGNAL

PROCESSING.

Keshab K. Parhi (S’85-M’88-SM’91-F’96) is a distin-

guished McKnight University Professor of Electrical and

Computer Engineering at the University of Minnesota,

Minneapolis. He is also affiliated with Broadcom

Corporation in Irvine, CA. He received the B.Tech.,

M.S.E.E., and Ph.D. degrees from the Indian Institute of

Technology, Kharagpur (India) (1982), the University of

Pennsylvania, Philadelphia (1984) and the University

of California at Berkeley (1988), respectively.

His research interests include all aspects of VLSI

implementations of broadband access networks. He is

currently working on VLSI adaptive digital filters,

equalizers and beamformers, error control coders and

cryptography architectures, low-power digital systems and

computer arithmetic. He has published over 320 papers in

these areas. He has authored the text book VLSI Digital

Signal Processing Systems (Wiley, 1999) and co-edited

the reference book Digital Signal Processing for Multi-

media Systems (Dekker, 1999). He received the 2001

W.R.G. Baker prize paper award from the IEEE, a Golden

Jubilee medal from the IEEE Circuits and Systems Society

in 1999, a 1996 Design Automation Conference best paper

award, the 1994 Darlington and the 1993 Guillemin-Cauer

best paper awards from the IEEE Circuits and Systems

society, the 1991 paper award from the IEEE signal

processing society, the 1991 Browder Thompson prize

paper award from the IEEE, and the 1992 Young

Investigator Award of the National Science Foundation.

Dr Parhi has served on editorial boards of the IEEE

TRANSACTIONS ON CIRCUITS AND SYSTEMS, the

IEEE TRANSACTIONS ON SIGNAL PROCESSING,

the IEEE TRANSACTIONS ON CIRCUITS AND

SYSTEMS—PART II: ANALOG AND DIGITAL

SIGNAL PROCESSING, the IEEE TRANSACTIONS

ON VLSI SYSTEMS and the IEEE SIGNAL PROCES-

SING LETTERS. He is an editor of the JOURNAL OF

VLSI SIGNAL PROCESSING. He is the guest editor of a

special issue of the IEEE TRANSACTIONS ON SIGNAL

PROCESSING, two special issues of the JOURNAL OF

VLSI SIGNAL PROCESSING and a special issue of

JOURNAL OF ANALOG INTEGRATED CIRCUITS

AND SIGNAL PROCESSING. He served as technical

program co-chair of the 1995 IEEE Workshop on Signal

Processing and the 1996 ASAP conference, and is general

chair of the 2002 IEEE Workshop on Signal Processing

DEEP-SUBMICRON TECHNOLOGY 585

Systems. He serves on numerous technical program

committees, and was a distinguished lecturer of the IEEE

Circuits and Systems society (1994–1999). He is a fellow

of IEEE.

Hannu Tenhunen received degrees of Diploma Engineer

in Electrical Engineering and Computer Sciences from

Helsinki University of Technology, Helsinki, Finland, in

1982 and Ph.D. in Microelectronics from Cornell

University, Ithaca, NY, USA, in 1986. During 1978–

1982 he was with Electron Physics Laboratory, Helsinki

University of Technology, and from 1983 to 1985 at

Cornell University as a Fullbright scholar. From

September 1985 he has been with Tampere University of

Technology, Signal Processing Laboratory, Tampere,

Finland, as an associate professor. He was also a

coordinator of National Microelectronics Programme of

Finland during 1987–1991. Since January 1992 he has

been with the Royal Institute of Technology (KTH),

Stockholm, Sweden, where he is a professor of electronic

system design. His current research interests are VLSI

circuits and systems for wireless and broadband

communication, and related design methodologies and

prototyping techniques. He has made over 400 presenta-

tions and publications on IC technologies and VLSI

systems worldwide, and has over 16 patents pending or

granted. He has served in TPCs of many conferences and

was the conference chairman of European Solid State

Circuits Conference in 2000. Currently he is the dean of

School of Information Technology at KTH.

I.B. DHAOU et al.586

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