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Graduate Category: Engineering and Technology Degree Level: Ph.D. Abstract ID# 1112 Energy-Efficient Wireless Transceiver Operation using Optimized Heterogeneous Processor-FPGA Computations Benjamin Drozdenko, Matthew Zimmermann, Tuan Dao, Kaushik Chowdhury, Miriam Leeser Abstract Recent explosion in the number & diversity of devices, protocols, and applications Trend points towards systems with high data rates and low energy consumption Emerging vision of creating a transceiver architecture that can adapt to the functional and processing needs of existing and future protocols Maps computation to underlying heterogeneous platform, with CPU and FPGA We introduce a method for modeling 802.11a-based OFDM wireless transceiver Prototype on Xilinx Zynq system-on-chip by dividing PHY layer into functional units Our approach creates MathWorks Simulink model variants for both transmitter and receiver, each with a different boundary between HW and SW components Use models to generate HDL code-FPGA bitstream & C code-ARM CPU executable Results demonstrate how to select a HW-SW codesign for ideal 802.11a operation Background Design follows IEEE 802.11a Physical (PHY) layer specifications [1] Scrambling: XOR to make data pseudorandom, unbiased, independent Interleaving: rearranges bit indices to make random errors seem more random Convolutional Encoding: adds redundancy by producing parity bits Binary/Quadrature Phase Shift Keying (B/QPSK): modulation from bits to symbols Orthogonal Frequency Division Multiplexing (OFDM): map symbols to subcarriers and use Inverse Fast Fourier Transform (IFFT) to carry data on multiple channels Preamble: the fixed initial sequence at the start of a transmission, used to detect the beginning of frame at Rx Conclusion For direct feedthrough algorithms, moving more components to execution in HW results in faster execution speed, but adds risk of overwhelming FPGA resources While energy consumption increases as more components are placed on PL, the amount is negligible when compared to the embedded ARM energy consumption Many of the components developed for this base design can be reused for other variants of 802.11 (ac, af) as well as LTE protocols (4G mobile) For future work, we plan to perform tests with online radio transmissions and measure bit error rate (BER) for the different HW-SW co-designs References [1] IEEE 802.11 Working Group, “IEEE Std802.11a-1999.” IEEE, 1999. [2] Analog Devices, Inc. (2015) Integrated transceivers, transmitters, and receivers. [Online]. Available: http://www.analog.com/en/products/rf-microwave/ [3] MathWorks, Inc. (2015) Xilinx Zynq Support for MATLAB and Simulink. [Online]. Available: http://www.mathworks.com/hardware-support/zynq.html [4] G. Eichinger, K. Chowdhury, and M. Leeser, “CRUSH: cognitive radio universal software hardware,” in 22nd FPL, Oslo, Norway, August 29-31, 2012 [5] J. Pendlum, M. Leeser, K. Chowdhury, “Reducing processing latency with a heterogeneous FPGA- processor framework,” IEEE FCCM 2014, Boston, May 11-13, 2014 [6] B. Drozdenko, R. Subramanian, K. Chowdhury, M. Leeser, “Implementing a MATLAB-based self- configurable software defined radio transceiver,” 10th CROWNCOM ‘15, Doha, Qatar, Apr 21-23, 2015 Results: Execution Time Faster speed moving more components on PL. IFFT & Preamble Detection longest. Hardware Components Platform uses Xilinx ZC706 Evaluation Kit, ADI FMComms3 RF front end, Host PC Software Tools Workflow uses MathWorks Simulink, HDL Coder, Embedded Coder, Xilinx Vivado Method: Hardware-Software Codesign Model Variants Create seven models to represent HW-SW divides between 802.11 function units Hardware-Software Interfacing AXI-stream interface uses DMA controller to transfer data between PS & PL Results: Resource Utilization and Energy Consumption As more functional units put on PL, utilization & energy usage gradually increases Acknowledgements Discussion A benefit of flexible SDR testbed is reuse for other 802.11 & mobile standards Some units (scrambling, interleaving) can be reused directly in their present form Modifications needed for different encoding rates (2/3) and modulation schemes This reusability allows us to explore LTE and Wi-Fi coexistence on the same channel, TV whitespace reuse, and co-operation with RADAR PL Data Path Delay PL Energy Usage

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GraduateCategory: Engineering and TechnologyDegree Level: Ph.D. Abstract ID# 1112

Energy-Efficient Wireless Transceiver Operation using Optimized Heterogeneous Processor-FPGA Computations

Benjamin Drozdenko, Matthew Zimmermann, Tuan Dao, Kaushik Chowdhury, Miriam LeeserAbstract

• Recent explosion in the number & diversity of devices, protocols, and applications• Trend points towards systems with high data rates and low energy consumption• Emerging vision of creating a transceiver architecture that can adapt to the

functional and processing needs of existing and future protocols• Maps computation to underlying heterogeneous platform, with CPU and FPGA• We introduce a method for modeling 802.11a-based OFDM wireless transceiver• Prototype on Xilinx Zynq system-on-chip by dividing PHY layer into functional units• Our approach creates MathWorks Simulink model variants for both transmitter

and receiver, each with a different boundary between HW and SW components• Use models to generate HDL code-FPGA bitstream & C code-ARM CPU executable• Results demonstrate how to select a HW-SW codesign for ideal 802.11a operation

Background

• Design follows IEEE 802.11a Physical (PHY) layer specifications [1]• Scrambling: XOR to make data pseudorandom, unbiased, independent• Interleaving: rearranges bit indices to make random errors seem more random• Convolutional Encoding: adds redundancy by producing parity bits• Binary/Quadrature Phase Shift Keying (B/QPSK): modulation from bits to symbols• Orthogonal Frequency Division Multiplexing (OFDM): map symbols to subcarriers

and use Inverse Fast Fourier Transform (IFFT) to carry data on multiple channels• Preamble: the fixed initial

sequence at the start of atransmission, used to detect the beginning of frame at Rx

Conclusion

• For direct feedthrough algorithms, moving more components to execution in HW results in faster execution speed, but adds risk of overwhelming FPGA resources

• While energy consumption increases as more components are placed on PL, the amount is negligible when compared to the embedded ARM energy consumption

• Many of the components developed for this base design can be reused for other variants of 802.11 (ac, af) as well as LTE protocols (4G mobile)

• For future work, we plan to perform tests with online radio transmissions and measure bit error rate (BER) for the different HW-SW co-designs

References

[1] IEEE 802.11 Working Group, “IEEE Std802.11a-1999.” IEEE, 1999.[2] Analog Devices, Inc. (2015) Integrated transceivers, transmitters, and receivers. [Online]. Available: http://www.analog.com/en/products/rf-microwave/[3] MathWorks, Inc. (2015) Xilinx Zynq Support for MATLAB and Simulink. [Online]. Available: http://www.mathworks.com/hardware-support/zynq.html [4] G. Eichinger, K. Chowdhury, and M. Leeser, “CRUSH: cognitive radio universal software hardware,” in 22nd FPL, Oslo, Norway, August 29-31, 2012[5] J. Pendlum, M. Leeser, K. Chowdhury, “Reducing processing latency with a heterogeneous FPGA-processor framework,” IEEE FCCM 2014, Boston, May 11-13, 2014[6] B. Drozdenko, R. Subramanian, K. Chowdhury, M. Leeser, “Implementing a MATLAB-based self-configurable software defined radio transceiver,” 10th CROWNCOM ‘15, Doha, Qatar, Apr 21-23, 2015

Results: Execution Time

• Faster speed moving more components on PL. IFFT & Preamble Detection longest.

Hardware Components

• Platform uses Xilinx ZC706 Evaluation Kit, ADI FMComms3 RF front end, Host PCSoftware Tools

• Workflow uses MathWorks Simulink, HDL Coder, Embedded Coder, Xilinx Vivado

Method: Hardware-Software Codesign Model Variants

• Create seven models to represent HW-SW divides between 802.11 function units Hardware-Software Interfacing

• AXI-stream interface uses DMA controller to transfer data between PS & PL

Results: Resource Utilization and Energy Consumption

• As more functional units put on PL, utilization & energy usage gradually increases

Acknowledgements

Discussion

• A benefit of flexible SDR testbed is reuse for other 802.11 & mobile standards• Some units (scrambling, interleaving) can be reused directly in their present form• Modifications needed for different encoding rates (2/3) and modulation schemes• This reusability allows us to explore LTE and Wi-Fi coexistence on the same

channel, TV whitespace reuse, and co-operation with RADAR

PL Data Path Delay PL Energy Usage