EMC of ICs Masters STU 2009

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    April 27th, 2009

    Alexandre Boyer

    [email protected]

    INSA de Toulouse, France

    Electromagnetic Compatibility of IntegratedElectromagnetic Compatibility of Integrated

    Circuits (EMC of ICs)Circuits (EMC of ICs)

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    OUTLINE

    AGENDA

    9h - 12h: EMC of ICs part I (Course)

    14h - 17h: EMC of ICs part II (Lab activity)

    OBJECTIVES

    At the end of the course, the auditor will be able to understand the origins of

    electromagnetic compatibility (EMC) issues at integrated circuits level, the

    basic knowledge to face with EMC issues, and become familiar with the most

    common circuit-level EMC design guidelines.

    PRE REQUISITES

    Basic knowledge in electrical circuits, CMOS technology, electromagnetism,

    electrical simulation (SPICE).

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    Electromagnetic Compatibility ofElectromagnetic Compatibility of

    Integrated Circuits (EMC of ICs)Integrated Circuits (EMC of ICs)

    Part IPart I -- CourseCourse

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    OUTLINECONTENT

    IntroductionEMC Basics concepts

    Emission/Susceptibility Origin

    Measurement methods

    EMC Guidelines

    Conclusion

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    1. Introduction

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    What is EMC ?

    Disturbances of flight instruments

    causing trajectory deviations appear whenone or several passengers switch on

    electronic devices. (Air et Cosmos, April

    1993)

    29th July 1967 : accident of the American

    aircraft carrier USSForrestal. The accidental

    launching of a rocket blew gas tank and

    weapon stocks, killing 135 persons and

    causing damages which needed 7 monthreparations. Investigations showed that a

    radar induced on plane wiring a sufficient

    parasitic voltage to trigger the launching of the

    rocket.

    Two examples

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    What is EMC ?

    The abili ty of a device, equipment or system to function satisfactori ly

    in its electromagnetic environment without introducing intolerableelectromagnetic disturbance to anything in that environment.

    Reduce parasitic electromagnetic emission and sensitivity or

    susceptibility to electromagnetic interferences

    Guarantee the simultaneous operation of all nearby electric or electronic

    devices in a given electromagnetic environment

    Essential aspect for functional safety of electronic applications

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    Technology trends

    2000 2005 2010 2015

    10nm

    100nm

    1m

    Technology (log scale)

    Year

    0.13m90nm

    45nm32nm

    Technology trendhigh performance

    microprocessors

    22nm

    2020

    1nm

    7nm

    18nm9nm

    0.18m0.13m

    65nm

    Technology trend cost-performance

    microcontrollers0.25m0.35m

    90nm

    45nm 32nm

    5-years gap22nm

    Year

    Consequences on

    electronic systems safety,

    reliability, and EMC

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    EMC of ICs

    Until mid 90s, IC designers had no consideration about EMC problems in

    their design. EMC was only handled at system and PCB levels

    Many EMC problems originate from ICs (3rd origin of IC redesign !), as it

    is the source of noise emission and sensitivity

    With technology trends (increased clock speed, chip complexity andreduced voltage), ICs are more emissive and sensitive to noise

    Semiconductor manufacturers are faced with increasing customer

    expectations for designing low emission and highly immune ICs

    EMC must be handled at IC level

    Why EMC of ICs

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    EMC of ICsDesign issues

    EMC problems handled at

    the end of design cycleDESIGN

    Architectural

    Design

    Design Entry

    Design Architect

    FABRICATION

    Version n

    EMC Measurements

    GONO GO

    +6m

    onths

    +$$

    $$$$$$

    Compliance ?

    Version n

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    DESIGN

    Architectural

    Design

    Design Entry

    Design Architect

    FABRICATION

    EMC compliant

    EMC Simulations

    Compliance ?

    GO

    NO GO

    EMC validated before fabricationDesign Guidelines

    Tools

    Training

    EMC problems handled at

    the end of design cycle

    EMC of ICsDesign issues

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    2. EMC Basic Concepts

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    P=H2 x 377 (watts/m2)

    far field conditions

    P=I2 x R (watts)

    Z=E/HZ=V/I

    Characteristic impedance Z0 (Ohm)Impedance Z (Ohm)

    Magnetic field H (A/m)Current I (Amp)

    Electric Field E (V/m)Voltage V (Volt)

    Electromagnetic domainElectrical domain

    The EMC way of thinking

    EMC environment

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    Wide dynamic range of signals in EMC use ofdB (decibel)

    0.1

    10

    1

    100

    0.01

    Volt dBV

    0.001

    0.001

    0.1

    0.01

    1

    0.0001

    Milli

    VoltdBV

    0.00001

    Extensive use of dB for voltage units

    For example dBV, dBA:

    ( )( )AdBAVdBV

    log20

    log20

    ==

    Extensive use of dBV

    ( ) 120log201

    log20 +=

    = V

    V

    VVdBV

    0

    20

    40

    -20

    -40

    -60

    0

    20

    40

    -20

    -40

    60

    Specific Units

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    Specific UnitsExtensive use of dB for power units

    The most common power unit is the dBm (dB milli-Watt)

    1 mV = ___ dBV

    0.1 W = ___ dBm

    Exercise: Specific units

    ( ) 30log101

    log10 +=

    = W

    WdBmW P

    mW

    PP

    1 W

    1 MW

    1 KW

    Power

    (Watt)

    1 mW

    Power

    (dBm)

    1 W

    1 nW

    30

    90

    60

    0

    -30

    -60

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    Emission and susceptibility level units

    30K 300K 3M 30M

    40

    50

    60

    70

    80

    dBV

    Conducted emission level

    (CISPR25)

    Class 4

    Class 5

    1M 100M 1G

    10

    20

    30

    40

    50

    dBV/m

    Radiated emission level

    (CISPR25)

    Class 5

    10M

    CISPR 25 : Radio disturbance characteristics for the protection of receivers used on board

    vehicles, boats, and on devices Limits and methods of measurement

    Specific Units

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    Fourier Transform

    Time domain measurement

    Volt

    Time

    Frequency measurementFourier transform

    Freq (Log)

    dB

    Invert Fourier transform

    Fourier transform: principle

    Spectrum analyserOscilloscope

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    Fourier TransformWhy Frequency domain is so important for EMC?

    FFT

    Users specification

    Time domainFrequency domain

    Low level harmonics

    contribution

    Only high level harmonics contribution

    appearsContribution of each harmonic appears

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    Fourier transform - Example

    50 % duty cycle trapezoidal signal

    Period T = 100 ns, Tr = Tf = 2 ns

    FFT

    Fourier Transform

    Fast evaluation of signal

    bandwidth

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    Two main conceptsEmission of EM wavesSusceptibility to EM waves

    Personal entrainments

    Safety systems

    interferences

    Hardware fault

    Software failure

    Function Loss

    Components

    Printed circuit boards

    Equipments

    System

    Noise

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    Victim

    Aggressor

    Coupling method:

    Conducted

    Radiated

    Basic EMC problem

    Solving EMC issues consists in acting

    on these 3 different elements.

    Electromagneticemission

    Electromagnetic

    induced failure

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    Emission spectrum

    Specification foran IC emission

    Parasitic emission

    (dBV)

    -10

    0

    10

    20

    30

    40

    50

    60

    70

    80

    1 10 100 1000

    Frequency (MHz)

    Measured

    emission

    EMC compatible

    Aggressor IC

    Radiated emission

    Sufficient margin

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    Susceptibility threshold

    Immunity level(dBmA)

    -40

    -30-20

    -10

    0

    10

    20

    30

    40

    50

    1 10 100 1000

    Specification forboard immunityCurrent injection limit

    Measured

    immunity

    A very low energyproduces a fault

    Frequency (MHz)

    Victim IC

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    Notion of margin

    0 dB1 yearConsumer

    20 dB10 yearsAutomotive

    40 dB30 yearsAeronauticsMarginLifetimeDomain

    Parasit ic emission (dBV)

    Component/PCB/System Ageing

    Nominal Level

    Design Objective

    Process dispersion

    Measurement error/dispersion

    Environment

    Safety margin

    To ensure the electromagnetic compatibility,

    emission or susceptibility levels have to be

    lower than a nominal target But it is not sufficient to cancel all risks of

    failures !

    Margin are required to compensate

    unpredictable variations and reduce failureappearance probability.

    Margin depends on the

    safety level required in

    an application domain:

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    Parasitic coupling mechanisms

    Radiated mode

    Antenna coupling

    Example : The VSS

    supply track propagates

    noise

    The EM wave propagates

    through the air

    Coupling mechanisms

    Conducted mode Common

    impedance coupling

    Loop : Magnetic field coupling

    Wire : Electric field coupling

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    Parasitic coupling mechanismsCrosstalk

    Parasitic coupling between nearby conductors.

    Near field coupling radiated coupling

    Capacitive crosstalk Inductive crosstalk

    dielectric

    ground

    C C

    C12

    h

    t

    wd

    dielectric

    ground

    L12

    h

    t

    wddtdVCI=

    dtdILV=

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    ImpedanceR,L,C vs. frequency

    Impedance profile of:

    50 ohms resistor

    100pF capacitor

    10nH inductor

    a real 100 pF SMD

    capacitor

    Z = constant

    Z10atea

    chdecade

    Z10

    ateach

    decad

    e

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    Ceramic capacitor

    Carbon resistor

    Inductor

    ImpedancePassive components Real model

    Understand EMC issues

    requires the knowledge of

    electronic device parasitics

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    Interconnections

    2a

    l

    I

    acdc RRR +=

    2a

    l

    Rdc = a

    lR

    ac 2=

    = 1

    2ln

    2 a

    llL o

    Quasi static approximation : If l < /20,

    interconnections are considered as

    electrically small.

    PCB

    Package

    Bonding wires

    Parasitic resistance

    Parasitic inductance

    Interconnect parasit ics

    Interconnections are

    not equipotentials !

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    Interconnections

    Coaxial line Microstrip line

    From the electromagnetic point of view:

    H

    EZ =0 Link to conductor geometry and material properties

    jCG

    jLRZ

    +

    +=0

    C

    LZ 0

    lossless

    conductor

    From the electric point of view :

    Equivalent electrical schematic

    Characteristic impedance

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    InterconnectionsImpedance matching

    Adapted: the line is transparentNot adapted: the signal suffers from

    distortions: ringing, insertion losses

    time

    Voltage

    time

    Voltage

    Essential for signal integrity

    and power transfer

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    InterconnectionsCharacteristic impedance Small conductor Large conductor

    What is the optimum characteristic

    impedance for a coaxial cable ?

    Maximum power : Z0 = 32

    Minimum loss: Z0 = 77

    xLow Impedance

    xSmall inductance

    xSmallcapacitance

    xxLow loss

    Xweight

    XBending

    XPower handling

    Large

    conductor

    Small

    conductor

    Or ?

    Ideal values:

    EMC cable (compromise betweenpower and loss) : Z0 = 50

    TV cable (minimize Loss): Z0 = 75

    Cable examples:

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    50 adapted equipments

    Gtem

    Tem cell

    Spectrum analyzer

    Waveform generator

    Amplifier

    EMC equipments

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    3. Origin of Emission and

    Susceptibility of ICs

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    Susceptibility

    Chip

    Chip

    EmissionPCB

    PCB System

    Components

    Components

    System

    Integrated circuits are the origin of parasitic emission and susceptibility to

    RF disturbances in electronic systems

    Noisy

    IC

    Sensitive

    IC

    Interferences

    Radiation

    Coupling

    EMC at system level

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    Source of Electromagnetic InterferencesNatural disturbances

    (cosmic rays, thunder)Radio communications,

    wireless, radars,

    ElectricalOverstress

    Inductive loads,

    motors

    IC

    activity

    IC

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    VDD

    VSS

    Output

    capa

    Vin

    Basic mechanisms for CMOS circuit current: CMOS inverter example

    IDD(0.1mA)

    ISS(0.1mA)

    IDD

    (0.1mA)

    ISS (0.1mA)

    VOUT

    Switching current

    Voltage Time

    Time

    Origin of parasitic emission

    Main noise sources comes from AC current sources:

    - Clock-driven blocks, synchronized logic

    - I/O switching

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    Origin of parasitic emission Parasitic emission is linked to voltage drops... But only current peaks can

    not explained completely electromagnetic emission.

    Inductance are responsible of the conversion of current peak to voltagedrops.

    Current peaks and voltage drops generate the conducted emission and then

    the radiated emission.

    Vss

    Vdd

    50ps

    i(t)

    Time

    Switching gates

    Internal

    switching noise

    Vdd

    Vss

    i(t)

    Voltage drops

    t

    iLV

    =

    i(t)Radiated

    Emission

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    Stronger di/dtStronger di/dt

    Increase parasitic

    noise

    Increase parasitic

    noise

    Time

    New process

    Volt

    Old process

    Why technology scale down makes things worse ?

    Current level keeps

    almost constant but: Faster current switching

    Current level keeps

    almost constant but: Faster current switching

    Time

    Current

    di/dt

    New process

    Old process

    Origin of parasitic emission

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    Example: evaluation of switching current in an IC

    0.1 mA / Gate in 100ps

    1 Billion gates (32 Bit Micro) =>

    10% switching activity =>

    Spreading of current peak (non synchronous switching) =>

    Ampere

    time

    Vdd

    Vss

    i(t)Current / gate

    Ampere

    time

    Current / Ic

    Origin of parasitic emission

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    Example: evaluation of supply voltage bounce

    L=0.6nH/mm

    L=1nH/mm

    Lead = 10 mm

    1 A en

    1 ns Evaluate noise amplitude :

    VDD

    VSS

    Lead = 10 mm

    Chip

    Origin of parasitic emission

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    Susceptibility issues

    5.0

    3.3

    2.5

    1.8

    0.5 0.35 0.18 90nm 65nm

    Technology

    0.7

    Less voltage, more IOs

    Supply (V)

    1.2

    45nm

    Core supply

    I/O supply

    100

    200 5001000

    Noise margin

    reduction

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    Susceptibility issues

    Hobby

    Hobby

    TV UHF

    Radars

    Satellites

    MWave

    Badge

    DECT

    Stat. de base

    1W

    Frequency

    1MW

    1KW

    1GW Radar Mto

    3 MHz 30 MHz 300 MHz 3 GHz 30 GHz 300 GHz

    Power

    1mW

    HF VHF UHF SHF xHF THF

    RadarUMTS

    TV VHF

    GSM

    Components

    issues

    Components

    issues

    Multiple parasitic electromagnetic sources

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    Susceptibility issues

    Electromagnetic wave

    System failureHardware fault

    Function loss

    p

    mixed

    More complex ICs, more failure types

    analog

    Software failure

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    Susceptibility issuesDesynchronisation issues

    EMI induced delay is becoming increasingly important in digital design due to rising

    operating frequencies.

    EMI induced

    jitter

    EMI induced

    jitter

    Bit error

    Dynamicfailure

    EMI on supply

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    IC failures

    Origin of IC susceptibilityOverview of influent parameters on IC susceptibil ity

    IC

    IC Internal

    interconnexions

    IC active

    devices

    PCB tracks andexternal passive

    components

    Vdd

    Vss

    RF

    interferences

    Internalperceived noise

    1. Filtering effects of PCB tracks

    and external passive components

    2. Filtering effect of IC interconnections

    3. Impedance of IC nodes (high Znode = high susceptibility)

    4. Non linear effects of active

    devices (conversion RF signals to

    DC offsets !)

    5. Block own susceptibility (noise

    margin, delay margin, )

    1

    2 3 4 5

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    Emission / Susceptibility issues

    --++3. Charge pump

    +++1. DC/DC converter

    ++--7. Analog input/supply-+6. Digital block supply

    -++5. Fast digital I/O

    +++8. RF front end

    ++++4. Oscillator / PLL /

    Clock circuitry

    --++2. Power switch output

    SusceptibilityEmissionBlock type

    Overview of typical emissive/susceptible blocks

    1

    2

    3

    48

    5

    6

    7

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    4. EMC measurement methods

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    Why EMC standard measurement methods

    Check EMC compliance of ICs, equipments and systems

    Comparison of EMC performances between different products, differenttechnologies, designs, PCB routings

    Improve interaction between customers and providers (same protocols, same

    set-up)

    EMC measurement methods

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    Device under testCoupling device

    Coupling network

    Antennas

    Wave guide

    Acquisition system

    Spectrumanalyzer

    EMI receiver

    Oscilloscope

    Emission General measurement set-up

    Radiated or

    conducted coupling

    50 adapted

    path

    Control -

    Acquisition

    Emission requirements verified ?

    Emission measurement methods

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    IEC 61967-2

    (GTEM 18 GHz)

    IEC 61967-7

    (Mode Stirred Chamber: 18 GHz)

    IEC 61967-5

    (WBFC, 1 GHz)

    IEC 61967-4

    (1/150 ohm, 1 GHz)

    IEC 61967-3/6

    (Near field scan, 5GHz)

    IEC 61967-2

    (TEM : 1GHz)

    International standards for IC emission measurement methodsEmission measurement methods

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    Spectrum

    Analyser

    1ohm

    IC

    Complex

    implementationwith multiple

    power pins

    IEC 61967-4 International Standard : 1/150 Ohm methodEmission measurement methods

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    Microcontroller - 32 MHz scan

    Low

    High

    X axis

    Y axis

    dBV

    freq

    32MHz

    IEC 61967-3 International Standard : Near field scanEmission measurement methods

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    Hx Probe

    Priviledged

    current

    measurement

    Power rails

    CPU 12RAM

    2K

    32K FEEPROM 28K

    FEEPROM

    Power rails

    MS-

    CAN

    A

    T

    D

    1

    A

    T

    D

    0

    P

    WM

    E

    CT

    MI

    BUSMSI

    EE

    1K

    MMIIN

    TBDM

    K

    W

    U

    LIM D60

    CGMW

    C

    R

    MEBIBKP

    Emission measurement methodsIEC 61967-3 International Standard : Silicon scan

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    Immunity measurement methodsImmunity General measurement set-up

    Device under test

    Coupling device

    Coupling network

    Antennas

    Wave guide

    Radiated or

    conducted coupling

    Disturbance generation

    Harmonic signal

    Transients

    Burst

    50 adapted

    path

    Failure detectionInjected level

    Extraction

    Immunity requirements verified ?

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    Still research:

    (NFS 10 GHz)

    New proposal:

    (LIHA : 10 GHz)

    IEC 62132-5

    (WBFC 1 GHz)

    IEC 62132-4

    (TEM/GTEM)

    IEC 62132-3

    (Direct Power Inj 1GHz)

    IEC 62132-2

    (Bulk Current Injection : 1 GHz)

    International standards for IC susceptibility measurement methodsImmunity measurement methods

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    Immunity measurement methods

    10W Amplifier

    Oscilloscope

    PC Monitoring

    Signal generator

    IEEEBus or

    Good signal

    Failure signal

    Printed Circuit Board

    Device under test

    Dout

    Coupling

    Capacitance DUT

    Power increase loop until failure

    Frequency loop 1 MHz 3 GHz

    IEC 62132-3 International Standard : Direct Power Injection

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    Immunity measurement methods

    Inductive coupling to the network

    Parasitic current injected on the chip

    Limited to 1 GHz

    Normal

    current

    Parasitic current

    RF

    power

    CAN Bus

    Microcontroler

    DUT

    Fault

    Measured

    current

    IEC 62132-2 International Standard : Bulk Current Injection

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    5. EMC guidelines

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    Basic concepts to reduce emission andsusceptibilityRemember the influent parameters on emission and susceptibility

    Control IC internal activity

    Minimize circuit output load

    Control effect of ICinterconnections (decoupling)

    Control effect of PCB

    interconnections (decoupling)

    Emission: Susceptibility:

    Control effect of PCB interconnections

    (decoupling)

    Control effect of IC interconnections

    (decoupling)

    Control Impedance of IC nodes

    Reduce non linear effects of active devices

    Improve block own susceptibility

    Techniques used to reduce emission and/or susceptibility

    issues are based on these principles

    Techniques used to reduce emission and/or susceptibility

    issues are based on these principles

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    Golden Rules for Low Emission

    Lead: L=0.6nH/mm

    Bonding: L=1nH/mm

    Inductance causes voltage bounce Each conductor acts as an inductance

    Ground plane modifies inductance value (worst case is far from ground)

    A) Use shortest interconnection to reduce the serial inductance

    Rule 1: Power supply routing strategy

    Reducing inductancedecreases voltage bounce !!Reducing inductancedecreases voltage bounce !!

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    Golden Rules for Low EmissionRule 1: Power supply routing strategy

    A) Use shortest interconnection to reduce the serial inductance

    Leadframe package:L up to 10nH

    PCB

    Long

    leads

    Die of the IC

    Close from ground

    bonding

    Die of the ICShort

    leadsballsFlip chip package:

    L up to 3nH

    Far from ground

    Requirements for high speed microprocessors : L < 50 pH !Requirements for high speed microprocessors : L < 50 pH !

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    Golden Rules for Low EmissionRule 1: Power supply routing strategy

    Correct

    Fail

    9 I/O ports

    B) Place enough supply pairs: Use One pair (VDD/VSS) for 10 IOs

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    Golden Rules for Low EmissionRule 1: Power supply routing strategy

    Current density simulation

    C) Place supply pairs close to noisy blocks

    Layout view

    Digital core

    Memory PLL

    VDD / VSS

    VDD / VSSVDD / VSS

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    Golden Rules for Low EmissionRule 1: Power supply routing strategy

    to increase decoupling capacitance that reduces fluctuations to reduce current loops that provoke magnetic field

    D) Place VSS and VDD pins as close as possible

    Current

    loop

    EM field

    Addedcontributions

    currentsDie

    LeadLead

    current

    EM wave

    current

    EM wave

    Reduced

    contributions

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    Golden Rules for Low EmissionRule 1: Power supply routing strategy

    Case 1 : InfineonTricore Case 2 : virtex II

    Case study 1:

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    Golden Rules for Low EmissionRule 1: Power supply routing strategyCase study 2:

    courtesy of Dr. Howard Johnson, "BGA Crosstalk", www.sigcon.com

    More Supply pairs for IOs

    Better distribution

    More Supply pairs for IOs

    Better distribution

    2 FPGA , same power supply, same IO drive, same characteristics

    Supply strategy very different !

    Golden Rules for Low Emission

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    Golden Rules for Low Emission

    Rule 1: Power supply routing strategy

    Case study 2:

    courtesy of Dr. Howard Johnson, "BGA Crosstalk", www.sigcon.com

    Case 1: low emission due to

    a large number of supply

    pairs well distributed

    Case 1: low emission due to

    a large number of supply

    pairs well distributed

    Case 2: higher emission

    level (5 times higher)

    Case 2: higher emission

    level (5 times higher)

    Golden Rules for Low Emission

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    Z Vdd - Vss

    Frequency

    Target impedance Zt (0.25 m)

    In order to minimize voltage bounce on power

    supply and ground reference, impedance

    between Vdd and Vss must be as low as

    possible (inferior to a target impedance).

    Freq range

    current

    rippleVZ ddt

    max -3

    dB, RF input reflected coefficient > -10 dB. Tune the passive elements of the bias tee to check these

    properties from 1 MHz to 1 GHz. Use S parameter simulation.

    Problem 5 Conducted susceptibility

    of a digital circuit

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    o a d g ta c cu t

    2. Connect the bias tee and the RF injection system to a 100 load. Simulate the

    susceptibility threshold for a maximum noise of 1 V across the load. Would it be

    possible to predict the susceptibility threshold without SPICE simulation ?

    3. Build the equivalent model of the circuit (use Tools/ICEM model expert) and the PCB

    (use Tools/Interconnect parameters, remove the 1 probe). Simulate the susceptibility

    threshold of circuit.

    4. Simulate the reflection coefficient of the circuit. Does a link exist between thesusceptibility threshold and the reflection coefficient ?

    5. If a decoupling capacitor is added between Vdd and Vss, what will be the effect on

    circuit susceptibility ? Verify your conclusion by simulation.