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8/2/2019 EMC Lect 6 [Compatibility Mode]
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A Typical Power Supply Network
Consider a single section of the inductive (off-chip) portion of the
network.
Since the line impedance >> load impedance, it is modeled as a
lumped inductance. 1
Each section of the supply network is an LC circuit
Has a resonant frequency fres < fclock
Then, inductor carries the average (DC) current
And capacitor supplies the instantaneous (AC) current
Size the bypass capacitor to
Supply cycle to cycle AC current with acceptable ripple
Handle inductor start/stop transient 2
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3
The bypass capacitance C > ki Qclock/V
V is the maximum allowed supply variation
Here, Qclock = Iav Tclock is the charge transferred in one
clock cycle.
Inductor provides the current Iav and the capacitor the
difference . The factor ki is:
ki =
t
TIdtItI clockavt
av /])([max0
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Here, ki reflects the maximum fraction of the total charge
transferred each cycle ( Qclock
) that must be supplied by
the capacitor at a given t.
If I(t) is a delta function, ki = 1
If I(t) is a DC, ki = 0
5
Noise in Digital Systems
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Proportional and Independent
Noise Sources
7
Noise proportional to signal swing
- cross-talk
- inter-symbol interference
- signal return noise
- signaling power supply noise
8
Need to eliminate or cancel this noise
We cannot overpower it!
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Noise independent of signal swing
- receiver sensitivity
- receiver offset
- unrelated power supply noise
- reference offsets
Can overpower this noise
9
Power Supply Noise
10
Voltage drops across parasitics cause variation in the
voltage of a single supply ( VDD or GND) from one
point in the system
If signal is referenced to local supply, this variation
results in additive voltage noise
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Affects delay of many elements
- May not meet timing specs
- Jitter in timing circuits
Cross Talk
Noise induced by one signal interferes with another
signal
Capacitive coupling between on-chip lines
CapacitiveandInductive coupling between off-chip
lines
Coupling over shared signal returns
12
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Cross Talk and Delay
Capacitive cross talk can
affect delay of RC signals
If aggressor(s) switch in
opposite direction,
effective capacitance of Cc
is doubled
14
If aggressor(s) switch in the same direction, Cc is
effectively eliminated
Can cause 2:1 variation in delay in some cases
Significant cause of jitter if timing is critical
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Impact of noise on delay
15
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Impact of noise on functionality
17
Transmission Line Cross Talk
A signal transition on one line induces forward and
reverse traveling waves on adjacent lines
18
Inductive and
Capacitive
Coupling
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Consider a positive transient on aggressor line, A
Capacitive coupling induces a voltage on victim line B
positive waves in both forward and reverse directions
19
Inductive coupling induces acurrent in line B
positive wave in the reverse direction
negative wave in the forward direction
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Inductive and capacitive coupling addat the near end of
the line
both waves are positive
pulse begins at beginning of coupled section
21
Inductive and capacitive couplingsubtract at the far end
of the line
- in a homogeneous medium cancellation is exact
- narrow pulse coincident with wave on aggressor
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Managing noise
23
Divide noise along two axes
proportional vs. independent
bounded vs. statistical
Allocate noise to various sources
Prepare a budget for the bounded sources Net margin
is what remains after bounded sources
Compare magnitude of net margin to standard deviation
of statistical sources BER is a function of this SNR
Constrain design to meet the budget 24
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Parallel cross-talk
ISI
Receiver offset
Receiver sensitivity
Perpendicular cross-
talk
Power supply noise
Thermal noise
Proportional Independent
Bounded
Sta
tistical
25
Margins and Margin Ratio
Gross margin (VGM) is half the signal swing
Net margin (VNM) is gross margin less all bounded noise
sources
Margin ratio (VNM/VGM) is a good figure of merit
indicates proportion by which one can increase noise
sources without causing failure
26
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Worst - Case Analysis
All noise sources have the greatest possible magnitude
and they all add up in the same direction
Unlikely in any single unit at any instant in time, but if
one makes enough units and run them long enough,
this case will occur
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Vni Receiver offset 50 mV
Power supply noise 20 mV
Total Vni 70 mV
Kn Cross-talk 10%
Reflections 10%
Total Kn 20%
Signal swing Vs = 400 mV
Kn Vs = 80 mV
29
Gross margin = 200 mV
Vni = 70 mV
KnVs = 80 mV
Vn = 150 mV
Net margin = 50 mV
Margin ratio = 0.25
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Statistical Analysis
For some noise sources, we consider the probabilitydistribution of values rather than the worst case values
- thermal noise, shot noise, cross talk, power supply
noise.
These sources are modeled as a Gaussian distribution of
zero mean relevant parameter is the RMS value
31
Adding Gaussian Noise Sources
Cross-talk : 10 mV (rms)
PS noise : 20 mV (rms)
Total : 22.4 mv (rms)
Vrms = sqrt [ Vi ]
32
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If the net margin is VNM and the total Gaussian noise is
VGN
, then
SNR = VNM/VGN
What is the probability that the noise will exceed the
margin?
P(error) = erfc(VNM/VGN)
< exp [ - (VNM/VGN ) ]33
Electrical wire models:
The Ideal Wire
The Lumped Model
The Lumped RC model
The Distributed rc Line
The Transmission Line
34
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Inductive effects can be ignored if the resistance of the wire is
substantial this is the case for long Aluminium wires with a small
cross-section or if the rise/fall time of the applied signal is large.
When the wires are short or the cross-section of the wire is large or
the interconnect material used has a low resistivity, a capacitance-
only model can be used.
When the separation between neighboring wires is large, or when
the wires run together only for a short distance, inter-wire
capacitance can be ignored, and all the parasitic capacitance can be
modeled as capacitance to ground.35
The circuit parasitics of a wire are distributed along its length and
are not lumped at a single position. Yet, when only a single parasitic
component is dominant, or when the interaction between the
components is small, it is often possible to lump the different
fractions into a single circuit element.
The advantage of this approach is that the effects of the parasitic
then can be described by an ordinary differential equation.
The description of distributed elements requires partial differential
equations.
36
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In this model, the wire still represents an equipotential region, and
the wire itself does not introduce any delay. The only impact on
performance is by the loading effect of the capacitor on the driving
gate. This capacitive lumped model is simple, yet effective, and is
the model of choice for the analysis of most interconnect wires in
digital circuits.
As long as the resistive component of the wire is small and the
switching frequencies are in the low to medium range, it is
meaningful to consider only the capacitive component of the wire,
and to lump the distributed capacitance into a single capacitor
37
Clumped=Lcwire, with L the length of the wire and cwire thecapacitance per unit length. The driver is modeled as a voltage
source and a source resistanceRdriver. 38
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On-chip metal wires of over a few mm length have a significant
resistance. The equipotential assumption is no longer valid and a
resistive-capacitive model has to be adopted .
A first approach lumps the total wire resistance of each wire
segment into one singleR and similarly combines the global
capacitance into a single capacitor C.
This simple model, called the lumped RC modelis pessimistic and
inaccurate for long interconnect wires, which are more adequately
represented by adistributed rc-model.
39
Voltage range Lumped RC
network
Distributed rc
network
0 to 50 % 0.69 RC 0.38 RC
0 to 63 % RC 0.5 RC
10 to 90% 2.2 RC 0.9 RC
0 to 90 % 2.3 RC RC
40
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Distributed rc delays should be considered only when tpRC > tpgate of
the driving gate
rc delays should be considered only when the rise (fall) time at the
line input is smaller than RC R and C are the total resistance
and capacitance of the wire
Otherwise, lumped C model suffices
41
When the switching speeds become sufficiently fast, and the qualityof the interconnect material become high enough so that the
resistance of the wire is kept within bounds, the inductance of the
wire starts to dominate the delay behavior, and transmission line
effects must be considered.
This is more precisely the case when the rise and fall times of the
signal become comparable to the time of flight of the signal
waveform across the line.
42
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The lossless transmission line, is appropriate for wires at the
printed-circuit board level. Due to the high conductivity of the
Copper interconnect material used there, the resistance of the
transmission line can be ignored - On the other hand, resistance
plays an important role in ICs, and the lossy transmission line
modelshould be considered.
To avoid potentially disastrous transmission line effects such as
ringing or large propagation delays, the line should be terminated,
either at the source (series termination), or at the destination
(parallel termination) with a resistance equal to the characteristic
impedance of the line. 43
Loads in MOS digital circuits tend to be of a capacitive nature.
How this influences the transmission line behavior and when the
load capacitance should be taken into account?
The characteristic impedance of the transmission line determines
the current that can be supplied to charge capacitive load CL.
From the loads point of the view, the line behaves as a resistance
with value Z0. The transient response at the capacitor node,
therefore, displays a time constantZ0CL.
44
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Capacitively terminated transmission line:
RS = 50 W, CL= 2 pF,Z0 = 50 W,tflight = 50 ps.
45
Output rises to its final value with a time-constant of 100 ps (= 50 W 2 pF) after a delay equal to the time-of-flight of the line.
Propagation delay of the line equals the sum of the time-of-flight of
the line (50 ps) and the time it takes to charge the capacitance
(= 0.69Z0 CL = 69 ps).
The capacitive load should be considered in the analysis only when
its value is comparable to or larger than the total capacitance of the
transmission line
46
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After 2tflight, a voltage dip occurs at the source node.
Upon reaching the destination node, the incident wave is reflected.
This reflected wave also approaches its final value asymptotically.
Since Vdest equals 0 initially, the reflection equals - 2.5 V. This forces
the line temporarily to 0 V. This effect gradually disappears as the
output node converges to its final value.
47
The response of a lossyRLC line to a unit step combines wave
propagation with a diffusive component. The step input still
propagates as a wave through the line. However, the amplitude of
this traveling wave is attenuated along the line:
48
The arrival of the wave is followed by a diffusive relaxation to the
steady-state value at pointx.
The farther it is from the source, the more the response resembles
the behavior of a distributedrc line
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In fact, the resistive effect becomes dominant, and the line behaves
as a distributedrc line whenR ( =rL, the total resistance of the
line) >> 2Z0.
WhenR = 5Z0, only 8 % of the original step reaches the end of the
line. At that point, the line is more appropriately modeled as a
distributedrc line.
49
Be aware that actual wires on chips, boards, or substrates behave in
a far more complex way than predicted by the above analysis.
For instance, branches on wires, calledtransmission line taps, cause
extra reflections and can affect both signal shape and delay.
1) Transmission line effects should be considered when the rise or
fall time of the input signal (tr, tf) is smaller than the time-of-
flight of the transmission line (tflight).
For on-chip wires with a length of 1 cm, one need worry about
transmission line effects only whentr < 150 ps. At the board level,
where wires can reach a length of up to 50 cm, we should account
for the delay of the line whentr < 8 ns. This condition is easily
achieved with state-of-the-art processes and packaging
technologies. Ignoring the inductive component of the propagation
delay can easily result in overly optimistic delay predictions.50
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2) Transmission line effects should be considered only when the
total resistance of the wire is limited to R < 5 Zo
If this is not the case, the distributed rc model is more appropriate.
Both constraints can be summarized in the following set of
bounds on the wire length:
51