Embedded systems:

Nios II Avalon Interface

The Nios II architecture supports separate instruction and data busses, classifying it as a Harvard architecture

Memory

CPU CPU

DATA INSTRUCTION / PROGRAM

Instruction busData busShared bus

Von Neumann Harvard

Nios II Processor reference guide: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/nios2/n2cpu-nii5v1gen2.pdf

Instruction master port

• Performs a single function: it fetches instructions to be executed by the processor

• The instruction master port does not perform any write operations

Data master port

• Read data from memory or a peripheral when the processor executes a load instruction

• Write data to memory or a peripheral when the processor executes a store instruction

Avalon Memory Mapped interface

• Used as read and write interfaces on master and slave components in a memory-mapped system– E.g.: CPU, memories,

UARTs, timers, etc– Interfaces connected by an

interconnect fabric (Avalon interconnect)

• Components typically include only the signals required for the component logic

What is a QSYS* component?

• Hardware sub-circuit that is available as a library component for use in the tool

• Two parts:– Internal hardware modulus

(custom logic, desired functionality)

– Avalon-MM Interface (Communication)

*QSYS is the former name of Platform Designer.

Avalon interfaces• Avalon Clock Inteface

– drives and receives clocks (all avalon interfaces are synchronous)• Avalon Reset Interface

– provides reset connectivity• Avalon Memory-Mapped Interface (Avalon MM)

– address-based read/write interface (typical of master-slave connections)

• Avalon Streaming Inteface (Avalon ST) – support unidirectional flow of data

• Avalon Conduit Interface– for individual signals or group of signals that do not fit into any of the

other Avalon Interface types. Conduit signals can be exported to make connections external to the Qsys system

• Avalon interrupt interface: – allows components to signal events to other components

Source: ftp://ftp.altera.com/up/pub/Altera_Material/13.0/Tutorials/making_qsys_components.pdfhttp://www.altera.com/literature/manual/mnl_avalon_spec.pdf

Avalon interfaces

• Avalon interfaces are an open standard (no licensor royalty required to develop and sell products that use, or are based on Avalon Interfaces)

• All components must include the Avalon Clock and Reset interfaces.

• A single component may use as many of these interface types as it requires– Avalon ST for high-throughput data & Avalon MM

slave port for control

Avalon Bus Signals

FYS4220 I2C Avalon memory mapped interface

Avalon Bus Signals

Register interface for theI2C avalon memory mapped interface