Embedded Systems-8051 Microcontroller

7/18/2019 Embedded Systems-8051 Microcontroller

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8051 MICROCONTROLLER

EMBEDDED SYSTEMS



Introduction

CPU

General-

Purpose

Micro- processor

RAM ROM I/O

Port

TimerSerial

COM

Port

Data Bus

Address Bus

General-Purpose Microprocessor System

CPU for Computers

No RAM, ROM, I/O on CPU chip itself

!ample： Intel"s !#$, Motorola"s $#%!%

Many chips on mother"s &oar'

General-purpose microprocessor



RAM ROM

I/O

PortTimer

Serial

COM

PortMicrocontroller

CPU

A smaller computer

On-chip RAM, ROM, I/O ports(((

!ample：Motorola"s $#)), Intel"s #%*), +ilo"s +# an' PIC )$

A sinle chip

Microcontroller .



Microprocessor

CPU is stan'-alone, RAM,

ROM, I/O, timer are separate

'esiner can 'eci'e on theamount of ROM, RAM an'

I/O ports(

e!pansie

ersatility

eneral-purpose

Microcontroller

0 CPU, RAM, ROM, I/O an'

timer are all on a sinle chip

0 fi! amount of on-chip ROM,RAM, I/O ports

0 for applications in 1hich cost,

po1er an' space are critical

0 sinle-purpose

Microprocessor s( Microcontroller



)( meetin the computin nee's of the tas2 efficiently an' cost

effectiely

0 spee', the amount of ROM an' RAM, the num&er of I/O

ports an' timers, si3e, pac2ain, po1er consumption

0 easy to upra'e

0 cost per unit

4( aaila&ility of soft1are 'eelopment tools

0 assem&lers, 'e&uers, C compilers, emulator, simulator,

technical support

5( 1i'e aaila&ility an' relia&le sources of the microcontrollers(

6hree criteria in Choosin a Microcontroller



Block Diagram

CPU

On-cip

RAM

On-cip

ROM !or

program

code

" I/O Ports

Timer #

Serial

PortOSC

Interrupt

Control

$%ternal interrupts

Timer &

Timer/Counter

Bus

Control

T%D R%DP# P& P' P(

Address/Data

Counter

Inputs



Feature 8051 8052 8031

ROM (program space in b!es" #$ 8$ 0$ R%M (b!es" 1&8 &5' 1&8

Timers & &

I)O pins & & &

Seria* por! 1 1 1

In!err+p! so+rces ' 8 '

Comparison o! te )#*& +amil, Memers





Pin Description o! te )#*&

P7IP/Cer'ip

1234567

891011121314151617181920

40393837363534

33323130292827262524232221

P1.0P1.1P1.2P1.3P1.4P1.5P1.6

P1.7RST

(RXD)P3.0(TXD)P3.1

(T0)P3.4(T1)P3.5

XTAL2XTAL1

GND

(INT0)P3.2

(INT1)P3.3

(RD)P3.7(WR)P3.6

VccP0.0(AD0

)P0.1(AD1)P0.2(AD2

)P0.3(AD3)P0.4(AD4)P0.5(AD5)

P0.6(AD6)P0.7(AD7)

EA/VPP ALE/PROG

PSENP2.7(A15)P2.6(A14

)P2.5(A13

)P2.4(A12

)P2.3(A11)P2.2(A10)P2.1(A9)P2.0(A8)

8051



Pins o! )#*&（

'/"）

RS6（ pin 8）： reset

It is an input pin an' is actie hih（ normally lo1） (

6he hih pulse must &e hih at least 4 machine cycles(

It is a po1er-on reset(

Upon applyin a hih pulse to RS6, the microcontroller

1ill reset an' all alues in reisters 1ill &e lost(

Reset alues of some #%*) reisters

9ay )： Po1er-on reset circuit

9ay 4： Po1er-on reset 1ith 'e&ounce



Pins o! )#*&（

(/"）

/A（ pin 5)）： e!ternal access

6here is no on-chip ROM in #%5) an' #%54 (

6he /A pin is connecte' to GN7 to in'icate the co'e is

store' e!ternally(

/PSN ＆ A: are use' for e!ternal ROM(

;or #%*), /A pin is connecte' to <cc(

=/> means actie lo1(

/PSN（ pin 48）： proram store ena&le

6his is an output pin an' is connecte' to the O pin of the

ROM(



Pins o! )#*&（

"/"）

A:（ pin 5%）： a''ress latch ena&le

It is an output pin an' is actie hih(

#%*) port % proi'es &oth a''ress an' 'ata(

6he A: pin is use' for 'e-multiple!in the a''ress an'

'ata &y connectin to the G pin of the ?@:S5?5 latch(

I/O port pins

6he four ports P%, P), P4, an' P5(

ach port uses # pins(

All I/O pins are &i-'irectional(



;iure @-4 aB( 6A: Connection to #%*)

2

(#p+

1

(#p+

XTAL2

XTAL1

GND

Usin a uart3 crystal oscillator

9e can o&sere the freuency on the 6A:4 pin(



;iure @-4 &B( 6A: Connection to an !ternal Cloc2

Source

N

EXTERNALOSILLATOR

SIGNAL

XTAL2

XTAL1

GND

Usin a 66: oscillator

6A:4 is unconnecte'(



!ample .

;in' the machine cycle for

aB 6A: D ))(%*84 ME3

&B 6A: D )$ ME3(

Solution.

aB ))(%*84 ME3 / )4 D 84)($ 2E3F

machine cycle D ) / 84)($ 2E3 D )(%#* µs

&B )$ ME3 / )4 D )(555 ME3F

machine cycle D ) / )(555 ME3 D %(?* µs



R$S$T alue o! Some )#*& Registers.

####DPTR ###0SP

####PS1

####B####ACC

####PC

Reset alueRegister

RAM are all 2ero3



Po1er-On RS6 1ith 7e&ounce

EA/VPP

X1

X2RST

Vcc

10 !"

8.2 #

30 $"

9

31



Pins o! I/O Port

6he #%*) has four I/O ports

Port % （ pins 54-58）： P%（ P%(%～ P%(?） Port )（ pins )-#）： P)（ P)(%～ P)(?） Port 4（ pins 4)-4#）： P4（ P4(%～ P4(?） Port 5（ pins )%-)?）： P5（ P5(%～ P5(?） ach port has # pins(

Name' P%( （D%,),(((,?） , P)(, P4(, P5(

!： P%(% is the &it %（ :S） of P% !： P%(? is the &it ?（MS） of P%

6hese # &its form a &yte(

ach port can &e use' as input or output &i-'irectionB(



Registers

A

R%

R)

R5

R@

R4

R*

R?

R$

7PE 7P:

PC

7P6R

PC

Some #%*) )$-&it Reister

Some #-&itt Reisters of

the #%*)



Some Simple Instructions

MO dest4source 5 dest 6 source

MO A470'8 5A60'8

MO A4 79r9 5A6:r9 OR 0'8

MO R"47;'8 5R"6;'8

MO B4#+<8 5B6te content o! +<9t ,te o! RAM

MO DPTR470;("8

MO DP=47("8

MO DP8470;8

MO P&4A 5mo> A to port &

?ote &.MO A470'8 @ MO A40'8

A!ter instruction MO A40'8 te content o! 0'9t ,te o! RAM ill replace in Accumulator3

)#); )#*&MO A=40'8 MO A470'8

MO A=49r9 MO A479r9

MO B40'8

MO A=4EBF MO A40'8

?ote '.MO A4R( G MO A4(



ADD A4 Source FADAHSOURC

A77 A,$ FADAH$

A77 A,R$ FADAHR$

A77 A,$ FADAHJ$K or ADAHR$

%DD %,0-. /%%20-.3



S$TB it 5 it6&

C=R it 5 it6#

S6 C F CLD)

S6 P%(% F&it % from port % D)

S6 P5(? F&it ? from port 5 D)

S6 ACC(4 F&it 4 from ACCUMU:A6OR D)

S6 %* Fset hih 7* of RAM loc( 4%h

?ote.

C:R instruction is as same as S6

i(e.

C:R C FCLD%

ut follo1in instruction is only for C:R.

C:R A FAD%

it A''ressa&le

Pae 5*8,5$%



SUBB A4source 5A6A-source-CH

S6 C FCLD)

SU A,R* FADA-R*-)

ADC A4source 5A6AsourceCH

S6 C FCLD)

A7C A,R* FADAHR*H)



D$C ,te 5,te6,te-&

I?C ,te 5,te6,te&

INC R?7C A

7C @%E F J@%KDJ@%K-)

CP= A 5&9s complement!ample.

MO< A,**E FAD%)%)%)%) :%). CP: A

MO< P),A

ACA:: 7:AL

SMP :%)

?OP J R$T J R$TI

All are li2e #%#$ instructions(

CA::



A?= - OR= - R=

AMP:.MO< R*,#8E

AN: R*,%#E

RR K R= K RRC K R=C A

AMP:.

RR A



Structure of Assembly

language and Running an8051 program

OR4 0.

MO R5,6&5.

MO R7,6#.

MO %,60

%DD %,R5

%DD %,61&..ERE S9M: .ERE

END

7I6OR

PROGRAM

ASSM:R

PROGRAM

:INR

PROGRAM

OE

PROGRAM

Myfile(asm

Myfile(o&

Other o& fileMyfile(lst

Myfile(a&s

Myfile(he!



Memory mapping in 8051

ROM memory map in 8051 family

%%%%E

%;;;E

%%%%E

);;;E

%%%%E

?;;;E

#?*)

A6#8C*)#?*4

A6#8C*4

4%

7S*%%%-54

8% 32%

from Atmel Corporationfrom 7allas Semicon'uctor



RAM memory space allocation in te 8051

?;E

5%E

4;E

4%E

);E

)?E)%E

%;E

%?E

%#E

)#E

%%EReister an2 %

)Stac2 (Register Bank 1

Reister an2 4

Reister an2 5

it-A''ressa&le RAM

Scratch pa' RAM

8051 Flag bits and te !S"



8051 Flag bits and te !S"register :S; Regis!er

CL AC ;% RS) O<RS% P--

CHPS9(?Carry flag

ACPS9($ Auxiliary carry flag

--PS9(* Available to the user for general purpose

RS&PS9(@ Register Bank selector bit 1

RS#PS9(5 Register Bank selector bit 0

OPS9(4Overflow flag

--PS9()User define bit

PPS9(% arity flag !et"Reset odd"even parity

RS& RS# Register Bank Address

% % % %%E-%?E

% ) ) %#E-%;E

) % 4 )%E-)?E

) ) 5 )#E-);E



Instructions that Affect Flag Bits:

N&' X c*+ , 0 &- 1



E<amp*e

MO %,68.%DD %,6&-.

8 00111000&- 00101111 ==== ==============

'7 01100111CY0 %C1 :1

E<amp*eMO %,688.%DD %,6>.

88 10001000> 10010011 ==== ============== 11B 00011011

CY1 %C0 :0

E<amp*eMO %,6>C.%DD %,6'#.

>C 10011100'# 01100100 ==== ============== 100 00000000

CY1 %C1 :0



Addressing Modes Imme'iate

Reister

7irect Reister In'irect



Immediate Addressing Mode

MO< A,$*E

MO< A,"A"

MO< R$,$*E

MO< 7P6R,45@5E

MO< P),$*E

!ample .

Num U 5%

Q

MO<R%,NumMO< 7P6R,'ata)

Q

ORG )%%E

'ata).'& =IRAN>



Register Addressing ModeMO< Rn, A FnD%,((,?

A77 A, Rn

MO< 7P:, R$

MO< 7P6R, A

MO< Rm, Rn



Direct Addressing Mode

Althouh the entire of )4# &ytes of RAM can &e accesse' usin 'irecta''ressin mo'e, it is most often use' to access RAM loc( 5% ?;E(

MO< R%, @%E

MO< *$E, AMO< A, @ F MO< A, R@

MO< $, 4 F copy R4 to R$

F MO< R$,R4 is inali' T

S+R register and teir address

MO< %%E, $$E F MO< A,$$E

MO< %;%E, R4 F MO< , R4

MO< #%E,A F MO< P),A

it A''ressa&le Pae 5*8,5$%



Register Indirect Addressing Mode

In this mo'e, reister is use' as a pointer to the 'ata(

MO< A,Ri F moe content of RAM loc(9here a''ress is hel' &y Ri into A

iD% or ) B

MO< R),

In other 1or', the content of reister R% or R) is sources or taret in MO<, A77 an' SU

insructions(!ample.

9rite a proram to copy a &loc2 of )% &ytes from RAM location stertin at 5?h to RAMlocation startin at *8h(

Solution.

MO< R%,5?h F source pointer

MO< R),*8h F 'est pointer

MO< R4,)% F counter

:). MO< A,R%

MO< R),A

INC R%

INC R)

7N+ R4,:)

ump



On-Cip ROM Access

6his mo'e is 1i'ely use' in accessin 'ata elements ofloo2-up ta&le entries locate' in the proram co'eBspace ROM at the #%*)

MO<C A,AH7P6R

AD content of a''ress A H7P6R from ROM

?ote.ecause the 'ata elements are store' in the proramco'e B space ROM of the #%*), it uses the instructionMO<C instea' of MO<( 6he =C> means co'e(



!ample.

Assumin that ROM space startin at 4*%h contains =Eello(>, 1rite a proram to transfer the &ytes into RAM locations startin at @%h(

Solution.

ORG %

MO< 7P6R,ML7A6A

MO< R%,@%E

:). C:R A

MO<C A,AH7P6R

+ :4

MO< R%,A

INC 7P6R INC R%

SMP :)

:4. SMP :4

F-------------------------------------

ORG 4*%E

ML7A6A.7 =Eello>,%

N7

?otice te ?U== caracter 4#4 as end o! string and o e use te L instruction todetect tat3



!ample.

9rite a proram to et the ! alue from P) an' sen' !4 to P4, continuously (

Solution.

ORG %

MO< 7P6R, 6A)

MO< A,%;;E

MO< P),A

:%).

MO< A,P)

MO<C A,AH7P6R MO< P4,A

SMP :%)

F----------------------------------------------------

ORG 5%%E

6A). 7 %,),@,8,)$,4*,5$,@8,$@,#)

N7



MU: V 7I<

MU= AB 5WA D AX

MO< A,4*E

MO< ,$*EMU: A F4*EX$*ED%88

FD%E, AD88E MU= AB 5A D A/, D A mo'

MO< A,4*

MO< ,)%

MU: A FAD4, D*



Stack in te )#*&

6he reister use' to accessthe stac2 is calle' SPstac2 pointerB reister(

6he stac2 pointer in the#%*) is only # &its 1i'e,1hich means that it canta2e alue %% to ;;E(

9hen #%*) po1ere' up,the SP reister containsalue %?(

?;E

5%E

4;E

4%E

);E

)?E

)%E

%;E

%?E

%#E

)#E

%%EReister an2 %

)Stac2 (Register Bank 1

Reister an2 4

Reister an2 5

it-A''ressa&le RAM

Scratch pa' RAM



!ample.

MO< R$,4*E

MO< R),)4E

MO< R@,%;5E

PUSE $

PUSE )

PUSE @

%E

%AE

%8E

%#E

Start SPD%?E

4*

%E

%AE

%8E

%#E

SPD%#E

;5

)4

4*

%E

%AE

%8E

%#E

SPD%#E

)4

4*

%E

%AE

%8E

%#E

SPD%8E



=OOP and LUMP Instructions

D9N?

;ri!e a program !o c*ear %CC, !@enaAA !o !@e acc+m+*a!or !en !ime

So*+!ion

MO %,60/

MO R&,610

%4%IN %DD %,60

D9N? R&,%4%IN4 /repea! +n!i* R&0 (10 !imes"

MO R5,%



Oter conditional #umps

+ ump if AD%

N+ ump if A/D%

7N+ 7ecrement an' ump if A/D%

CN A,&yte ump if A/D&yte

CN re,'ata ump if &yte/D'ata

C ump if CLD)

NC ump if CLD%

ump if &itD)

N ump if &itD%

C ump if &itD) an' clear &it



CL?$ 4 L?C

$%ercise.

9rite a proram that compare R%,R)(

If R%YR) then sen' ) to port 4,

else if R%ZR) then sen' %;;h to port 4,else sen' % to port 4(



$A%% &nstructions

Another control transfer instruction is the CA::

instruction, 1hich is use' to call a su&routine(

=CA==Nlong call

In this 5-&yte instruction, the first &yte is the opco'e

an the secon' an' thir' &ytes are use' for the

a''ress of taret su&routine( 6herefore, :CA:: can

&e use' to call su&routines locate' any1here 1ithin

the $@ &yte a''ress space of the #%*)(



ACA== Nasolute call

ACA:: is 4-&yte instruction in contrast to :CA::,1hich is )5 &ytes( Since ACA:: is a 4-&yte instruction,the taret a''ress of the su&routine must &e 1ithin 4

&ytes a''ress &ecause only )) &its of the 4 &ytes are use'for the a''ress( 6here is no 'ifference &et1een ACA::an' :CA:: in terms of sain the proram counter onthe stac2 or the function of the R6 instruction( 6he only'ifference is that the taret a''ress for :CA:: can &e

any1here 1ithin the $@ &yte a''ress space of the #%*)1hile the taret a''ress of ACA:: must &e 1ithin a 4-

&yte rane(

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Embedded Systems-8051 Microcontroller