IV B.Tech I Semester –Embedded Systems________________________________________________________________________________1. Intel 8086 has - 1 -a. 4 bytes queueb. 4 bytes queuec. 4 bytes queued. 4 bytes queue2. Semiconductor memory has ___ memory cella. slowb. fastestc. lowestd. highest3. Which of the following is a 16-bit microprocessor?a. Intel 8085b. Intel 8086c. Zilog 0d. Motorola 68004. Address bus of Intel 8085 is ____ bit widea. 2b. 4c. 8d. 165. _____ is the first computer designed to support real-time operation.a. Whirlpoolb. whirllandc. whirlswindd. whirlwind6. The first microprocessor isa. Intel 3003b. Intel 4004c. Intel 5005d. Intel 60067. The _____ was the first hand held calculator to perform transcendentalfunctionsa. HP-32b. HP-33c. HP-34d. HP-358. _____ technology has allowed us to put a complete CPU on a single chipa. LSIb. MSIc. VLSId. SSI9. Example of embedded computer system isa. personal computerb. fax machinec. printerd. keyboard10. Modern ___ processors can execute one instruction per clock cyclea. RISCb. CISCc. RISKd. CISK11. be A good specification shoulda. ambiguous

b. nonfunctionalc. specificd. unambiguous12. FPGA stands fora. File-programmable gate arraysb. Final-programmable gate arraysc. Finite-programmable gate arraysd. Field-programmable gate arrays13. Design phase will usually bea. top-downb. bottom-upc. randomd. centre fringing14. The railway-reservation system currently operational in India can beclassified as aa. Batch processingb. real-time systemc. on-line systemd. expert system15. One good way to refine at least the user interface portion of a system'srequirements is to build a __.a. roll-upb. set-upc. drill-upd. mock-up16. ____ serves as the contract between the customer and the architects.a. Architectureb. Specificationc. Componentsd. Requirements17. Which is nonfunctional requirement?a. designb. codec. costd. test18. Which is nonfunctional requirement?a. designb. codec. performanced. test19. The ___ should be understandable enough so that someone can verify thatit meets system requirements and overall expectations of the systema. Architectureb. Specificationc. Componentsd. Requirements20. Requirements form consists ofa. Deviceb. powerc. testingd. documentation21. UML includes ____ diagramsa. sevenb. eightc. nine

d. ten22. ._________ is a special kind of association, representing a structuralrelationship between a whole and its partsa. Dependencyb. Aggregationc. Generalizationd. Realization23. An ___________ is a named property of a class that describes a range ofvalues that instance of the property may helda. itemb. attributec. operationd. entity24. A_________ is a semantic relationship between two things in which achange to one thing may affect the semantics of their thinga. dependencyb. generalizationc. realizationd. message25. An ________ is a structural relationship that describes a set of links, a linkbeing a connection among objectsa. interactionb. associationc. interfaced. dependency26. A_________ is a specialization relationship in which objects of thespecialized element are substitutable for objects of the generalized elementa. dependencyb. generalizationc. realizationd. message27. UML stands fora. Uniform Modeling Languageb. United Modeling Languagec. United Modeling Languaged. Unique Modeling Language28. UML is a _________ modeling languagea. general -purposeb. object-purposec. architecture-purposed. code-purpose29. We build models so that we can better_____ the system we ate developinga. misunderstandb. understandc. guided. misguide30. Which one of the following view express the requirements of the system?a. Use caseb. Designc. Processd. Implementation31. In an object-oriented approach the main building block of all s/w isthe______.a. classb. function

c. procedured. module32. An object contains _______________.a. attributes & methodsb. only attributesc. only methodsd. classes33. ________things are the names of UML modelsa. Structuralb. Behavioralc. Groupingd. Annotational34. .________ Things are the dynamic parts of UML modelsa. Structuralb. Behavioralc. Groupingd. Annotational35. An ______ is a collection of operations that specify a service of a class orcomponenta. interfaceb. active classc. use cased. interaction36. Which one of the following is not structural thing?a. classb. packagec. use cased. collaboration37. common use of class diagrams is (S)a. to model simple interactionsb. to model object diagramc. to model the vocabulary of a systemd. to model the life cycle of a system.38. _______ diagrams let you model static data structuresa. objectb. classc. stated. component39. Aggregation is a _________ kind of relationshipa. is-ab. to-ac. was-ad. has-a40. A ____ diagram is somewhat similar to a hardware timing diagrama. classb. objectc. activityd. sequence41. Which one of the following diagrams has the sequence number?a. Sequenceb. collaborationc. activityd. use case42. Collaboration diagrams use _______ relationshipa. dependency

b. associationc. generalizationd. message43. Dependency relationship is rendered asa.b. ________________________c.d.44. Association is relationship is rendered asa.b. _____________c.d.45. Generalization relationship is rendered asa.b. ________________________c.d.46. Aggregation relationship is rendered asa.b. _______________________c.d.47. Use _________ only when you have an is a- kind-of relationshipa. dependencyb. associationc. aggregationd. generalization48. Use _________ only when you have an ''is -a- kind-of'' relationshipa. dependencyb. associationc. aggregationd. generalization49. Use ________ only when the relationship you are modeling is notstructurala. dependenciesb. associationsc. aggregationsd. generalizations50. ___________ is specification of an asynchronous stimulus communicatedbetween instancesa. Signalb. Componentc. Noded. Subsystem51. A(an) _______ diagram is essentially an instance of a class diagrama. interactionb. objectc. use cased. activity52. A _____ is an asynchronous occurrencea. fileb. typec. signald. view

53. Which one of the following diagram is an interaction diagram?a. classb. objectc. sequenced. statement54. A_________ diagram is an interaction diagram that emphasizes thestructural organization of the objects that sends and receive messagesa. collaborationb. objectc. sequenced. component55. The UMLs _____ provide a semantic backplane that contains all the portsof all the models of a system, each part related to one another in aconsistent fashiona. adornmentsb. specificationsc. common divisionsd. extension mechanisms56. ._________ is a special kind of association, representing a structuralrelationship between a whole and its partsa. Dependencyb. Aggregationc. Generalizationd. Realization57. A __________ relationship is rendered as a solid line with a hollowarrowhead pointing to the parenta. dependencyb. aggregationc. generalizationd. realization58. A___ diagram shows the configuration of runtime processing nodes andthe components that live on thema. use caseb. activityc. deploymentd. component59. A_________ is a semantic relationship between two things in which achange to one thing may affect the semantics of their thinga. dependencyb. generalizationc. realizationd. message60. An ________ is a structural relationship that describes a set of links, a linkbeing a connection Among objectsa. interactionb. associationc. interfaced. dependency61. A_________ is a specialization relationship in which objects of thespecialized element are substitutable for objects of the generalized elementa. dependencyb. generalizationc. realizationd. message62. A______ is a semantic relationship between classifiers where in one

classifier specifies a contract that another classifier guarantees to carry outa. dependencyb. generalizationc. realizationd. message63. UML includes ____ diagramsa. sevenb. eightc. nined. ten64. Which one of the following diagram address the dynamic view of asystem?a. classb. objectc. componentd. state chart65. Which one the following diagram address the static view of a system?a. interactionb. activityc. state chartd. component66. A________ extends the semantics of a UML building block, allowing you toadd new rules or modify existing onesa. tagged valueb. stereotypec. constraintd. adornments67. A________ extends the vocabulary to the UML, allowing you to create newkinds of building block that are derived from existing ones out that arespecific to your problema. tagged valueb. stereotypec. constraintd. adornments68. What is the fifth bit of PSW?a. CYb. FOc. ACd. OV69. What is the first bit of PSW?a. CYb. FOc. ACd. reserved for future use70. Full duplex serial data receiver/transmitter isa. SBUFb. SCONc. PCONd. TMOD71. A functioning computer must have memory for program code bytes,commonly in ______.a. ROMb. RAMc. RAAMd. ROOM

72. _____ memory for variable data that can be altered as the program runsa. ROMb. RAMc. RAAMd. ROOM73. The function of DPH isa. Addressing internal memoryb. Addressing external memoryc. Interrupt enable controld. Power control74. The 8051 contains ______ 16-bit registersa. oneb. twoc. threed. four75. The DPTR register is made up of two ___ registersa. 4-bitb. 8-bitc. 16 bitd. 32-bit76. The 8051 contains ___ general-purpose registersa. 17b. 24c. 34d. 4177. The 8051 has ___ math flagsa. 1b. 2c. 3d. 478. What are control registers?a. TCON and IEb. IE and SBUFc. PC and DPTRd. IP and PC79. ALE stands fora. Address Latch Enableb. Add Latch Enablec. Accumulator Latch Enabled. Access Latch Enable80. The ____ register is used with the A register for multiplication and divisionoperationsa. Eb. Cc. Bd. D81. PSW stands fora. Program Start Wordb. Program Start Workc. Program Status Wordd. Program Status work82. The 8-bit ___ register is used by the 8051 to hold internal RAM addressa. Stack Pointerb. Ac. B

d. IP83. When ____ is used as an address bus to external memory, internal controlsignals switch the address lines to the gates of the FETsa. port 0b. port 1c. port 2d. port 384. _____ provides the high byte of the memory address the entire memoryread/write cyclea. port 0b. port 1c. port 2d. port 385. The 8051 accesses ____ whenever certain program instructions areexecuteda. Internal RAMb. External RAMc. Internal RPMd. External ROM86. External RAM is accessed bya. DPTRb. PCONc. TMODd. SCON87. ___ pins may serve as inputs, outputs, or, when used together as abidirectional low-order address and data bus for external memorya. port 0b. port 1c. port 2d. port 388. ____ pins have no dual functionsa. port 0b. port 1c. port 2d. port 389. ____ pins are momentarily changes by the address control signal whensupplying the high byte of a 16- bit addressa. port 0b. port 1c. port 2d. port 390. ____ latches remain stable when external memory is addresseda. port 0b. port 1c. port 2d. port 391. ____ is an input/output port similar to port 1a. port 0b. port 1c. port 2d. port 392. Each pin of ___ may be individually programmed to be used either as I/Oor as one of the alternate functionsa. port 0b. port 1

c. port 2d. port 393. The 8751 solution works well if the program will fit into _____a. 2Kb. 4Kc. 8Kd. 16K94. _____ is accessed whenever the external access pin is connected togrounda. Internal RAMb. External RAMc. Internal RPMd. External ROM95. The register containing Gate and C/Ta. TMODb. TCONc. SCONd. PCON96. The register containing IE0 and IE1a. TMODb. TCONc. SCONd. PCON97. The register containing M0 and M1a. TMODb. TCONc. SCONd. PCON98. ______ in mode 3 becomes two completely separate 8-bit countersa. Timer 3b. Timer 2c. Timer 1d. Timer 099. The band rate for the serial port in mode 0 for a 6 megahertz crystala. 500khzb. 600khzc. 700khzd. 800khz100. The largest possible time delay for a timer in mode 1 if a 6 megahertzcrystal is useda. 0.1131b. 0.1113c. 0.131d. 0.3111101. To find the frequency of a pulse train, ____ is requireda. Timerb. pulsarc. counterd. controller102. ______ is dedicated solely to the two timersa. TCONb. TMODc. DPTRd. DPH103. ______ has control bits and flags

a. TCONb. TMODc. DPTRd. DPH104. What is the seventh bit of TMOD?a. gateb. M1c. M0d. C/T105. TCON stands fora. Timer Connectionb. Training Connectionc. Timer Controld. Timer Condition106. TMOD stands fora. Time Mode Controlb. Timer Mode Controlc. Time Modulationd. Time Moderate107. If the crystal frequency is 6.0 megahertz, then the timer clock will havea frequency of ____ KHza. 200b. 300c. 400d. 500108. In order for oscillator clock pulses to reach the timer, the C/T bit in theTmod register must be set to _____.a. 0b. 1c. 2d. 3109. _____ can be used for band rate generation for the serial porta. Timer 3b. Timer 2c. Timer 1d. Timer 0110. The registers used by SBUF area. read and writeb. write and executec. read and executed. Write only111. If timer 1 is not run in timer mod 2 for mod 1 then the baud rate isa. fbaud = 2SMOD/12d * ( timer 1 overflow frequency )b. fbaud = 2SMOD/32d * ( timer 1 overflow frequency )c. fbaud = 2SMOD/64d * ( timer 1 overflow frequency )d. fbaud = 2SMOD/256d * ( timer 1 overflow frequency )112. Baud rate for multiprocessor modea. fbaud = 2SMOD./12d * (Oscillator frequency)b. fbaud = 2SMOD/32d * (Oscillator frequency)c. fbaud = 2SMOD/64d * (Oscillator frequency)d. fbaud = 2SMOD/256d * ( timer 1 overflow frequency )113. Shift frequency is also called asa. Counterb. Timerc. Baud rate

d. Oscillator frequency114. Serial baud rate modify bit isa. TMODb. PMODc. b CMODd. SMOD115. SBUF is physically ___ register(s)a. oneb. twoc. threed. four116. The 8051 has a serial data communication circuit that uses register ____to hold dataa. SBUFb. SCONc. PCONd. TCON117. Register _____ controls data communicationa. SBUFb. SCONc. PCONd. TCON118. Register _____ controls data rates, and pins RXD and TXDa. SBUFb. SCONc. PCONd. TCON119. SCON stands fora. Serial Mode Controlb. Serial Port Controlc. Serial Function Controld. Serial Change Co120. PCON stands fora. Power Mode Controlb. Serial Change Controlc. Power Function Controld. Serial Change Control121. The register containing TB8 and RB8a. SBUFb. SCONc. PCONd. TCON122. The registers containing PD and IDLa. SBUFb. SCONc. PCONd. TCON123. The registers containing TI and RIa. SBUFb. SCONc. PCONd. TCON124. The registers containing GF1 and GF0a. SBUFb. SCON

c. PCONd. TCON125. The address (HEX) of the SERIAL interrupt isa. 0021b. 0022c. 0023d. 0024126. The address (HEX) of the TF0 interrupt isa. 000Ab. 000Bc. 0001d. 000D127. The address (HEX) of the IE0 interrupt isa. 0003b. 0002c. 0001d. 0000128. Position of the Es bit in IE isa. 6b. 5c. 4d. 3129. IE register stands fora. Internet Explorerb. Interpret Enablec. Interrupt Enabled. Internet Enable130. IP register stands fora. Internet Priorityb. Interrupt Producerc. Internet producerd. Interrupt Priority131. _____ interrupts are provided in the 8051a. Threeb. Fourc. Fived. Six132. The register containing EA and ESa. IEb. IPc. SCONd. PCON133. The register containing EA and ESa. IEb. IPc. SCONd. PCON134. The register containing PX0 and PX1a. IEb. IPc. SCONd. PCON135. The register containing PT0 and PT1a. IEb. IP

c. SCONd. PCON136. What are the bits not implemented in IP?a. 1 and 2b. 3 and 4c. 5 and 6d. 6 and 7137. Which bit is not implemented in IE?a. 4b. 5c. 6d. 7138. Position of the PS bit in IP isa. 1b. 2c. 3d. 3139. FORTH is a ____ languagea. High-levelb. Low-levelc. Middle-leveld. Machine140. ______ languages are not transportablea. High-levelb. Low-levelc. assembly-leveld. machine141. The sequence of events that happen during a typical fetch operation isa. Pc-mar-memory-MDR-IRb. PC-memory-MDR-IRc. PC-memory-IRd. PC-MAR-memory-IR142. Which of the following is volatile?a. Bubble memoryb. RAMc. ROMd. Magnetic disk143. The cost for storing a bit is minimum ina. cacheb. registerc. RAMd. Magnetic tape144. Von Neumann architecture isa. SISDb. SIMDc. MIMDd. MISD145. Nibble length in bits isa. 1b. 4c. 8d. 16146. For each instruction in program memory, the CPU goes through aa. decode-fetch-execute sequenceb. execute-store-decode sequence

c. fetch-decode-execute sequenced. fetch-execute-decode sequ147. The heart of any computers is thea. CPUb. memoryc. I/O unitd. Disks148. Which memory is volatile?a. RAMb. ROMc. EPROMd. PROM149. A microprocessor with 12 address lines is capable of addressinga. 1024 locationsb. 2048 locationsc. 4096 locationsd. 64K locations150. The first operating system used in micro-processor isa. DOSb. DOSc. CP/Md. Multics151. Programming in a language that actually controls the [path of signals ordata within the computer is calleda. micro programmingb. systems programmingc. assembly language programmingd. Machine language programming152. An assembler that runs on one machine but produces machine code foranother machine is calleda. simulatorb. emulatorc. cross-assemblerd. boot-strap loader153. The three main components of a digital computer system area. memory, I/O, DMAb. ALU, CPU, memoryc. memory, CPU, I/Od. control circuits, ALU, registers154. A ____ program is loaded from disk into RAM and tests the machinelanguagefile under user control.a. buggingb. debuggingc. compiled. assemble155. What do the contents of stack pointer specify?a. address of the bottom of stackb. address of the top of stackc. contents of the bottom of stackd. address of the top of stack156. A kilobyte, also referred to as K, is equal toa. 1000 bytesb. 1024 bytesc. 2048 bytesd. 512 bytes

157. Run-time errors also called asa. conceptual errorsb. bugsc. faultsd. syntax errors158. The ____ errors in the source file are corrected by the programmer andthe program re-assembleda. run-timeb. compile-timec. syntaxd. conceptual159. The symbol used for action box isa.b.c.d.160. The symbol used for bubble isa.b.c.d.161. The symbol used for start and end isa.b.c.d.162. The symbol used for decision making isa.b.c.d.163. A list of instructions is classified asa. softwareb. hardwarec. programmed. data164. The third part in 8051 instruction syntax isa. labelb. instructionc. commentsd. assembler165. In 8051, labels should be followed bya. :b. ;c. .d. ,166. The length of characters length in 8051 isa. 6b. 7c. 8d. 9167. The first part in 8051 instruction syntax isa. labelb. instructionc. comments

d. assembler168. Part 1 in 8051 instruction isa. mnemonicb. sourcec. destinationd. comment169. Part 2 in 8051 instruction isa. mnemonicb. sourcec. destinationd. comment170. Part 3 in 8051 instruction isa. mnemonicb. sourcec. destinationd. comment171. Example of code address label isa. fred,2b. fred:2:c. fred.2d. fred-2:172. Example of code address label isa. ad12:3:b. ad123:h:c. ad123,h;d. ad123.4h:173. Comments begin with ____ in 8051a. :b. ;c. .d. ,174. When using _____, the upper nibble of A and the upper nibble of theaddress location in Rp do not exchangea. XCHb. XCHDc. XCHCd. XCHE175. Only registers ____ may be used for indirect addressinga. A0 or A1b. B0 or B1c. S0 or S1d. R0 or R1176. SP register stands fora. stack pointerb. stable pointerc. standard pointerd. selection pointer177. A _____ register copies data from the source address to the stacka. MOVb. MOV Xc. PUSHd. POP178. A ____ opcode copies data from the stack to the destination addressa. MOVb. MOV X

c. PUSHd. POP179. Data exchange can be done bya. CXHb. XCHc. HCXd. CHX180. The addressing mode used in an instruction of the form ADD X,Y isa. absoluteb. immediatec. indirectd. index181. The addressing mode used in the instruction PUSH B isa. directb. registerc. register indirectd. immediate182. The most relevant addressing mode to write position independent codeisa. direct modeb. indirect modec. relative moded. indexed mode183. In order to save accumulator value onto the stack, which of the followinginstructions may be used?a. PUSH PSWb. PUSH Ac. PUSH SPd. POP PSW184. The mnemonic symbol for immediate data is the ___ signa. #b. @c. &d. <<185. The mnemonic symbol for indirect addressing is the ___ signa. #b.@c. &d. <<186. All exchanges use register ____ .a. Ab. Bc. Cd. D187. _____ is normally used with external RAM I/O addressesa. MOVb. MOV Xc. PUSHd. POP188. If A=A9h then RL A isa. 52hb. 51hc. 53hd. 54h189. If A=53h then RL A is

a. B6hb. C6hc. D6hd. A6h190. The contents of after the following operations MOV A,#0FFh MOVR0,#77h ANL A,R0 MOV 15h,A CPL Aa. 77hb. 88hc. 99hd. 66h191. Find a number that, when XORed to the A register, results in the number3Fh in Aa. FBhb. 5Ahc. 3Ahd. ABh192. If A=A5h then SWAP A in binary isa. 10101010b. 01011010c. 11101110d. 01100101193. If A=A5h then RR A isa. B2hb. D3hc. B3hd. D2h194. 8051 mnemonic code for NOT Boolean operator isa. ANLb. ORLc. XRLd. CPL195. 8051 mnemonic code for AND Boolean operator isa. ADLb. ANLc. ALN

d. NDL196. 8051 mnemonic code for OR Boolean operator isa. RLb. ROLc. ORLd. LOR197. 8051 mnemonic code for XOR Boolean operator isa. XLb. RLc. OXLd. XRL198. To clear the A register to 00h isa. CL Ab. CLR Ac. CR Ad. CRL A199. The clear bit 5 of the A register isa. CLR ACC.4b. CLR ACC.5

c. CLR ACC.6d. CLR ACC200. Complement the lower nibble of RAM location 2Aha. AAhb. 2Ahc. DAhd. 25h201. Complement the upper nibble of RAM location 2Aha. AAhb. 2Ahc. DAhd. 25h202. Find a number that, when XORed to the A register, results in the number3Fh in Aa. OAhb. OAhc. 3Ahd. ABh203. The C flag is set to 1 if the adjusted number exceeds ___ BCDa. 88b. 99c. 77d. 66204. Only ADD and ADDC are adjusted to BCD by _____.a. DB Ab. DC Ac. DA Ad. DD A205. The ___ flag is effected by every instruction executeda. carryb. auxiliary carryc. overflowd. parity206. Register ___ is the destination address for subtractiona. Ab. Bc. Cd. D207. Addition of 49 and 38 in BCD isa. 80b. 83c. 82d. 81208. Which is not arithmetic flag?a. Cb. ACc. Pd. B209. Mnemonic code for decimal adjust isa. AD Ab. DA Ac. ADJd. DEC A210. What is the value of A? MOV A,#3Ah DEC Aa. 39h

b. 3Bhc. 3Chd. 3Dh211. Addition of 5Fh and 1Bh(unsigned) isa. 2Chb. 3Chc. 1Chd. 0Ch212. Addition of FFh and 1Bh(unsigned) isa. 0Ahb. 1Ahc. 2Ahd. 3Ah213. Addition of 2Dh and 4Bh(unsigned) isa. 75hb. 76hc. 77hd. 78h214. Mnemonic code for multiplication in 8051 isa. MUL A Bb. MUL ABc. MU ABd. ML A B215. Mnemonic code for subtraction in 8051 isa. SUB A Bb. SUBB A Bc. DIV A,Bd. DIV AB216. Mnemonic code for division in 8051 isa. DV ABb. DIV A Bc. DIV A,Bd. DIV AB217. The OV flag will be set if A X Ba. <FFhb. > FFhc. = FFhd. AAh218. Register ___ is the destination address for subtractiona. Ab. Bc. Cd. D219. The C flag is set to 1 if the adjusted number exceeds ___ BCDa. 88b. 99c. 77d. 66220. Addition of FFh and 1Bh(unsigned) isa. 0Ahb. 1Ahc. 2Ahd. 3Ah221. Which is not arithmetic flag?a. C

b. ACc. Pd. O222. DA A mnemonic code is used fora. Binary adjustb. Decimal adjustc. Hex adjustd. Octal adjust223. Mnemonic code to add a 1 to the sourcea. IN sourceb. INC sourcec. NIC sourced. NC source224. Mnemonic code Multiply the bytes in A and Ba. MUL A Bb. MUL Ac. MUL ABd. MUL B225. Mnemonic code to add the contents of A, the immediate number n, andthe C flaga. ADDC A,#nb. ADDC A,addc. ADDC A,Rrd. ADDC A,@Rp226. Mnemonic code to add the contents of A, the direct address contents,and the C flaga. ADDC A,#nb. ADDC A,addc. ADDC A,Rrd. ADDC A,@Rp227. Mnemonic code to add the contents of A, register Rr, and the C flaga. ADDC A,#nb. ADDC A,addc. ADDC A,Rrd. ADDC A,@Rp228. Mnemonic code to add the contents of A, the contents of the indirectaddress in Rp, and the C flaga. ADDC A,#nb. ADDC A,addc. ADDC A,Rrd. ADDC A,@Rp229. If A=FFh and B=2Ch, then DIV AB isa. A=05h and B=23hb. A=04h and B=22hc. A=00h and B=23hd. A=05h and B=20h230. If A=05h and B=23h, then DIV AB isa. A=6Ch and B=23hb. A=4Dh and B=22hc. A=00h and B=23hd. A=00h and B=05h231. If A=00h and B=05h, then DIV AB isa. A=6Ch and B=23hb. A=00h and B=00hc. A=00h and B=23h

d. A=00h and B=5Eh232. Byte jump isa. JNBb. JBCc. AJMPd. CJNF233. Byte jump isa. JNBb. JBCc. AJMPd. JNZ234. Unconditional jump isa. CJNFb. AJMPc. DJNZd. JZ235. Mnemonic code to jump to the relative address if A is not 0a. JNZ raddb. JZ raddc. JZd. JNZ236. Mnemonic code to pop 2 bytes from the stack into the program countera. NOPb. RETic. RETd. RETN237. A ____ is a program that may be used many times in the execution of alarger programa. jumpb. callc. subroutined. router238. Relative range of jumper or call instructions isa. +126d to -127db. +127d to -128dc. +128d to -129dd. +128d to -128d239. Absolute range of jumper or call instructions isa. 4K pagesb. 3K pagesc. 2K pagesd. 1K pages240. Long absolute range of jumper or call instructions isa. 0000f to FFFFhb. 0000f to EEEEhc. 0000f to DDDDhd. 0000f to CCCCh241. Mnemonic code for jump relative if the carry flag is set to 1a. JC raddb. JNC raddc. JB b,raddd. JNB b,radd242. Mnemonic code for jump relative if addressable bit is reset to 0a. JC raddb. JNC radd

c. B b,raddd. JNB b,radd243. Mnemonic code for jump relative if addressable bit is set to 1a. JC raddb. JNC raddc. JB b,raddd. JNB b,radd244. Mnemonic code to compare the context of the A register with theimmediate number na. CJNE A,#n,raddb. CJNF #n,raddc. CJNE A,@n,raddd. CJNF A,n,radd245. Mnemonic code to compare the context of the register Rn with theimmediate number na. CJNE A,#n,raddb. CJNF #n,raddc. CJNF Rn,#n,raddd. CJNF Rn,n,radd246. Mnemonic code to jump to the relative address if A is 0a. JNZ raddb. JZ raddc. JZd. JNZ247. Which is not byte jump?a. JMPb. CJMPc. CJNZd. JNZ248. Which is not bit jump?a. JCb. JNCc. JBd. JMP249. Mnemonic code to decrement the direct address by 1 and jump to therelative address if the result is not 0a. DJNZb. JZc. JNZd. CJNE250. Mnemonic code to call the subroutine located any where in programmemory spacea. ACALLb. SCALLc. RETd. LCALL251. A ____ opcode is encountered at the end of the subroutinea. ACALLb. ACALLc. SCALLd. RET252. Which is not unconditional jump?a. AJMPb. LJMPc. SJMP

d. JNC253. Mnemonic code to jump relative if the carry flag is reset to 0a. JC raddb. JNC raddc. JB b,raddd. JNB b,radd254. Mnemonic code to jump relative if addressable bit is set, and clear theaddressable bit to 0a. JC raddb. JNC raddc. JB b,raddd. JBC b,radd255. Mnemonic code to compare the contents of A register with the contentsof the direct addressa. CJNE A,add,raddb. CJNE add,raddc. CJNE addd. CJNE radd256. Mnemonic code to do nothing and go to the next instructiona. NPb. PNc. NPOd. NOP257. Mnemonic code to jump to relative addresseda. AJMP saddb. LJMP laddc. SJMP raddd. JMP258. Unconditional jump isa. JNCb. JBCc. SJMPd. CJNE259. Byte jump isa. JBCb. JNZc. NOPd. JMP260. Bit jump isa. JNBb. NOPc. JNZd. JZ261. NOP isa. bit jumb. byte jumpc. nibble jumpd. unconditional jump262. Which is not arithmetic flag?a. Cb. ACc. Pd. O263. Interrupt return isa. RET

b. RETURNc. RETId. RETUI264. The register containing ET1 and ET2a. IEb. IPc. SCONd. PCON265. What is the fifth bit of PSW?a. CYb. FOc. ACd. OV266. What is the first bit of PSW?a. CYb. FOc. ACd. reserved for future use267. Full duplex serial data receiver/transmitter isa. SBUFb. SCONc. PCONd. TMOD268. The register containing PX0 and PX1a. IEb. IPc. SCONd. PCON269. Mnemonic code to pop 2 bytes from the stack into the program counterand reset the interrupt enable flip-flopsa. RETb. RTNc. RETId. REI270. The interrupt subroutine address of IE0 isa. 0003b. 000Bc. 0013d. 001B271. The interrupt subroutine address of TF0 isa. 0003b. 000Bc. 0013d. 001B272. The interrupt subroutine address of IE1 isa. 0003b. 000Bc. 0013d. 001B273. The interrupt subroutine address of TF1 isa. 0003b. 000Bc. 0013d. 001B274. The interrupt subroutine address of SERIAL is

a. 0003b. 000Bc. 0023d. 001B275. The 8051 ha a total of ____ interruptsa. 2b. 3c. 4d. 5276. The ___ bit is the global interrupt enable bita. IEb. EAc. IPd. OV