Embedded FIFO Generator v1.0 LogiCORE IP Product Guide · 2021. 1. 15. · 2. The Embedded FIFO Generator core supports the UniSim simulation model. 3. For the supported versions

Embedded FIFO Generatorv1.0

LogiCORE IP Product Guide

PG327 (v1.0) July 14, 2020

https://www.xilinx.com

Table of ContentsChapter 1: Introduction.............................................................................................. 4

Features........................................................................................................................................4IP Facts..........................................................................................................................................6

Chapter 2: Overview......................................................................................................7Navigating Content by Design Process.................................................................................... 7Core Overview..............................................................................................................................7Applications................................................................................................................................41Licensing and Ordering............................................................................................................ 44

Chapter 3: Product Specification......................................................................... 45Performance.............................................................................................................................. 45

Chapter 4: Designing with the Core................................................................... 46General Design Guidelines.......................................................................................................46Initializing the FIFO Generator................................................................................................ 48FIFO Usage and Control........................................................................................................... 49Clocking...................................................................................................................................... 62Resets..........................................................................................................................................65Actual FIFO Depth..................................................................................................................... 68Latency........................................................................................................................................69Special Design Considerations................................................................................................ 75

Chapter 5: Design Flow Steps.................................................................................79Customizing and Generating the Native Core.......................................................................79Customizing and Generating the AXI Core............................................................................ 84Constraining the Core...............................................................................................................84Simulation.................................................................................................................................. 85Synthesis and Implementation................................................................................................85

Appendix A: Verification, Compliance, and Interoperability...............86Simulation.................................................................................................................................. 86

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Appendix B: Debugging.............................................................................................87Finding Help on Xilinx.com...................................................................................................... 87Debug Tools............................................................................................................................... 88Simulation Debug......................................................................................................................89Hardware Debug....................................................................................................................... 89Interface Debug........................................................................................................................ 89

Appendix C: Additional Resources and Legal Notices............................. 91Xilinx Resources.........................................................................................................................91References..................................................................................................................................91Revision History......................................................................................................................... 91Please Read: Important Legal Notices................................................................................... 92



Chapter 1

IntroductionThe Xilinx® LogiCORE™ IP Embedded FIFO Generator core is a fully verified first-in first-out(FIFO) memory queue for applications requiring in-order storage and retrieval. The core providesan optimized solution for all FIFO configurations and delivers maximum performance (up to 500MHz) while utilizing minimum resources. Delivered through the Vivado® Design Suite, you cancustomize the width, depth, status flags, memory type, and the write/read port aspect ratios.

The Embedded FIFO Generator core supports Native interface FIFOs, AXI Memory Mappedinterface FIFOs and AXI4-Stream interface FIFOs. Native interface FIFO cores are optimized forbuffering, data width conversion and clock domain decoupling applications, providing orderedstorage and retrieval.

AXI Memory Mapped and AXI4-Stream interface FIFOs are derived from the Native interfaceFIFO. Two AXI Memory Mapped interface styles are available: AXI4 and AXI4-Lite.

Features• Supports Native, AXI4-Stream, AXI4, and AXI4-Lite interfaces.

• FIFO depths up to 4194304 entries.

• Independent or common clock domains.

• Fully configurable using the Xilinx Vivado® Design Suite IP catalog.

Native FIFO Specific Features

• FIFO data widths from 1 to 4096 bits.

• Symmetric or Non-symmetric aspect ratios (read-to-write port ratios ranging from 1:8 to 8:1).

• Synchronous reset option.

• Selectable memory type (block/UltraRAM and distributed RAM).

• Option to operate in Standard or first-word fall-through modes (FWFT).

• Full and Empty status flags, and Almost Full and Almost Empty flags for indicating one-word-left.

• Programmable Full and Empty status flags, set by user-defined constant(s).

Chapter 1: Introduction



• Hamming error injection and correction checking (ECC) support for block RAM and UltraRAMFIFO configurations.

• Configurable read latency for Standard Read Mode.

• Dynamic Power Gating.

AXI FIFO Features

• FIFO data widths:

○ AXI4-Stream: 1 to 4096 bits

○ AXI4: 32, 64....... 1024 (multiples of 2) bits

○ AXI4-Lite: 32, 64 bits

• Supports AXI4 memory mapped and AXI4-Stream interface protocols: AXI4, AXI4-Stream, andAXI4-Lite.

• Symmetric aspect ratios.

• Asynchronous active-Low reset.

• Selectable memory type (block/UltraRAM, or distributed RAM).

• Selectable application type (Data FIFO and Packet FIFO).

○ Packet FIFO feature is available only for common/independent clock AXI4-Stream FIFOand common clock AXI4 FIFOs.

• Operates in first-word fall-through mode (FWFT).

• Auto-calculation of FIFO width based on AXI signal selections and data and address widths.

• Hamming error injection and correction checking (ECC) support for block / UltraRAM FIFOconfigurations.

• Configurable programmable Full/Empty flags as sideband signals.




IP FactsLogiCORE™ IP Facts Table

Core Specifics

Supported Device Family Versal™ ACAP

Supported User Interfaces Native, AXI4-Stream, AXI4, AXI4-Lite

Provided with Core

Design Files System Verilog RTL

Example Design N/A

Test Bench N/A

Constraints File XDC

Simulation Model N/A

Supported S/W Driver N/A

Tested Design Flows

Design Entry Vivado Design Suite

Simulation For supported simulators, see the Xilinx Design Tools: Release Notes Guide.

Synthesis Vivado Synthesis

Support

All Vivado IP Change Logs Master Vivado IP Change Logs: 72775

Xilinx Support web page

Notes:1. For a complete list of supported devices, see the Vivado® IP catalog.2. The Embedded FIFO Generator core supports the UniSim simulation model.3. For the supported versions of the tools, see the Xilinx Design Tools: Release Notes Guide.



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Chapter 2

Overview

Navigating Content by Design ProcessXilinx® documentation is organized around a set of standard design processes to help you findrelevant content for your current development task. This document covers the following designprocesses:

• Hardware, IP, and Platform Development: Creating the PL IP blocks for the hardwareplatform, creating PL kernels, subsystem functional simulation, and evaluating the Vivado®timing, resource use, and power closure. Also involves developing the hardware platform forsystem integration. Topics in this document that apply to this design process include:

• Clocking

• Resets

• Customizing and Generating the Native Core

Core OverviewThe Embedded FIFO Generator core is a fully verified first-in first-out memory queue for use inany application requiring ordered storage and retrieval, enabling high-performance and area-optimized designs. The core provides an optimized solution for all FIFO configurations anddelivers maximum performance (up to 500 MHz) while using minimum resources.

This core supports Native interface FIFOs, AXI Memory Mapped interface FIFOs and AXI4-Stream interface FIFOs. AXI Memory Mapped and AXI4-Stream interface FIFOs are derived fromthe Native interface FIFO. Two AXI Memory Mapped interface styles are available: AXI4 andAXI4-Lite.

This core can be customized using the Vivado® IP customizers in the IP catalog as a completesolution with control logic already implemented, including management of the read and writepointers and the generation of status flags.

Note: The Memory Mapped interface FIFO and AXI4-Stream interface FIFO are referred to as AXI FIFOthroughout this document.

Chapter 2: Overview



Native Interface FIFOsThe Native interface FIFO can be customized to utilize block RAM, UltraRAM, and DistributedRAM resources available in some FPGA families to create high-performance, area-optimizedFPGA designs. Standard mode and First Word Fall Through are the two operating modesavailable for Native interface FIFOs.

Figure 1: Native Interface FIFO Signals

dout[m:0]

empty

rd_en

Write Clock Domain

Read Clock Domain

full

wr_en

din[n:0]

almost_full

prog_full

almost_empty

prog_empty

data_validunderflow

rd_data_count[q:0]

sbiterr

dbiterr

wr_ackoverflow

wr_data_count[p:0]

injectsbiterr

injectdbiterr

rst

OPTIONALMANDATORY

OPTIONAL SIDEBAND

wr_clk rd_clk

Read AgentWrite Agent

X21794-111318

AXI Interface FIFOsAXI interface FIFOs are derived from the Native interface FIFO, as shown in the following figure.Three AXI interface styles are available: AXI4-Stream, AXI4, and AXI4-Lite. In addition toapplications supported by the Native interface FIFO, AXI FIFOs can also be used in AXI SystemBus and Point-to-Point high speed applications.

Chapter 2: Overview



Use the AXI FIFOs in the same applications supported by the Native Interface FIFO when youneed to connect to other AXI functions. AXI FIFOs can be integrated into a system by using theIP integrator. See the Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator(UG994) for more details.

Figure 2: AXI FIFO Derivation

fullrd_en

rd_clk

emptywr_en

wr_clk

rst

din[n:0] dout[n:0]

*VALID

*ready

*data

*strobe

*last

*user

*id

---

*valid

*ready

*data

*strobe

*last

*user

*id

---

s_aclk

s_aresetn

m_aclk

AXI4 SLAVE AXI4 MASTER

WRITE CLOCKDOMAIN

READ CLOCKDOMAIN

wr_data_count[P:0]

injectsbiterr

prog_full

injectdbiterr

rd_data_count[Q:0]

sbiterr

prog_empty

dbiterr

Mandatory

Optional Sideband

AXI4 MASTER AXI4 SLAVE

*valid

X21791-111318

The AXI interface protocol uses a two-way valid and ready handshake mechanism. Theinformation source uses the valid signal to show when valid data or control information isavailable on the channel. The information destination uses the ready signal to show when it canaccept the data. The following figures show an example timing diagram for write and readoperations to the AXI4-Stream FIFO, and an example timing diagram for write and readoperations to the AXI memory mapped interface FIFO.

Chapter 2: Overview


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Figure 3: AXI4-Stream FIFO Timing

s_axis_tready

s_aclk

s_axis_tvalid

m_axis_tvalid

m_axis_tready

D0information D1

D0information D1

Information--> s/m_axs_tdata/tid/tstrb/tkeep/tkeep/tdest/tlast/tuserX21891-111218

Figure 4: AXI Memory Mapped Interface FIFO Timing

s_axi_*ready

s_aclk

s_axi_*valid

m_axi_*valid

m_axi_*ready

D0information D1

D0information D1

*valid --> awvalid/wvalid/bvalid/arvalid/rvalid*ready --> awready/wready/bready/arready/rreadyInformation --> s/m_axi_aw/wb/ar/r channel signals except valid and ready

X21890-111218

The information source generates the valid signal to indicate when the data is available. Thedestination generates the ready signal to indicate that it can accept the data, and transferoccurs only when both the valid and ready signals are High.

Because AXI FIFOs are derived from Native interface FIFOs, much of the behavior is commonbetween them. The ready signal is generated based on availability of space in the FIFO and isheld high to allow writes to the FIFO. The ready signal is pulled Low only when there is nospace in the FIFO left to perform additional writes. The valid signal is generated based onavailability of data in the FIFO and is held High to allow reads to be performed from the FIFO.The valid signal is pulled Low only when there is no data available to be read from the FIFO.The information signals are mapped to the din and dout bus of Native interface FIFOs. Thewidth of the AXI FIFO is determined by concatenating all of the information signals of theAXI interface. The information signals include all AXI signals except for the valid and readyhandshake signals.

Chapter 2: Overview



AXI FIFOs operate only in First-Word Fall-Through mode. The First-Word Fall-Through (FWFT)feature provides the ability to look ahead to the next word available from the FIFO withoutissuing a read operation. When data is available in the FIFO, the first word falls through the FIFOand appears automatically on the output data bus.

Native FIFO Feature OverviewClock Implementation and Operation

The Embedded FIFO Generator core enables FIFOs to be configured with either independent orcommon clock domains for write and read operations. The independent clock configuration ofthe Embedded FIFO Generator core enables you to implement unique clock domains on thewrite and read ports. The Embedded FIFO Generator core handles the synchronization betweenclock domains, placing no requirements on phase and frequency. When data buffering in a singleclock domain is required, the Embedded FIFO Generator core can be used to generate a coreoptimized for that single clock.

First-Word Fall-Through (FWFT)

The first-word fall-through (FWFT) feature provides the ability to look-ahead to the next wordavailable from the FIFO without issuing a read operation. When data is available in the FIFO, thefirst word falls through the FIFO and appears automatically on the output bus (dout). FWFT isuseful in applications that require Low-latency access to data and to applications that requirethrottling based on the contents of the read data. FWFT support is included in FIFOs createdwith block RAM, Distributed RAM, or UltraRAM.

See the FIFO Configurations table for FWFT availability. The use of this feature impacts thebehavior of many other features, such as:

• Read operations

• Programmable empty

• Data counts

Supported Memory Types

The Embedded FIFO Generator core implements FIFOs built from block RAM, Distributed RAM,or UltraRAM. The following table provides best-use recommendations for specific designrequirements.

Table 1: Memory Configuration Benefits

MemoryTypes

IndependentClocks

CommonClock

SmallBuffering

Medium - LargeBuffering

HighPerformance

MinimalResources

Block RAM ✓ ✓ ✓ ✓ ✓UltraRAM ✓ ✓ ✓ ✓

Chapter 2: Overview



Table 1: Memory Configuration Benefits (cont'd)

MemoryTypes

IndependentClocks

CommonClock

SmallBuffering

Medium - LargeBuffering

HighPerformance

MinimalResources

DistributedRAM

✓ ✓ ✓ ✓

Non-Symmetric Aspect Ratio Support

The core supports generating FIFOs with write and read ports of different widths, enablingautomatic width conversion of the data width. Non-symmetric aspect ratios ranging from 1:8 to8:1 are supported for the write and read port widths. This feature is available for the followingFIFO implementations:

• Common or Independent clock block RAM FIFOs

• Common clock UltraRAM FIFOs

Configurable Read Latency

The core supports configurable read latency, ranging from 1 to 16 for Standard Read ModeFIFOs. For FWFT FIFOs, the supported latency is 0.

Error Injection and Correction (ECC) Support

The block RAMs and UltraRAMs are equipped with built-in Error Injection and CorrectionChecking. This feature is available for Common/Independent Clock block RAM FIFOs andCommon Clock UltraRAM FIFOs.

Chapter 2: Overview



Native FIFO Configuration and ImplementationThe following table defines the supported memory and clock configurations.

Table 2: FIFO Configurations

ClockDomain Memory Type

Non-symmetricAspect Ratios

First-word Fall-Through ECC Support

ConfigurableRead Latency

SupportCommon Block RAM ✓ ✓ ✓ ✓Common Distributed RAM ✓ ✓Common UltraRAM ✓ ✓ ✓ ✓Independent Block RAM ✓ ✓ ✓ ✓Independent Distributed RAM ✓ ✓

Common Clock: Block RAM, Distributed RAM, UltraRAM

This implementation category allows you to select block RAM, Distributed RAM, or UltraRAMand supports a common clock for write and read data accesses. The feature set supported forthis configuration includes non-symmetric aspect ratios (different write and read port widths) forblock/UltraRAM FIFOs, status flags (full, almost full, empty, and almost empty), andprogrammable empty and full flags generated with user-defined thresholds.

In addition, optional handshaking and error flags are supported (write acknowledge, overflow,read valid, and underflow), and an optional data count provides the number of words in the FIFO.The block/UltraRAM FIFO configuration also supports ECC.

Independent Clocks: block RAM and Distributed RAM

This implementation option allows you to select block RAM or Distributed RAM and supportsindependent clock domains for write and read data accesses. Operations in the read domain aresynchronous to the read clock and operations in the write domain are synchronous to the writeclock.

The feature set supported for this type of FIFO includes non-symmetric aspect ratios (differentwrite and read port widths) for block RAM, status flags (full, almost full, empty, and almostempty), as well as programmable full and empty flags generated with user-defined thresholds.Optional read data count and write data count indicators provide the number of words in theFIFO relative to their respective clock domains. In addition, optional handshaking and error flagsare available (write acknowledge, overflow, read valid, and underflow). The block RAM FIFOconfiguration also supports ECC.

Chapter 2: Overview



Native Interface Feature SummaryThe following table summarizes the supported Embedded FIFO Generator core features for eachclock configuration and memory type.

Table 3: FIFO Configurations Summary

FIFO FeatureIndependent Clocks Common Clock

Block RAM DistributedRAM Block RAMDistributed

RAM UltraRAM

Non-symmetricAspect Ratios

✓ ✓ ✓

Symmetric AspectRatios

✓ ✓ ✓ ✓ ✓

Almost Full ✓ ✓ ✓ ✓ ✓Almost Empty ✓ ✓ ✓ ✓ ✓Handshaking ✓ ✓ ✓ ✓ ✓Data Count ✓ ✓ ✓ ✓ProgrammableEmpty/FullThresholds

✓ ✓ ✓ ✓ ✓

First-Word Fall-Through

✓ ✓ ✓ ✓ ✓

SynchronousReset

✓ ✓ ✓ ✓ ✓

dout Reset Value ✓ ✓ ✓ ✓ ✓ECC ✓ ✓ ✓Configurable ReadLatency

✓ ✓ ✓ ✓ ✓

Dynamic PowerSaving

✓

Native FIFO Interface SignalsThe following sections define the FIFO interface signals. The following figure illustrates thesesignals (both standard and optional ports) for a FIFO core that supports independent write andread clocks.

Chapter 2: Overview



Figure 5: FIFO with Independent Clocks: Interface Signals

dout[M:0]

empty

rst

rd_en

rd_clk

Write Clock Domain

Read Clock Domain

full

wr_en

din[n:0]

wr_clk

almost_empty

prog_empty

data_valid

underflow

almost_full

prog_full

wr_ack

overflow

X#####-110618X21839-110618

Note: Optional ports are represented in italics.

Interface Signals: FIFOs With Independent Clocks

The rst signal, as defined in the following table, causes a reset of the entire core logic (bothwrite and read clock domains. The initial hardware reset should be generated by the user.

Table 4: Reset and Sleep Signals for FIFOs with Independent Clocks

Name Direction Descriptionrst Input Reset: A synchronous reset signal that initializes all internal

pointers and output registers.

sleep Input Dynamic power gating. If sleep is active, the FIFO is in powersaving mode.Only available for UltraRAM FIFOs.

The following table defines the write interface signals for FIFOs with independent clocks. Thewrite interface signals are divided into required and optional signals and all signals aresynchronous to the write clock (wr_clk).

Chapter 2: Overview



Table 5: Write Interface Signals for FIFOs with Independent Clocks

Name Direction DescriptionRequired

wr_clk Input Write Clock: All signals on the write domain are synchronous tothis clock.

din[n:0] Input Data Input: The input data bus used when writing the FIFO.

wr_en Input Write Enable: If the FIFO is not full, asserting this signal causesdata (on din) to be written to the FIFO.

full Output Full Flag: When asserted, this signal indicates that the FIFO is full.Write requests are ignored when the FIFO is full, initiating a writewhen the FIFO is full is not destructive to the contents of the FIFO.

Optional

almost_full Output Almost Full: When asserted, this signal indicates that only onemore write can be performed before the FIFO is full.

prog_full Output Programmable Full: This signal is asserted when the number ofwords in the FIFO is greater than or equal to the assert threshold.It is deasserted when the number of words in the FIFO is lessthan the negate threshold.

wr_data_count [d:0] Output Write Data Count: This bus indicates the number of wordswritten into the FIFO. The count is guaranteed to never under-report the number of words in the FIFO, to ensure you neveroverflow the FIFO. The exception to this behavior is when a writeoperation occurs at the rising edge of wr_clk/clk, that writeoperation will only be reflected on wr_data_count at the secondrising clock edge. If D is less than log2(FIFO depth)-1, the bus istruncated by removing the least-significant bits.

wr_ack Output Write Acknowledge: This signal indicates that a write request(wr_en) during the prior clock cycle succeeded.

overflow Output Overflow: This signal indicates that a write request (wr_en)during the prior clock cycle was rejected, because the FIFO is full.Overflowing the FIFO is not destructive to the contents of theFIFO.

injectsbiterr Input Injects a single bit error if the ECC feature is used on block RAMsor UltraRAM FIFO macros.

injectdbiterr Input Injects a double bit error if the ECC feature is used on block RAMsor UltraRAM FIFO macros.

wr_rst_busy Output When asserted, this signal indicates that the write domain is inreset state.

The following table defines the read interface signals of a FIFO with independent clocks. Readinterface signals are divided into required signals and optional signals, and all signals aresynchronous to the read clock (rd_clk).

Table 6: Read Interface Signals for FIFOs with Independent Clocks


rd_clk Input Read Clock: All signals on the read domain are synchronous tothis clock.

dout[m:0] Output Data Output: The output data bus is driven when reading theFIFO.

Chapter 2: Overview



Table 6: Read Interface Signals for FIFOs with Independent Clocks (cont'd)

Name Direction Descriptionrd_en Input Read Enable: If the FIFO is not empty, asserting this signal causes

data to be read from the FIFO (output on dout).

empty Output Empty Flag: When asserted, this signal indicates that the FIFO isempty. Read requests are ignored when the FIFO is empty,initiating a read while empty is not destructive to the FIFO.

Optional

almost_empty Output Almost Empty Flag: When asserted, this signal indicates that theFIFO is almost empty and one word remains in the FIFO.

prog_empty Output Programmable Empty: This signal is asserted when the numberof words in the FIFO is less than or equal to the programmablethreshold. It is de-asserted when the number of words in the FIFOexceeds the programmable threshold.

rd_data_count [c:0] Output Read Data Count: This bus indicates the number of wordsavailable for reading in the FIFO. The count is guaranteed tonever over-report the number of words available for reading, toensure that you do not underflow the FIFO. The exception to thisbehavior is when the read operation occurs at the rising edge ofrd_clk/clk, that read operation is only reflected on rd_data_countat the second rising clock edge. If C is less than log2(FIFOdepth)-1, the bus is truncated by removing the least-significantbits.

data_valid Output Data Valid: This signal indicates that valid data is available on theoutput bus (dout).

underflow Output Underflow: Indicates that the read request (rd_en) during theprevious clock cycle was rejected because the FIFO is empty.Underflowing the FIFO is not destructive to the FIFO.

sbiterr Output Single Bit Error: Indicates that the ECC decoder detected andfixed a single-bit error on block RAM or UltraRAM FIFO macro.

dbiterr Output Double Bit Error: Indicates that the ECC decoder detected adouble-bit error on block RAM or UltraRAM FIFO macro and datain the FIFO core is corrupted.

rd_rst_busy Output When asserted, this signal indicates that the read domain is inreset state.

Interface Signals: FIFOs with Common Clock

The following table defines the interface signals of a FIFO with a common write and read clockand is divided into standard and optional interface signals. All signals are synchronous to thecommon clock (clk).

Table 7: Interface Signals for FIFOs with a Common Clock


rst Input Reset: A synchronous reset that initializes all internal pointersand output registers.

clk Input Clock: All signals on the write and read domains are synchronousto this clock.

din[n:0] Input Data Input: The input data bus used when writing the FIFO.

Chapter 2: Overview



Table 7: Interface Signals for FIFOs with a Common Clock (cont'd)

Name Direction Descriptionwr_en Input Write Enable: If the FIFO is not full, asserting this signal causes

data (on din) to be written to the FIFO.

full Output Full Flag: When asserted, this signal indicates that the FIFO is full.Write requests are ignored when the FIFO is full, initiating a writewhen the FIFO is full is not destructive to the contents of the FIFO.

dout[m:0] Output Data Output: The output data bus driven when reading the FIFO.

rd_en Input Read Enable: If the FIFO is not empty, asserting this signal causesdata to be read from the FIFO (output on dout).

empty Output Empty Flag: When asserted, this signal indicates that the FIFO isempty. Read requests are ignored when the FIFO is empty,initiating a read while empty is not destructive to the FIFO.

Optional

wr_data_count [c:0] Output Data Count: This bus indicates the number of words stored in theFIFO. If C is less than log2(FIFO depth)-1, the bus is truncated byremoving the least-significant bits.

almost_full Output Almost Full: When asserted, this signal indicates that only onemore write can be performed before the FIFO is full.

prog_full Output Programmable Full: This signal is asserted when the number ofwords in the FIFO is greater than or equal to the assert threshold.It is deasserted when the number of words in the FIFO is lessthan the negate threshold.

wr_ack Output Write Acknowledge: This signal indicates that a write request(wr_en) during the prior clock cycle succeeded.

overflow Output Overflow: This signal indicates that a write request (wr_en)during the prior clock cycle was rejected, because the FIFO is full.Overflowing the FIFO is not destructive to the FIFO.

almost_empty Output Almost Empty Flag: When asserted, this signal indicates that theFIFO is almost empty and one word remains in the FIFO.

prog_empty Output Programmable Empty: This signal is asserted after the numberof words in the FIFO is less than or equal to the programmablethreshold. It is de-asserted when the number of words in the FIFOexceeds the programmable threshold.

data_valid Output Data Valid: This signal indicates that valid data is available on theoutput bus (dout).

underflow Output Underflow: Indicates that read request (rd_en) during theprevious clock cycle was rejected because the FIFO is empty.Underflowing the FIFO is not destructive to the FIFO.

sbiterr Output Single Bit Error: Indicates that the ECC decoder detected andfixed a single-bit error.

dbiterr Output Double Bit Error: Indicates that the ECC decoder detected adouble-bit error and data in the FIFO core is corrupted.

injectsbiterr Input Injects a single bit error if the ECC feature is used. For detailedinformation.

injectdbiterr Input Injects a double bit error if the ECC feature is used. For detailedinformation.

sleep Input Dynamic shutdown power saving. If sleep is active, the FIFO is inpower saving mode.

wr_rst_busy Output When asserted, this signal indicates that the write domain is inreset state.

Chapter 2: Overview



Table 7: Interface Signals for FIFOs with a Common Clock (cont'd)

Name Direction Descriptionrd_rst_busy Output When asserted, this signal indicates that the read domain is in

reset state.

AXI FIFO Feature OverviewEasy Integration of Independent FIFOs for Read and Write Channels

For AXI memory mapped interfaces, AXI specifies Write Channels and Read Channels. WriteChannels include a Write Address Channel, Write Data Channel and Write Response Channel.Read Channels include a Read Address Channel and Read Data Channel. The Embedded FIFOGenerator core provides the ability to generate either Write Channels or Read Channels, or bothWrite Channels and Read Channels for AXI memory mapped. Three FIFOs are integrated forWrite Channels and two FIFOs are integrated for Read Channels. When both Write and ReadChannels are selected, the FIFO Generator core integrates five independent FIFOs.

For AXI memory mapped interfaces, the Embedded FIFO Generator core provides the ability toimplement independent FIFOs for each channel, as shown in the following figure. For eachchannel, the core can be independently configured to generate a block RAM or DistributedMemory or UltraRAM based FIFO. The depth of each FIFO can also be independentlyconfigured.

Chapter 2: Overview



Figure 6: AXI Memory Mapped FIFO Block Diagram

Write ClockDomain

Read ClockDomain

Write ClockDomain

Read ClockDomain

Write ClockDomain

Write ClockDomain

Read ClockDomain

Write ClockDomain

VALID

READY

CHANNEL INFO

VALIDREADY

CHANNEL INFO

VALIDREADY

CHANNEL INFO

VALID

READYCHANNEL INFO

VALID

READYCHANNEL INFO

VALID

READY

CHANNEL INFO

VALIDREADY

CHANNEL INFO

VALID

READYCHANNEL INFO

VALID

READYCHANNEL INFO

VALID

READY

CHANNEL INFO

Read ClockDomain

Read ClockDomain

S_ACLKS_ARESETN

Write Address Channel

Write Data Channel

Write Response

Channel

Read Address Channel

Read Response

Channel

Write Channels

Read Channels

Write Address Channel

Write Data Channel

Write Response Channel

Read Address Channel

Read Response Channel

Write Channels

Read Channels

M_ACLK

OptionalMandatoryX21800-110618

Clock and Reset Implementation and Operation

For the AXI4-Stream and AXI memory mapped interfaces, all instantiated FIFOs share clock andasynchronous active-Low reset signals. In addition, all instantiated FIFOs can support eitherindependent clock or common clock operation.

The independent clock configuration of the Embedded FIFO Generator core enables you toimplement unique clock domains on the write and read ports. The Embedded FIFO Generatorcore handles the synchronization between clock domains, placing no requirements on phase andfrequency. When data buffering in a single clock domain is required, the Embedded FIFOGenerator core can be used to generate a core optimized for a single clock by selecting thecommon clock option.

Chapter 2: Overview



Automatic FIFO Width Calculation

AXI FIFOs support symmetric widths for the FIFO Read and Write ports. The FIFO width for theAXI FIFO is determined by the selected interface type (AXI4-Stream or AXI memory mapped)and user-selected signals and signal widths within the given interface. The AXI FIFO width isthen calculated automatically by the aggregation of all signal widths in a respective channel.

Supported Configuration, Memory and Application Types

The Embedded FIFO Generator core implements FIFOs built from block RAM, UltraRAM, orDistributed RAM memory types. Depending on the application type selection (Data FIFO orPacket FIFO), the core combines memory primitives in an optimal configuration based on thecalculated width and selected depth of the FIFO.

Packet FIFO

The Packet FIFO configuration delays the start of packet (burst) transmission until the end (LASTbeat) of the packet is received. This ensures uninterrupted availability of data after master-sidetransfer begins, thus avoiding source-end stalling of the AXI data channel. This is valuable inapplications in which data originates at a master device. Examples of this include real-time signalchannels that operate at a lower data rate than the downstream AXI switch and/or slavedestination, such as a high-bandwidth memory.

The Packet FIFO principle applies to both AXI4 memory-mapped burst transactions (both writeand read) and AXI4-Stream packet transmissions. This feature is sometimes referred to as "store-and-forward", referring to the behavior for memory-mapped writes and stream transmissions. Formemory-mapped reads, transactions are delayed until there are enough vacancies in the FIFO toguarantee uninterrupted buffering of the entire read data packet, as predicted by the AR-channeltransaction. Read transactions do not actually rely on the RLAST signal.

The Packet FIFO feature is supported for Common Clock AXI4 and Common/Independent ClockAXI4-Stream configurations. It is not supported for AXI4-Lite configurations.

AXI4-Stream Packet FIFO

The Embedded FIFO Generator core uses AXI4-Stream Interface for the AXI4-Stream PacketFIFO feature. The Embedded FIFO Generator core indicates a tvalid on the AXI4-StreamMaster side when a complete packet (marked by tlast) is received on the AXI4-Stream Slaveside or when the AXI4-Stream FIFO is FULL. Indicating tvalid on the Master side due to theFIFO becoming full is an exceptional case, and in such case, the Packet FIFO acts as a normalFWFT FIFO forwarding the data received on the Slave side to the Master side until it receivestlast on the Slave side.

Chapter 2: Overview



AXI4 Packet FIFO

The Embedded FIFO Generator core uses the AXI memory mapped interface for the AXI4 PacketFIFO feature (for both write and read channels).

• Packet FIFO on Write Channels: The Embedded FIFO Generator core indicates an awvalidon the AXI AW channel Master side when a complete packet (marked by wlast) is receivedon the AXI W channel Slave side. The Write Channel Packet FIFO is coupled to the WriteAddress Channel so that AW transfers are not posted to the AXI Write Address Channel untilall of the data needed for the requested transfer is received on the AXI W channel Slave side.The minimum depth of the W channel is set to 512 and enables the Write Channel PacketFIFO to hold two packets of its maximum length.

• Packet FIFO on Read Channels: The Embedded FIFO Generator core indicates an rvalid onthe AXI R channel Slave side when a complete packet (marked by rlast) is received on theAXI R channel Master side. The Read Channel Packet FIFO is coupled to the Read AddressChannel so that AR transfers are not posted to the AXI Read Address Channel if there is notenough space left in the Packet FIFO for the associated data. The minimum depth of the Rchannel is set to 512, and enables the Read Channel Packet FIFO to hold two packets of itsmaximum length.

Error Injection and Correction (ECC) Support

The block RAM and UltraRAM macros are equipped with built-in Error Injection and CorrectionChecking. This feature is available for both the common clock block/UltraRAM FIFOs andindependent clock block RAM FIFOs.

AXI Slave Interface for Performing Writes

AXI FIFOs provide an AXI Slave interface for performing Writes. The AXI Master providesINFORMATION and VALID signals; the AXI FIFO accepts the INFORMATION by asserting theREADY signal. The READY signal is de-asserted only when the FIFO is full.

AXI Master Interface for Performing Reads

The AXI FIFO provides an AXI Master interface for performing Reads. The AXI FIFO providesINFORMATION and VALID signals; upon detecting a READY signal asserted from the AXI Slaveinterface, the AXI FIFO places the next INFORMATION on the bus. The VALID signal is de-asserted only when the FIFO is empty.

AXI FIFO Feature SummaryThe following table summarizes the supported Embedded FIFO Generator core features for eachclock configuration and memory type.

Chapter 2: Overview



Table 8: AXI FIFO Configuration Summary

FIFO OptionsCommon Clock Independent Clock

Block RAM/UltraRAM

DistributedMemory Block RAM

DistributedMemory

Full1 ✓ ✓ ✓ ✓Programmable Full2 ✓ ✓ ✓ ✓Empty ✓ ✓ ✓ ✓Programmable Empty2 ✓ ✓ ✓ ✓Data Counts ✓ ✓ ✓ ✓ECC ✓ ✓Notes:1. Mapped to s_axis_tready/s_axi_awready/s_axi_wready/m_axi_bready/s_axi_arready/m_axi_rready depending on the

Handshake Flag Options in the IDE.2. Mapped to m_axis_tvalid/m_axi_awvalid/m_axi_wvalid/s_axi_bvalid/m_axi_arvalid/s_axi_rvalid depending on the

Handshake Flag Options in the IDE.Provided as sideband signal depending on the IDE option.Mapped tos_axis_tready/s_axi_awready/s_axi_wready/m_axi_bready/s_axi_arready/m_axi_rready depending on the HandshakeFlag Options in the IDE.

AXI FIFO Interface SignalsThe following sections define the AXI FIFO interface signals.

The value of s_axis_tready, s_axi_awready, s_axi_wready, m_axi_bready,s_axi_arready and m_axi_rready is 1 outside Reset Window. To avoid unexpectedbehavior, do not perform any transactions during Reset Window.

Note: Reset Window: reset duration + 60 slowest clock cycles.

Global Signals

The following table defines the global interface signals for AXI FIFO.

The s_aresetn signal causes a reset of the entire core logic. It is an active-Low, asynchronousinput synchronized internally in the core before use. The initial hardware reset should begenerated by the user.

Table 9: AXI FIFO - Global Interface Signals

Name Direction DescriptionGlobal Clock and Reset Signals Mapped to FIFO Clock and Reset Inputs

m_aclk Input Global Master Interface Clock: All signals on Master Interface ofAXI FIFO are synchronous to m_aclk

s_aclk Input Global Slave Interface Clock: All signals are sampled on therising edge of this clock.

s_aresetn Input Global Reset: This signal is active-Low.

Chapter 2: Overview



AXI4-Stream FIFO Interface Signals

The following table defines the AXI4-Stream FIFO interface signals.

Table 10: AXI4-Stream FIFO Interface Signals

Name Direction DescriptionAXI4-Stream Interface: Handshake Signals for FIFO Write Interface

s_axis_tvalid Input TVALID: Indicates that the master is driving a valid transfer. Atransfer takes place when both TVALID and TREADY are asserted.

s_axis_tready Output TREADY: Indicates that the slave can accept a transfer in thecurrent cycle.

AXI4-Stream Interface: Information Signals Mapped to FIFO Data Input (din) Bus

s_axis_tdata[m-1:0] Input TDATA: The primary payload that is used to provide the data thatis passing across the interface. The width of the data payload isan integer number of bytes.

s_axis_tstrb[m/8-1:0] Input TSTRB: The byte qualifier that indicates whether the content ofthe associated byte of TDATA is processed as a data byte or aposition byte. For a 64-bit DATA, bit 0 corresponds to the leastsignificant byte on DATA, and bit 7 corresponds to the mostsignificant byte. For example:

• STROBE[0] = 1b, DATA[7:0] is valid• STROBE[7] = 0b, DATA[63:56] is not valid

s_axis_tkeep[m/8-1:0] Input TKEEP: The byte qualifier that indicates whether the content ofthe associated byte of TDATA is processed as part of the datastream. Associated bytes that have the TKEEP byte qualifierdeasserted are null bytes and can be removed from the datastream. For a 64-bit DATA, bit 0 corresponds to the leastsignificant byte on DATA, and bit 7 corresponds to the mostsignificant byte. For example:

• KEEP[0] = 0b, DATA[7:0] is a NULL byte• KEEP [7] = 1b, DATA[63:56] is not a NULL byte

s_axis_tlast Input TLAST: Indicates the boundary of a packet.

s_axis_tid[m:0] Input TID: The data stream identifier that indicates different streams ofdata.

s_axis_tdest[m:0] Input TDEST: Provides routing information for the data stream.

s_axis_tuser[m:0] Input TUSER: The user-defined sideband information that can betransmitted alongside the data stream.

AXI4-Stream Interface: Handshake Signals for FIFO Read Interface

m_axis_tvalid Output TVALID: Indicates that the master is driving a valid transfer. Atransfer takes place when both tvalid and tready are asserted.

m_axis_tready Input TREADY: Indicates that the slave can accept a transfer in thecurrent cycle.

AXI4-Stream Interface: Information Signals Derived from FIFO Data Output (dout) Bus

m_axis_tdata[m-1:0] Output TDATA: The primary payload that is used to provide the data thatis passing across the interface. The width of the data payload isan integer number of bytes.

Chapter 2: Overview



Table 10: AXI4-Stream FIFO Interface Signals (cont'd)

Name Direction Descriptionm_axis_tstrb[m/8-1:0] Output TSTRB: The byte qualifier that indicates whether the content of

the associated byte of TDATA is processed as a data byte or aposition byte. For a 64-bit DATA, bit 0 corresponds to the leastsignificant byte on DATA, and bit 7 corresponds to the mostsignificant byte. For example:


m_axis_tkeep[m/8-1:0] Output TKEEP: The byte qualifier that indicates whether the content ofthe associated byte of TDATA is processed as part of the datastream. Associated bytes that have the TKEEP byte qualifierdeasserted are null bytes and can be removed from the datastream. For a 64-bit DATA, bit 0 corresponds to the leastsignificant byte on DATA, and bit 7 corresponds to the mostsignificant byte. For example:

• KEEP[0] = 1b, DATA[7:0] is a NULL byte• KEEP [7] = 0b, DATA[63:56] is not a NULL byte

m_axis_tlast Output TLAST: Indicates the boundary of a packet.

m_axis_tid[m:0] Output TID: The data stream identifier that indicates different streams ofdata.

m_axis_tdest[m:0] Output TDEST: Provides routing information for the data stream.

m_axis_tuser[m:0] Output TUSER: The user-defined sideband information that can betransmitted alongside the data stream.

AXI4-Stream FIFO: Optional Sideband Signals

injectsbiterr_axis Input Inject Single-Bit Error: Injects a single-bit error if the ECC featureis used.

injectdbiterr_axis Input Inject Double-Bit Error: Injects a double-bit error if the ECCfeature is used.

sbiterr_axis Output Single-Bit Error: Indicates that the ECC decoder detected andfixed a single-bit error.

dbiterr_axis Output Double-Bit Error: Indicates that the ECC decoder detected adouble-bit error and data in the FIFO core is corrupted.

wr_data_count_axis[d:0] Output Write Data Count: This bus indicates the number of wordswritten into the FIFO. The count is guaranteed to neverunderreport the number of words in the FIFO, to ensure younever overflow the FIFO. The exception to this behavior is when awrite operation occurs at the rising edge of write clock; that writeoperation will only be reflected on wr_data_count at the secondrising clock edge.

• D= log2(FIFO depth)+1

Chapter 2: Overview



Table 10: AXI4-Stream FIFO Interface Signals (cont'd)

Name Direction Descriptionrd_data_count_axis[d:0] Output Read Data Count: This bus indicates the number of words

available for reading in the FIFO. The count is guaranteed tonever over-report the number of words available for reading, toensure that you do not underflow the FIFO. The exception to thisbehavior is when the read operation occurs at the rising edge ofread clock; that read operation is only reflected on rd_data_countat the second rising clock edge.

• D = log2(FIFO depth)+1

prog_full_axis Output Programmable Full: This signal is asserted when the number ofwords in the FIFO is greater than or equal to the programmablethreshold. It is deasserted when the number of words in the FIFOis less than the programmable threshold.

prog_empty_axis Output Programmable Empty: This signal is asserted when the numberof words in the FIFO is less than or equal to the programmablethreshold. It is deasserted when the number of words in the FIFOexceeds the programmable threshold.

AXI4 FIFO Interface Signals

Write Channels

The following table defines the AXI4 FIFO interface signals for the Write Address Channel.

Table 11: AXI4 Write Address Channel FIFO Interface Signals

Name Direction DescriptionAXI4 Interface Write Address Channel: Information Signals Mapped to FIFO Data Input (din) Bus

s_axi_awid[m:0] Input Write Address ID: Identification tag for the write address groupof signals.

s_axi_awaddr[m:0] Input Write Address: The write address bus gives the address of thefirst transfer in a write burst transaction. The associated controlsignals are used to determine the addresses of the remainingtransfers in the burst.

s_axi_awlen[7:0] Input Burst Length: The burst length gives the exact number oftransfers in a burst. This information determines the number ofdata transfers associated with the address.

s_axi_awsize[2:0] Input Burst Size: Indicates the size of each transfer in the burst. Bytelane strobes indicate exactly which byte lanes to update.

s_axi_awburst[1:0] Input Burst Type: The burst type, coupled with the size information,details how the address for each transfer within the burst iscalculated.

s_axi_awlock[1:0] Input Lock Type: This signal provides additional information about theatomic characteristics of the transfer.

s_axi_awcache[3:0] Input Cache Type: Indicates the bufferable, cacheable, write-through,write-back, and allocate attributes of the transaction.

s_axi_awprot[2:0] Input Protection Type: Indicates the normal, privileged, or secureprotection level of the transaction and whether the transaction isa data access or an instruction access.

Chapter 2: Overview



Table 11: AXI4 Write Address Channel FIFO Interface Signals (cont'd)

Name Direction Descriptions_axi_awqos[3:0] Input Quality of Service (QoS): Sent on the write address channel for

each write transaction.

s_axi_awregion[3:0] Input Region Identifier: Sent on the write address channel for eachwrite transaction.

s_axi_awuser[m:0] Input Write Address Channel User

AXI4 Interface Write Address Channel: Handshake Signals for FIFO Write Interface

s_axi_awvalid Input Write Address Valid: Indicates that valid write address andcontrol information are available:

• 1 = Address and control information available.• 0 = Address and control information not available.• The address and control information remain stable until the

address acknowledge signal, awready, goes High.

s_axi_awready Output Write Address Ready: Indicates that the slave is ready to acceptan address and associated control signals:

• 1 = Slave ready.• 0 = Slave not ready.

AXI4 Interface Write Address Channel: Information Signals Derived from FIFO Data Output (dout) Bus

m_axi_awid[m:0] Output Write Address ID: This signal is the identification tag for thewrite address group of signals.

m_axi_awaddr[m:0] Output Write Address: The write address bus gives the address of thefirst transfer in a write burst transaction. The associated controlsignals are used to determine the addresses of the remainingtransfers in the burst.

m_axi_awlen[7:0] Output Burst Length: The burst length gives the exact number oftransfers in a burst. This information determines the number ofdata transfers associated with the address.

m_axi_awsize[2:0] Output Burst Size: This signal indicates the size of each transfer in theburst. Byte lane strobes indicate exactly which byte lanes toupdate.

m_axi_awburst[1:0] Output Burst Type: The burst type, coupled with the size information,details how the address for each transfer within the burst iscalculated.

m_axi_awlock[1:0] Output Lock Type: This signal provides additional information about theatomic characteristics of the transfer.

m_axi_awcache[3:0] Output Cache Type: This signal indicates the bufferable, cacheable,write-through, write-back, and allocate attributes of thetransaction.

m_axi_awprot[2:0] Output Protection Type: This signal indicates the normal, privileged, orsecure protection level of the transaction and whether thetransaction is a data access or an instruction access.

m_axi_awqos[3:0] Output Quality of Service (QoS): Sent on the write address channel foreach write transaction.

m_axi_awregion[3:0] Output Region Identifier: Sent on the write address channel for eachwrite transaction.

m_axi_awuser[m:0] Output Write Address Channel User

Chapter 2: Overview



Table 11: AXI4 Write Address Channel FIFO Interface Signals (cont'd)

Name Direction DescriptionAXI4 Interface Write Address Channel: Handshake Signals for FIFO Read Interface

m_axi_awvalid Output Write Address Valid: Indicates that valid write address andcontrol information are available:

• 1 = address and control information available• 0 = address and control information not available• The address and control information remain stable until the

address acknowledge signal, AWREADY, goes high.

m_axi_awready Input Write Address Ready: Indicates that the slave is ready to acceptan address and associated control signals:

• 1 = Slave ready• 0 = Slave not ready

The following table defines the AXI4 FIFO interface signals for the Write Data Channel.

Table 12: AXI4 Write Data Channel FIFO Interface Signals

Name Direction DescriptionAXI4 Interface Write Data Channel: Information Signals mapped to FIFO Data Input (din) Bus

s_axi_wdata[m-1:0] Input Write Data: The write data bus can be 8, 16, 32, 64, 128, 256 or512 bits wide.

s_axi_wstrb[m/8-1:0] Input Write Strobes: Indicates which byte lanes to update in memory.There is one write strobe for each eight bits of the write data bus.Therefore, WSTRB[n] corresponds to WDATA[(8 × n) + 7:(8 × n)].For a 64-bit DATA, bit 0 corresponds to the least significant byteon DATA, and bit 7 corresponds to the most significant byte. Forexample:


s_axi_wlast Input Write Last: Indicates the last transfer in a write burst.

s_axi_wuser[m:0] Input Write Data Channel User

AXI4 Interface Write Data Channel: Handshake Signals for FIFO Write Interface

s_axi_wvalid Input Write Valid: Indicates that valid write data and strobes areavailable:

• 1 = Write data and strobes available.• 0 = Write data and strobes not available.

s_axi_wready Output Write Ready: Indicates that the slave can accept the write data:


Chapter 2: Overview



Table 12: AXI4 Write Data Channel FIFO Interface Signals (cont'd)

Name Direction DescriptionAXI4 Interface Write Data Channel: Information Signals Derived from FIFO Data Output (dout) Bus

m_axi_wdata[m-1:0] Output Write Data: The write data bus can be 8, 16, 32, 64, 128, 256 or512 bits wide.

m_axi_wstrb[m/8-1:0] Output Write Strobes: Indicates which byte lanes to update in memory.There is one write strobe for each eight bits of the write data bus.Therefore, WSTRB[n] corresponds to WDATA[(8 × n) + 7:(8 × n)].For a 64-bit DATA, bit 0 corresponds to the least significant byteon DATA, and bit 7 corresponds to the most significant byte. Forexample:


m_axi_wlast Output Write Last: Indicates the last transfer in a write burst.

m_axi_wuser[m:0] Output Write Data Channel User

AXI4 Interface Write Data Channel: Handshake Signals for FIFO Read Interface

m_axi_wvalid Output Write valid: Indicates that valid write data and strobes areavailable:

• 1 = Write data and strobes available• 0 = Write data and strobes not available

m_axi_wready Input Write ready: Indicates that the slave can accept the write data:


AXI4 Write Data Channel FIFO: Optional Sideband Signals

injectsbiterr_wdch Input Inject Single-Bit Error: Injects a single bit error if the ECC featureis used.

injectdbiterr_wdch Input Inject Double-Bit Error: Injects a double bit error if the ECCfeature is used.

sbiterr_wdch Output Single-Bit Error: Indicates that the ECC decoder detected andfixed a single-bit error.

dbiterr_wdch Output Double-Bit Error: Indicates that the ECC decoder detected adouble-bit error and data in the FIFO core is corrupted.

wr_data_count_wdch[d:0] Output Write Data Count: This bus indicates the number of wordswritten into the FIFO. The count is guaranteed to neverunderreport the number of words in the FIFO, to ensure younever overflow the FIFO. The exception to this behavior is when awrite operation occurs at the rising edge of write clock, that writeoperation will only be reflected on wr_data_count at the nextrising clock edge. D = log2(FIFO depth)+1

rd_data_count_wdch[d:0] Output Read Data Count: This bus indicates the number of wordsavailable for reading in the FIFO. The count is guaranteed tonever over-report the number of words available for reading, toensure that you do not underflow the FIFO. The exception to thisbehavior is when the read operation occurs at the rising edge ofread clock, that read operation is only reflected on rd_data_countat the next rising clock edge. D = log2(FIFO depth)+1

Chapter 2: Overview



Table 12: AXI4 Write Data Channel FIFO Interface Signals (cont'd)

Name Direction Descriptionprog_full_wdch Output Programmable Full: This signal is asserted when the number of

words in the FIFO is greater than or equal to the programmablethreshold. It is deasserted when the number of words in the FIFOis less than the programmable threshold.

prog_empty_wdch Output Programmable Empty: This signal is asserted when the numberof words in the FIFO is less than or equal to the programmablethreshold. It is deasserted when the number of words in the FIFOexceeds the programmable threshold.

The following table defines the AXI4 FIFO interface signals for the Write Response Channel.

Table 13: AXI4 Write Response Channel FIFO Interface Signals

Name Direction DescriptionAXI4 Interface Write Response Channel: Information Signals Mapped to FIFO Data Output (dout) Bus

s_axi_bid[m:0] Output Response ID: The identification tag of the write response. TheBID value must match the AWID value of the write transaction towhich the slave is responding.

s_axi_bresp[1:0] Output Write Response: Indicates the status of the write transaction.The allowable responses are OKAY, EXOKAY, SLVERR, and DECERR.

s_axi_buser[m:0] Output Write Response Channel User

AXI4 Interface Write Response Channel: Handshake Signals for FIFO Read Interface

s_axi_bvalid Output Write Response Valid: Indicates that a valid write response isavailable:

• 1 = Write response available.• 0 = Write response not available.

s_axi_bready Input Response Ready: Indicates that the master can accept theresponse information.

• 1 = Master ready.• 0 = Master not ready.

AXI4 Interface Write Response Channel: Information Signals Derived from FIFO Data Input (din) Bus

m_axi_bid[m:0] Input Response ID: The identification tag of the write response. TheBID value must match the AWID value of the write transaction towhich the slave is responding.

m_axi_bresp[1:0] Input Write Response: Indicates the status of the write transaction.The allowable responses are OKAY, EXOKAY, SLVERR, and DECERR.

m_axi_buser[m:0] Input Write Response Channel User

AXI4 Interface Write Response Channel: Handshake Signals for FIFO Write Interface

m_axi_bvalid Input Write Response Valid: Indicates that a valid write response isavailable:


Chapter 2: Overview



Table 13: AXI4 Write Response Channel FIFO Interface Signals (cont'd)

Name Direction Descriptionm_axi_bready Output Response Ready: Indicates that the master can accept the

response information.


Read Channels

The following table defines the AXI4 FIFO interface signals for the Read Address Channel.

Table 14: AXI4 Read Address Channel FIFO Interface Signals

Name Direction DescriptionAXI4 Interface Read Address Channel: Information Signals Mapped to FIFO Data Input (din) Bus

s_axi_arid[m:0] Input Read Address ID: This signal is the identification tag for the readaddress group of signals.

s_axi_araddr[m:0] Input Read Address: The read address bus gives the initial address of aread burst transaction. Only the start address of the burst isprovided and the control signals that are issued alongside theaddress detail how the address is calculated for the remainingtransfers in the burst.

s_axi_arlen[7:0] Input Burst Length: The burst length gives the exact number oftransfers in a burst. This information determines the number ofdata transfers associated with the address.

s_axi_arsize[2:0] Input Burst Size: This signal indicates the size of each transfer in theburst.

s_axi_arburst[1:0] Input Burst Type: The burst type, coupled with the size information,details how the address for each transfer within the burst iscalculated.

s_axi_arlock[1:0] Input Lock Type: This signal provides additional information about theatomic characteristics of the transfer.

s_axi_arcache[3:0] Input Cache Type: This signal provides additional information aboutthe cacheable characteristics of the transfer.

s_axi_arprot[2:0] Input Protection Type: This signal provides protection unit informationfor the transaction.

s_axi_arqos[3:0] Input Quality of Service (QoS): Sent on the read address channel foreach read transaction.

s_axi_arregion[3:0] Input Region Identifier: Sent on the read address channel for eachread transaction.

s_axi_aruser[m:0] Input Read Address Channel User

AXI4 Interface Read Address Channel: Handshake Signals for FIFO Write Interface

s_axi_arvalid Input Read Address Valid: When high, indicates that the read addressand control information is valid and will remain stable until theaddress acknowledge signal, arready, is high.

• 1 = Address and control information valid.• 0 = Address and control information not valid.

Chapter 2: Overview



Table 14: AXI4 Read Address Channel FIFO Interface Signals (cont'd)

Name Direction Descriptions_axi_arready Output Read Address Ready: Indicates that the slave is ready to accept

an address and associated control signals:


AXI4 Interface Read Address Channel: Information Signals Derived from FIFO Data Output (dout) Bus

m_axi_arid[m:0] Output Read Address ID: This signal is the identification tag for the readaddress group of signals.

m_axi_araddr[m:0] Output Read Address: The read address bus gives the initial address of aread burst transaction. Only the start address of the burst isprovided and the control signals that are issued alongside theaddress detail how the address is calculated for the remainingtransfers in the burst.

m_axi_arlen[7:0] Output Burst Length: The burst length gives the exact number oftransfers in a burst. This information determines the number ofdata transfers associated with the address.

m_axi_arsize[2:0] Output Burst Size: This signal indicates the size of each transfer in theburst.

m_axi_arburst[1:0] Output Burst Type: The burst type, coupled with the size information,details how the address for each transfer within the burst iscalculated.

m_axi_arlock[1:0] Output Lock Type: This signal provides additional information about theatomic characteristics of the transfer.

m_axi_arcache[3:0] Output Cache Type: This signal provides additional information aboutthe cacheable characteristics of the transfer.

m_axi_arprot[2:0] Output Protection Type: This signal provides protection unit informationfor the transaction.

m_axi_arqos[3:0] Output Quality of Service (QoS) signaling, sent on the read addresschannel for each read transaction.

m_axi_arregion[3:0] Output Region Identifier: Sent on the read address channel for eachread transaction.

m_axi_aruser[m:0] Output Read Address Channel User

AXI4 Interface Read Address Channel: Handshake Signals for FIFO Read Interface

m_axi_arvalid Output Read Address Valid: Indicates, when HIGH, that the read addressand control information is valid and will remain stable until theaddress acknowledge signal, arready, is high.

• 1 = Address and control information valid.• 0 = Address and control information not valid.

m_axi_arready Input Read Address Ready: Indicates that the slave is ready to acceptan address and associated control signals:


The following table defines the AXI4 FIFO interface signals for the Read Data Channel.

Chapter 2: Overview



Table 15: AXI4 Read Data Channel FIFO Interface Signals

Name Direction DescriptionAXI4 Interface Read Data Channel: Information Signals Mapped to FIFO Data Output (dout) Bus

s_axi_rid[m:0] Output Read ID Tag: ID tag of the read data group of signals. The RIDvalue is generated by the slave and must match the ARID value ofthe read transaction to which it is responding.

s_axi_rdata[m-1:0] Output Read Data: Can be 8, 16, 32, 64, 128, 256 or 512 bits wide.

s_axi_rresp[1:0] Output Read Response: Indicates the status of the read transfer. Theallowable responses are OKAY, EXOKAY, SLVERR, and DECERR.

s_axi_rlast Output Read Last: Indicates the last transfer in a read burst.

s_axi_ruser[m:0] Output Read Data Channel User

AXI4 Interface Read Data Channel: Handshake Signals for FIFO Read Interface

s_axi_rvalid Output Read Valid: Indicates that the required read data is available andthe read transfer can complete:

• 1 = Read data available.• 0 = Read data not available.

s_axi_rready Input Read Ready: Indicates that the master can accept the read dataand response information:

• 1= Master ready.• 0 = Master not ready.

AXI4 Interface Read Data Channel: Information Signals Derived from FIFO Data Input (din) Bus

m_axi_rid[m:0] Input Read ID Tag: ID tag of the read data group of signals. The RIDvalue is generated by the slave and must match the ARID value ofthe read transaction to which it is responding.

m_axi_rdata[m-1:0] Input Read Data: Can be 8, 16, 32, 64, 128, 256 or 512 bits wide.

m_axi_ rresp[1:0] Input Read Response: Indicates the status of the read transfer. Theallowable responses are OKAY, EXOKAY, SLVERR, and DECERR.

m_axi_rlast Input Read Last: Indicates the last transfer in a read burst.

m_axi_ruser[m:0] Input Read Data Channel User

AXI4 Interface Read Data Channel: Handshake Signals for FIFO Write Interface

m_axi_rvalid Input Read Valid: Indicates that the required read data is available andthe read transfer can complete:

• 1 = Read data available.• 0 = Read data not available.

m_axi_rready Output Read Ready: Indicates that the master can accept the read dataand response information:

• 1= Master ready.• 0 = Master not ready.

AXI4 Read Data Channel FIFO: Optional Sideband Signals

injectsbiterr_rdch Input Injects a single bit error if the ECC feature is used.

injectdbiterr_rdch Input Injects a double bit error if the ECC feature is used.

Chapter 2: Overview



Table 15: AXI4 Read Data Channel FIFO Interface Signals (cont'd)

Name Direction Descriptionsbiterr_rdch Output Single Bit Error: Indicates that the ECC decoder detected and

fixed a single-bit error.

dbiterr_rdch Output Double Bit Error: Indicates that the ECC decoder detected adouble-bit error and data in the FIFO core is corrupted.

wr_data_count_rdch[d:0] Output Write Data Count: This bus indicates the number of wordswritten into the FIFO. The count is guaranteed to neverunderreport the number of words in the FIFO, to ensure younever overflow the FIFO. The exception to this behavior is when awrite operation occurs at the rising edge of write clock, that writeoperation will only be reflected on wr_data_count at the nextrising clock edge. D = log2(FIFO depth)+1

rd_data_count_rdch[d:0] Output Read Data Count: This bus indicates the number of wordsavailable for reading in the FIFO. The count is guaranteed tonever over-report the number of words available for reading, toensure that you do not underflow the FIFO. The exception to thisbehavior is when the read operation occurs at the rising edge ofread clock, that read operation is only reflected on rd_data_countat the next rising clock edge. D = log2(FIFO depth)+1

prog_full_rdch Output Programmable Full: This signal is asserted when the number ofwords in the FIFO is greater than or equal to the programmablethreshold. It is deasserted when the number of words in the FIFOis less than the programmable threshold.

prog_empty_rdch Output Programmable Empty: This signal is asserted when the numberof words in the FIFO is less than or equal to the programmablethreshold. It is deasserted when the number of words in the FIFOexceeds the programmable threshold.

AXI4-Lite FIFO Interface Signals

Write Channels

The following table defines the AXI4-Lite FIFO interface signals for the Write Address Channel.

Table 16: AXI4-Lite Write Address Channel FIFO Interface Signals

Name Direction DescriptionAXI4-Lite Interface Write Address Channel: Information Signals Mapped to FIFO Data Input (din) Bus

s_axi_awaddr[m:0] Input Write Address: Gives the address of the first transfer in a writeburst transaction. The associated control signals are used todetermine the addresses of the remaining transfers in the burst.

s_axi_awprot[3:0] Input Protection Type: Indicates the normal, privileged, or secureprotection level of the transaction and whether the transaction isa data access or an instruction access.

AXI4-Lite Interface Write Address Channel: Handshake Signals for FIFO Write Interface

s_axi_awvalid Input Write Address Valid: Indicates that valid write address andcontrol information are available:

• 1 = Address and control information available.• 0 = Address and control information not available.The address and control information remain stable until theaddress acknowledge signal, AWREADY, goes high.

Chapter 2: Overview



Table 16: AXI4-Lite Write Address Channel FIFO Interface Signals (cont'd)

Name Direction Descriptions_axi_awready Output Write Address Ready: Indicates that the slave is ready to accept

an address and associated control signals:


AXI4-Lite Interface Write Address Channel: Information Signals Derived from FIFO Data Output (dout) Bus

m_axi_awaddr[m:0] Output Write Address: Gives the address of the first transfer in a writeburst transaction. The associated control signals are used todetermine the addresses of the remaining transfers in the burst.

m_axi_awprot[3:0] Output Protection Type: This signal indicates the normal, privileged, orsecure protection level of the transaction and whether thetransaction is a data access or an instruction access.

AXI4-Lite Interface Write Address Channel: Handshake Signals for FIFO Read Interface

m_axi_awvalid Output Write Address Valid: Indicates that valid write address andcontrol information are available:

• 1 = Address and control information available.• 0 = Address and control information not available.The address and control information remain stable until theaddress acknowledge signal, AWREADY, goes high.

m_axi_awready Input Write Address Ready: Indicates that the slave is ready to acceptan address and associated control signals:


The following table defines the AXI4-Lite FIFO interface signals for the Write Data Channel.

Table 17: AXI4-Lite Write Data Channel FIFO Interface Signals

Name Direction DescriptionAXI4-Lite Interface Write Data Channel: Information Signals Mapped to FIFO Data Input (din) Bus

s_axi_wdata[m-1:0] Input Write Data: Can be 8, 16, 32, 64, 128, 256 or 512 bits wide.

s_axi_wstrb[m/8-1:0] Input Write Strobes: Indicates which byte lanes to update in memory.There is one write strobe for each eight bits of the write data bus.Therefore, WSTRB[n] corresponds to WDATA[(8 × n) + 7:(8 × n)].For a 64-bit DATA, bit 0 corresponds to the least significant byteon DATA, and bit 7 corresponds to the most significant byte. Forexample:


Chapter 2: Overview



Table 17: AXI4-Lite Write Data Channel FIFO Interface Signals (cont'd)

Name Direction DescriptionAXI4-Lite Interface Write Data Channel: Handshake Signals for FIFO Write Interface

s_axi_wvalid Input Write Valid: Indicates that valid write data and strobes areavailable:

• 1 = Write data and strobes available.• 0 = Write data and strobes not available.

s_axi_wready Output Write Ready: Indicates that the slave can accept the write data:


AXI4-Lite Interface Write Data Channel: Information Signals Derived from FIFO Data Output (dout) Bus

m_axi_wdata[m-1:0] Output Write Data: Can be 8, 16, 32, 64, 128, 256 or 512 bits wide.

m_axi_wstrb[m/8-1:0] Output Write Strobes: Indicates which byte lanes to update in memory.There is one write strobe for each eight bits of the write data bus.Therefore, WSTRB[n] corresponds to WDATA[(8 × n) + 7:(8 × n)].For a 64-bit DATA, bit 0 corresponds to the least significant byteon DATA, and bit 7 corresponds to the most significant byte. Forexample:


AXI4-Lite Interface Write Data Channel: Handshake Signals for FIFO Read Interface

m_axi_wvalid Output Write Valid: Indicates that valid write data and strobes areavailable:

• 1 = Write data and strobes available• 0 = Write data and strobes not available

m_axi_wready Input Write Ready: Indicates that the slave can accept the write data:


AXI4-Lite Write Data Channel FIFO: Optional Sideband Signals

injectsbiterr_wdch Input Injects a single bit error if the ECC feature is used.

injectdbiterr_wdch Input Injects a double bit error if the ECC feature is used.

sbiterr_wdch Output Single Bit Error: Indicates that the ECC decoder detected andfixed a single-bit error.

dbiterr_wdch Output Double Bit Error: Indicates that the ECC decoder detected adouble-bit error and data in the FIFO core is corrupted.

wr_data_count_wdch[d:0] Output Write Data Count: This bus indicates the number of wordswritten into the FIFO. The count is guaranteed to neverunderreport the number of words in the FIFO, to ensure younever overflow the FIFO. The exception to this behavior is when awrite operation occurs at the rising edge of write clock, that writeoperation will only be reflected on wr_data_count at the nextrising clock edge. D = log2(FIFO depth)+1.

Chapter 2: Overview



Table 17: AXI4-Lite Write Data Channel FIFO Interface Signals (cont'd)

Name Direction Descriptionrd_data_count_wdch[d:0] Output Read Data Count: This bus indicates the number of words

available for reading in the FIFO. The count is guaranteed tonever over-report the number of words available for reading, toensure that you do not underflow the FIFO. The exception to thisbehavior is when the read operation occurs at the rising edge ofread clock, that read operation is only reflected on rd_data_countat the next rising clock edge. D = log2(FIFO depth)+1.

prog_full_wdch Output Programmable Full: This signal is asserted when the number ofwords in the FIFO is greater than or equal to the programmablethreshold. It is deasserted when the number of words in the FIFOis less than the programmable threshold.

w_prog_empty_wdch Output Programmable Empty: This signal is asserted when the numberof words in the FIFO is less than or equal to the programmablethreshold. It is deasserted when the number of words in the FIFOexceeds the programmable threshold.

The following table defines the AXI4-Lite FIFO interface signals for the Write Response Channel.

Table 18: AXI4-Lite Write Response Channel FIFO Interface Signals

Name Direction DescriptionAXI4-Lite Interface Write Response Channel: Information Signals Mapped to FIFO Data Output (dout) Bus

s_axi_bresp[1:0] Output Write Response: Indicates the status of the write transaction.The allowable responses are OKAY, EXOKAY, SLVERR, and DECERR.

AXI4-Lite Interface Write Response Channel: Handshake Signals for FIFO Read Interface

s_axi_bvalid Output Write Response Valid: Indicates that a valid write response isavailable:


s_axi_bready Input Response Ready: Indicates that the master can accept theresponse information.


AXI4-Lite Interface Write Response Channel: Information Signals Derived from FIFO Data Input (din) Bus

m_axi_bresp[1:0] Input Write response: Indicates the status of the writ

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Embedded FIFO Generator v1.0 LogiCORE IP Product Guide · 2021. 1. 15. · 2. The Embedded FIFO Generator core supports the UniSim simulation model. 3. For the supported versions