ELEN 468 Advanced Logic Design

ELEN 468 Lecture 4 1

ELEN 468Advanced Logic DesignLecture 4 Data Types and Operators


Variables Represent values of signals in physical circuit in a digital format Nets – Represent physical connectivity Registers – Abstractions of storage elements Nets and registers may be either scalars or vectors


Storage Variable Storage variable = register reg, integer, real, realtime, time Abstraction of storage element Need not correspond directly to physical storage element in circuit Static – its value is assigned under program flow


Value Assignment Explicitly – through behavioral statements Implicitly – driven by a gate A net may be assigned value explicitly only through continuous assignment A register variable may be assigned value only within a behavior


Verilog Netswire (default)triwandwortriandtrior

tri

wand/wor

triand/trior

Not recommended!


Exampletri y;bufif1(y, x, ctrl);

triand y;bufif1(y, x1, ctrl1); bufif1(y, x2, ctrl2);

ctrl

yx

ctrl1

ctrl2x1

x2y

Three-state gate, page 651


Truth Tableswire/tri 0 1 x z 0 0 x x 0 1 x 1 x 1 x x x x x z 0 1 x z

triand / wand 0 1 x z 0 0 0 0 0 1 0 1 x 1 x 0 x x x z 0 1 x z

trior/wor 0 1 x z 0 0 1 x 0 1 1 1 1 1 x x 1 x x z 0 1 x z


More Verilog Netssupply0supply1tri0tri1trireg

Vdd

supply1

supply0

Gnd

Vdd

tri1 Gnd

tri0

a b

trireg

when a = b = 0,the line maintainsits value


Net Declarationwire[7:0] data_bus; // 8-bit vector wire, data_bus[7] -> MSBwire[0:3] control_bus; // control_bus[0] -> MSBdata_bus[5], data_bus[3:5], data_bus[k+2]// access

wire scalared[7:0] bus_a;// “scalared” is defaultwire vectored[7:0] bus_b; // Individual bits may not be

referenced

wire y1, z_5; // Multiple declarationwire A = B+C, D = E+F; // Implicit continuous assignment

wand A, B, C;trireg[7:0] A;


Initial Values At time tsim = 0 Nets driven by primitives, module or continuous assignment is determined by their drivers, default value “x” Net without driver, its initial value “z” Default initial value for register -> “x”


Register Data Typesreg – stores a logic valueinteger – support computationtime – stores time as a 64-bit unsigned quantityreal – stores values as real numbersrealtime – store time values as real numbers

Assigned value only within a procedural statement, a user defined sequential primitive, task or functionA reg object may never be output of

a primitive gate the target of a continuous assignment

Undeclared identifier is assumed as a net, which is illegal within behavior


Addressing Net and Register Variables

MSB of a part-select of a register = leftmost array index LSB = rightmost array index If index of part-select is out of bounds, “x” is returned If word [7:0] = 8’b00000100 word [3:0] = 4 word [5:1] = 2

Integer array integer A[3:0];


Variables and PortsVariable

typeInput port Output port Inout port

Net Yes Yes YesRegister No Yes No

An input port is implicitly a net variable


Memories…reg[31:0] cache_memory[0:1023];reg[31:0] word_register;reg[7:0] instr_register;…word_register = cache_memory[17];…// a loop…instr_register[k] =

word_register[k+4];…

•Individual bits within a memory cannot be addressed directly•The word is fetched to a register, then bit can be accessed

Memory sizeWord size


Scope of a Variable The scope of a variable is the

module, task, function, or named procedural block (begin … end) in which it is declared


De-ReferenceTo reference a variable defined inside an instantiated module X.w X.Y.Z.w

Module A - Instance X

Module B - Instance YModule C - Instance Zwire w

wire w


Example of De-referencingmodule testbench(); reg [3:0] a, b; wire [3:0] y; adder M1 (y, a, b);

initial $monitor($time,,”%”, M1.c);endmodule

module adder(y, a, b);…wire c;…endmodule


Strings Verilog does not have type for strings A string must be stored in a register array

reg [8*num_char-1 : 0] string_holder;


Constants Declared with keyword parameter Value may not be changed during simulation

parameter width = 32, depth = 1024;parameter real_value = 6.22;parameter av_delay = (dmin + dmax)/2;


Direct Substitution of Parameters

module modXnor(y, a, b); parameter size=8, delay=15; output [size-1:0] y; input [size-1:0] a, b; wire [size-1:0] #delay y =

a~^b;endmodule module param; wire [7:0] y1; wire [3:0] y2; reg [7:0] b1, c1; reg [3:0] b2, c2; modXnor G1(y1, b1, c1); modXnor #(4,5) G2(y2, b2, c2);endmodule

Value of a constant can be changed during compilationDon’t confuse with assigning delay to primitives Module

instantiation do not have delay

Primitives do not have parameters


Indirect Substitution of Parametersmodule param; wire [7:0] y1; wire [3:0] y2; reg [7:0] b1, c1; reg [3:0] b2, c2; modXnor G1(y1, b1, c1); modXnor G2(y2, b2, c2);endmodule

module annotate; defparam param.G2.size = 4; parem.G2.delay = 5;endmodule

Declare a separate module where defparam is used with hierarchical pathname


OperatorsOperator Number of

OperandsResult

Arithmetic 2 Binary wordBitwise 2 Binary word

Reduction 1 BitLogical 2 Boolean

valueRelational 2 Boolean

valueShift 1 Binary word

Conditional 3 Expression


Arithmetic Operators 2’s complement representation MSB is sign bit For scalar and vector For nets and registers

Symbol

Operator

+ Addition- Subtraction* Multiplicatio

n/ Division% Modulus


Bitwise Operators~(101011) = 010100(010101) & (001100) = 000100(010101) ^ (001100) = 011001

Symbol Operator~ Bitwise negation& Bitwise and| Bitwise inclusive

or^ Bitwise exclusive

or~^, ^~

Bitwise exclusive nor

Shorter word will extend to the size of longer word by padding bits with “0”


Reduction Operators

Unary operatorsReturn single-bit value

Symbol Operator& Reduction and

~& Reduction nand| Reduction or

~| Reduction nor^ Reduction xor

~^, ^~

Reduction xnor

&(101011) = 0|(001100) = 1


Logical OperatorsCase equality operators detect exact bit-by-bit match, including “x” or “z”The logical equality operator is less restrictive, “x” is returned for any ambiguityVerilog is loosely typed - OK to use A&&B when A and B are vectors

A&&B returns true if both words are non-zero integers

=== can recognize ‘x’ and ‘z’ while == would return ‘x’ for ambiguity

Symbol Operator! Logical negation

&& Logical and|| Logical or

== Logical equality!= Logical

inequality=== Case equality!== Case inequality


Relational and Shift Operators

Relational operators return ‘x’ for ambiguity0xxx > 1xxx returns 1

if ( ( a < b ) && ( a >= c ) ) result = a << 3;

Relational operators Shift operators< <<

<= >>>

>=


Conditional OperatorY = ( A == B ) ? C : D;

wire [1:0] select;wire [15:0] D1, D2, D3, D4;wire [15:0] bus = (select == 2’b00) ? D1 :

(select == 2’b01) ? D2 : (select == 2’b10) ? D3 : (select == 2’b11) ? D4 : 16’bx

“z” is not allowed in conditional_expression If conditional_expression is ambiguous, both true_expression and false_expression are evaluated bitwisely according to the truth table to get the result

? : 0 1 X0 0 X X1 X 1 XX X X X


Operands A Verilog operand may be compose of Nets Registers Constants Numbers Bit-select of a net or a register Part-select of a net or a register A function call Concatenation of any of above


Operator PrecedenceOperator precedence

Operator symbol

Highest - ! ~ (unary)* / %+ - (binary)<< >>< <= > >= == != === !==& ~&^ ^~ ~^| ~|&&||

Lowest ? :

Parentheses for precaution !

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ELEN 468 Advanced Logic Design